1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 2 // All Rights Reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are 6 // met: 7 // 8 // - Redistributions of source code must retain the above copyright notice, 9 // this list of conditions and the following disclaimer. 10 // 11 // - Redistribution in binary form must reproduce the above copyright 12 // notice, this list of conditions and the following disclaimer in the 13 // documentation and/or other materials provided with the distribution. 14 // 15 // - Neither the name of Sun Microsystems or the names of contributors may 16 // be used to endorse or promote products derived from this software without 17 // specific prior written permission. 18 // 19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 31 // The original source code covered by the above license above has been 32 // modified significantly by Google Inc. 33 // Copyright 2012 the V8 project authors. All rights reserved. 34 35 36 #ifndef V8_MIPS_ASSEMBLER_MIPS_H_ 37 #define V8_MIPS_ASSEMBLER_MIPS_H_ 38 39 #include <stdio.h> 40 41 #include <set> 42 43 #include "src/assembler.h" 44 #include "src/mips64/constants-mips64.h" 45 46 namespace v8 { 47 namespace internal { 48 49 // clang-format off 50 #define GENERAL_REGISTERS(V) \ 51 V(zero_reg) V(at) V(v0) V(v1) V(a0) V(a1) V(a2) V(a3) \ 52 V(a4) V(a5) V(a6) V(a7) V(t0) V(t1) V(t2) V(t3) \ 53 V(s0) V(s1) V(s2) V(s3) V(s4) V(s5) V(s6) V(s7) V(t8) V(t9) \ 54 V(k0) V(k1) V(gp) V(sp) V(fp) V(ra) 55 56 #define ALLOCATABLE_GENERAL_REGISTERS(V) \ 57 V(v0) V(v1) V(a0) V(a1) V(a2) V(a3) \ 58 V(a4) V(a5) V(a6) V(a7) V(t0) V(t1) V(t2) V(s7) 59 60 #define DOUBLE_REGISTERS(V) \ 61 V(f0) V(f1) V(f2) V(f3) V(f4) V(f5) V(f6) V(f7) \ 62 V(f8) V(f9) V(f10) V(f11) V(f12) V(f13) V(f14) V(f15) \ 63 V(f16) V(f17) V(f18) V(f19) V(f20) V(f21) V(f22) V(f23) \ 64 V(f24) V(f25) V(f26) V(f27) V(f28) V(f29) V(f30) V(f31) 65 66 #define FLOAT_REGISTERS DOUBLE_REGISTERS 67 #define SIMD128_REGISTERS DOUBLE_REGISTERS 68 69 #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ 70 V(f0) V(f2) V(f4) V(f6) V(f8) V(f10) V(f12) V(f14) \ 71 V(f16) V(f18) V(f20) V(f22) V(f24) V(f26) 72 // clang-format on 73 74 // CPU Registers. 75 // 76 // 1) We would prefer to use an enum, but enum values are assignment- 77 // compatible with int, which has caused code-generation bugs. 78 // 79 // 2) We would prefer to use a class instead of a struct but we don't like 80 // the register initialization to depend on the particular initialization 81 // order (which appears to be different on OS X, Linux, and Windows for the 82 // installed versions of C++ we tried). Using a struct permits C-style 83 // "initialization". Also, the Register objects cannot be const as this 84 // forces initialization stubs in MSVC, making us dependent on initialization 85 // order. 86 // 87 // 3) By not using an enum, we are possibly preventing the compiler from 88 // doing certain constant folds, which may significantly reduce the 89 // code generated for some assembly instructions (because they boil down 90 // to a few constants). If this is a problem, we could change the code 91 // such that we use an enum in optimized mode, and the struct in debug 92 // mode. This way we get the compile-time error checking in debug mode 93 // and best performance in optimized code. 94 95 96 // ----------------------------------------------------------------------------- 97 // Implementation of Register and FPURegister. 98 99 struct Register { 100 static const int kCpRegister = 23; // cp (s7) is the 23rd register. 101 102 #if defined(V8_TARGET_LITTLE_ENDIAN) 103 static const int kMantissaOffset = 0; 104 static const int kExponentOffset = 4; 105 #elif defined(V8_TARGET_BIG_ENDIAN) 106 static const int kMantissaOffset = 4; 107 static const int kExponentOffset = 0; 108 #else 109 #error Unknown endianness 110 #endif 111 112 enum Code { 113 #define REGISTER_CODE(R) kCode_##R, 114 GENERAL_REGISTERS(REGISTER_CODE) 115 #undef REGISTER_CODE 116 kAfterLast, 117 kCode_no_reg = -1 118 }; 119 120 static const int kNumRegisters = Code::kAfterLast; 121 122 static Register from_code(int code) { 123 DCHECK(code >= 0); 124 DCHECK(code < kNumRegisters); 125 Register r = { code }; 126 return r; 127 } 128 129 bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; } 130 bool is(Register reg) const { return reg_code == reg.reg_code; } 131 int code() const { 132 DCHECK(is_valid()); 133 return reg_code; 134 } 135 int bit() const { 136 DCHECK(is_valid()); 137 return 1 << reg_code; 138 } 139 140 // Unfortunately we can't make this private in a struct. 141 int reg_code; 142 }; 143 144 // s7: context register 145 // s3: lithium scratch 146 // s4: lithium scratch2 147 #define DECLARE_REGISTER(R) const Register R = {Register::kCode_##R}; 148 GENERAL_REGISTERS(DECLARE_REGISTER) 149 #undef DECLARE_REGISTER 150 const Register no_reg = {Register::kCode_no_reg}; 151 152 153 int ToNumber(Register reg); 154 155 Register ToRegister(int num); 156 157 static const bool kSimpleFPAliasing = true; 158 static const bool kSimdMaskRegisters = false; 159 160 // Coprocessor register. 161 struct FPURegister { 162 enum Code { 163 #define REGISTER_CODE(R) kCode_##R, 164 DOUBLE_REGISTERS(REGISTER_CODE) 165 #undef REGISTER_CODE 166 kAfterLast, 167 kCode_no_reg = -1 168 }; 169 170 static const int kMaxNumRegisters = Code::kAfterLast; 171 172 inline static int NumRegisters(); 173 174 // TODO(plind): Warning, inconsistent numbering here. kNumFPURegisters refers 175 // to number of 32-bit FPU regs, but kNumAllocatableRegisters refers to 176 // number of Double regs (64-bit regs, or FPU-reg-pairs). 177 178 bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; } 179 bool is(FPURegister reg) const { return reg_code == reg.reg_code; } 180 FPURegister low() const { 181 // TODO(plind): Create DCHECK for FR=0 mode. This usage suspect for FR=1. 182 // Find low reg of a Double-reg pair, which is the reg itself. 183 DCHECK(reg_code % 2 == 0); // Specified Double reg must be even. 184 FPURegister reg; 185 reg.reg_code = reg_code; 186 DCHECK(reg.is_valid()); 187 return reg; 188 } 189 FPURegister high() const { 190 // TODO(plind): Create DCHECK for FR=0 mode. This usage illegal in FR=1. 191 // Find high reg of a Doubel-reg pair, which is reg + 1. 192 DCHECK(reg_code % 2 == 0); // Specified Double reg must be even. 193 FPURegister reg; 194 reg.reg_code = reg_code + 1; 195 DCHECK(reg.is_valid()); 196 return reg; 197 } 198 199 int code() const { 200 DCHECK(is_valid()); 201 return reg_code; 202 } 203 int bit() const { 204 DCHECK(is_valid()); 205 return 1 << reg_code; 206 } 207 208 static FPURegister from_code(int code) { 209 FPURegister r = {code}; 210 return r; 211 } 212 void setcode(int f) { 213 reg_code = f; 214 DCHECK(is_valid()); 215 } 216 // Unfortunately we can't make this private in a struct. 217 int reg_code; 218 }; 219 220 // A few double registers are reserved: one as a scratch register and one to 221 // hold 0.0. 222 // f28: 0.0 223 // f30: scratch register. 224 225 // V8 now supports the O32 ABI, and the FPU Registers are organized as 32 226 // 32-bit registers, f0 through f31. When used as 'double' they are used 227 // in pairs, starting with the even numbered register. So a double operation 228 // on f0 really uses f0 and f1. 229 // (Modern mips hardware also supports 32 64-bit registers, via setting 230 // (privileged) Status Register FR bit to 1. This is used by the N32 ABI, 231 // but it is not in common use. Someday we will want to support this in v8.) 232 233 // For O32 ABI, Floats and Doubles refer to same set of 32 32-bit registers. 234 typedef FPURegister FloatRegister; 235 236 typedef FPURegister DoubleRegister; 237 238 // TODO(mips64) Define SIMD registers. 239 typedef FPURegister Simd128Register; 240 241 const DoubleRegister no_freg = {-1}; 242 243 const DoubleRegister f0 = {0}; // Return value in hard float mode. 244 const DoubleRegister f1 = {1}; 245 const DoubleRegister f2 = {2}; 246 const DoubleRegister f3 = {3}; 247 const DoubleRegister f4 = {4}; 248 const DoubleRegister f5 = {5}; 249 const DoubleRegister f6 = {6}; 250 const DoubleRegister f7 = {7}; 251 const DoubleRegister f8 = {8}; 252 const DoubleRegister f9 = {9}; 253 const DoubleRegister f10 = {10}; 254 const DoubleRegister f11 = {11}; 255 const DoubleRegister f12 = {12}; // Arg 0 in hard float mode. 256 const DoubleRegister f13 = {13}; 257 const DoubleRegister f14 = {14}; // Arg 1 in hard float mode. 258 const DoubleRegister f15 = {15}; 259 const DoubleRegister f16 = {16}; 260 const DoubleRegister f17 = {17}; 261 const DoubleRegister f18 = {18}; 262 const DoubleRegister f19 = {19}; 263 const DoubleRegister f20 = {20}; 264 const DoubleRegister f21 = {21}; 265 const DoubleRegister f22 = {22}; 266 const DoubleRegister f23 = {23}; 267 const DoubleRegister f24 = {24}; 268 const DoubleRegister f25 = {25}; 269 const DoubleRegister f26 = {26}; 270 const DoubleRegister f27 = {27}; 271 const DoubleRegister f28 = {28}; 272 const DoubleRegister f29 = {29}; 273 const DoubleRegister f30 = {30}; 274 const DoubleRegister f31 = {31}; 275 276 // Register aliases. 277 // cp is assumed to be a callee saved register. 278 // Defined using #define instead of "static const Register&" because Clang 279 // complains otherwise when a compilation unit that includes this header 280 // doesn't use the variables. 281 #define kRootRegister s6 282 #define cp s7 283 #define kLithiumScratchReg s3 284 #define kLithiumScratchReg2 s4 285 #define kLithiumScratchDouble f30 286 #define kDoubleRegZero f28 287 // Used on mips64r6 for compare operations. 288 // We use the last non-callee saved odd register for N64 ABI 289 #define kDoubleCompareReg f23 290 291 // FPU (coprocessor 1) control registers. 292 // Currently only FCSR (#31) is implemented. 293 struct FPUControlRegister { 294 bool is_valid() const { return reg_code == kFCSRRegister; } 295 bool is(FPUControlRegister creg) const { return reg_code == creg.reg_code; } 296 int code() const { 297 DCHECK(is_valid()); 298 return reg_code; 299 } 300 int bit() const { 301 DCHECK(is_valid()); 302 return 1 << reg_code; 303 } 304 void setcode(int f) { 305 reg_code = f; 306 DCHECK(is_valid()); 307 } 308 // Unfortunately we can't make this private in a struct. 309 int reg_code; 310 }; 311 312 const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister }; 313 const FPUControlRegister FCSR = { kFCSRRegister }; 314 315 // ----------------------------------------------------------------------------- 316 // Machine instruction Operands. 317 const int kSmiShift = kSmiTagSize + kSmiShiftSize; 318 const uint64_t kSmiShiftMask = (1UL << kSmiShift) - 1; 319 // Class Operand represents a shifter operand in data processing instructions. 320 class Operand BASE_EMBEDDED { 321 public: 322 // Immediate. 323 INLINE(explicit Operand(int64_t immediate, 324 RelocInfo::Mode rmode = RelocInfo::NONE64)); 325 INLINE(explicit Operand(const ExternalReference& f)); 326 INLINE(explicit Operand(const char* s)); 327 INLINE(explicit Operand(Object** opp)); 328 INLINE(explicit Operand(Context** cpp)); 329 explicit Operand(Handle<Object> handle); 330 INLINE(explicit Operand(Smi* value)); 331 332 // Register. 333 INLINE(explicit Operand(Register rm)); 334 335 // Return true if this is a register operand. 336 INLINE(bool is_reg() const); 337 338 inline int64_t immediate() const { 339 DCHECK(!is_reg()); 340 return imm64_; 341 } 342 343 Register rm() const { return rm_; } 344 345 private: 346 Register rm_; 347 int64_t imm64_; // Valid if rm_ == no_reg. 348 RelocInfo::Mode rmode_; 349 350 friend class Assembler; 351 friend class MacroAssembler; 352 }; 353 354 355 // On MIPS we have only one adressing mode with base_reg + offset. 356 // Class MemOperand represents a memory operand in load and store instructions. 357 class MemOperand : public Operand { 358 public: 359 // Immediate value attached to offset. 360 enum OffsetAddend { 361 offset_minus_one = -1, 362 offset_zero = 0 363 }; 364 365 explicit MemOperand(Register rn, int32_t offset = 0); 366 explicit MemOperand(Register rn, int32_t unit, int32_t multiplier, 367 OffsetAddend offset_addend = offset_zero); 368 int32_t offset() const { return offset_; } 369 370 bool OffsetIsInt16Encodable() const { 371 return is_int16(offset_); 372 } 373 374 private: 375 int32_t offset_; 376 377 friend class Assembler; 378 }; 379 380 381 class Assembler : public AssemblerBase { 382 public: 383 // Create an assembler. Instructions and relocation information are emitted 384 // into a buffer, with the instructions starting from the beginning and the 385 // relocation information starting from the end of the buffer. See CodeDesc 386 // for a detailed comment on the layout (globals.h). 387 // 388 // If the provided buffer is NULL, the assembler allocates and grows its own 389 // buffer, and buffer_size determines the initial buffer size. The buffer is 390 // owned by the assembler and deallocated upon destruction of the assembler. 391 // 392 // If the provided buffer is not NULL, the assembler uses the provided buffer 393 // for code generation and assumes its size to be buffer_size. If the buffer 394 // is too small, a fatal error occurs. No deallocation of the buffer is done 395 // upon destruction of the assembler. 396 Assembler(Isolate* isolate, void* buffer, int buffer_size); 397 virtual ~Assembler() { } 398 399 // GetCode emits any pending (non-emitted) code and fills the descriptor 400 // desc. GetCode() is idempotent; it returns the same result if no other 401 // Assembler functions are invoked in between GetCode() calls. 402 void GetCode(CodeDesc* desc); 403 404 // Label operations & relative jumps (PPUM Appendix D). 405 // 406 // Takes a branch opcode (cc) and a label (L) and generates 407 // either a backward branch or a forward branch and links it 408 // to the label fixup chain. Usage: 409 // 410 // Label L; // unbound label 411 // j(cc, &L); // forward branch to unbound label 412 // bind(&L); // bind label to the current pc 413 // j(cc, &L); // backward branch to bound label 414 // bind(&L); // illegal: a label may be bound only once 415 // 416 // Note: The same Label can be used for forward and backward branches 417 // but it may be bound only once. 418 void bind(Label* L); // Binds an unbound label L to current code position. 419 420 enum OffsetSize : int { kOffset26 = 26, kOffset21 = 21, kOffset16 = 16 }; 421 422 // Determines if Label is bound and near enough so that branch instruction 423 // can be used to reach it, instead of jump instruction. 424 bool is_near(Label* L); 425 bool is_near(Label* L, OffsetSize bits); 426 bool is_near_branch(Label* L); 427 inline bool is_near_pre_r6(Label* L) { 428 DCHECK(!(kArchVariant == kMips64r6)); 429 return pc_offset() - L->pos() < kMaxBranchOffset - 4 * kInstrSize; 430 } 431 inline bool is_near_r6(Label* L) { 432 DCHECK(kArchVariant == kMips64r6); 433 return pc_offset() - L->pos() < kMaxCompactBranchOffset - 4 * kInstrSize; 434 } 435 436 int BranchOffset(Instr instr); 437 438 // Returns the branch offset to the given label from the current code 439 // position. Links the label to the current position if it is still unbound. 440 // Manages the jump elimination optimization if the second parameter is true. 441 int32_t branch_offset_helper(Label* L, OffsetSize bits); 442 inline int32_t branch_offset(Label* L) { 443 return branch_offset_helper(L, OffsetSize::kOffset16); 444 } 445 inline int32_t branch_offset21(Label* L) { 446 return branch_offset_helper(L, OffsetSize::kOffset21); 447 } 448 inline int32_t branch_offset26(Label* L) { 449 return branch_offset_helper(L, OffsetSize::kOffset26); 450 } 451 inline int32_t shifted_branch_offset(Label* L) { 452 return branch_offset(L) >> 2; 453 } 454 inline int32_t shifted_branch_offset21(Label* L) { 455 return branch_offset21(L) >> 2; 456 } 457 inline int32_t shifted_branch_offset26(Label* L) { 458 return branch_offset26(L) >> 2; 459 } 460 uint64_t jump_address(Label* L); 461 uint64_t jump_offset(Label* L); 462 463 // Puts a labels target address at the given position. 464 // The high 8 bits are set to zero. 465 void label_at_put(Label* L, int at_offset); 466 467 // Read/Modify the code target address in the branch/call instruction at pc. 468 static Address target_address_at(Address pc); 469 static void set_target_address_at( 470 Isolate* isolate, Address pc, Address target, 471 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED); 472 // On MIPS there is no Constant Pool so we skip that parameter. 473 INLINE(static Address target_address_at(Address pc, Address constant_pool)) { 474 return target_address_at(pc); 475 } 476 INLINE(static void set_target_address_at( 477 Isolate* isolate, Address pc, Address constant_pool, Address target, 478 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED)) { 479 set_target_address_at(isolate, pc, target, icache_flush_mode); 480 } 481 INLINE(static Address target_address_at(Address pc, Code* code)); 482 INLINE(static void set_target_address_at( 483 Isolate* isolate, Address pc, Code* code, Address target, 484 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED)); 485 486 // Return the code target address at a call site from the return address 487 // of that call in the instruction stream. 488 inline static Address target_address_from_return_address(Address pc); 489 490 static void JumpLabelToJumpRegister(Address pc); 491 492 static void QuietNaN(HeapObject* nan); 493 494 // This sets the branch destination (which gets loaded at the call address). 495 // This is for calls and branches within generated code. The serializer 496 // has already deserialized the lui/ori instructions etc. 497 inline static void deserialization_set_special_target_at( 498 Isolate* isolate, Address instruction_payload, Code* code, 499 Address target) { 500 set_target_address_at( 501 isolate, 502 instruction_payload - kInstructionsFor64BitConstant * kInstrSize, code, 503 target); 504 } 505 506 // This sets the internal reference at the pc. 507 inline static void deserialization_set_target_internal_reference_at( 508 Isolate* isolate, Address pc, Address target, 509 RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE); 510 511 // Size of an instruction. 512 static const int kInstrSize = sizeof(Instr); 513 514 // Difference between address of current opcode and target address offset. 515 static const int kBranchPCOffset = 4; 516 517 // Here we are patching the address in the LUI/ORI instruction pair. 518 // These values are used in the serialization process and must be zero for 519 // MIPS platform, as Code, Embedded Object or External-reference pointers 520 // are split across two consecutive instructions and don't exist separately 521 // in the code, so the serializer should not step forwards in memory after 522 // a target is resolved and written. 523 static const int kSpecialTargetSize = 0; 524 525 // Number of consecutive instructions used to store 32bit/64bit constant. 526 // This constant was used in RelocInfo::target_address_address() function 527 // to tell serializer address of the instruction that follows 528 // LUI/ORI instruction pair. 529 static const int kInstructionsFor32BitConstant = 2; 530 static const int kInstructionsFor64BitConstant = 4; 531 532 // Distance between the instruction referring to the address of the call 533 // target and the return address. 534 #ifdef _MIPS_ARCH_MIPS64R6 535 static const int kCallTargetAddressOffset = 5 * kInstrSize; 536 #else 537 static const int kCallTargetAddressOffset = 6 * kInstrSize; 538 #endif 539 540 // Distance between start of patched debug break slot and the emitted address 541 // to jump to. 542 static const int kPatchDebugBreakSlotAddressOffset = 6 * kInstrSize; 543 544 // Difference between address of current opcode and value read from pc 545 // register. 546 static const int kPcLoadDelta = 4; 547 548 #ifdef _MIPS_ARCH_MIPS64R6 549 static const int kDebugBreakSlotInstructions = 5; 550 #else 551 static const int kDebugBreakSlotInstructions = 6; 552 #endif 553 static const int kDebugBreakSlotLength = 554 kDebugBreakSlotInstructions * kInstrSize; 555 556 // Max offset for instructions with 16-bit offset field 557 static const int kMaxBranchOffset = (1 << (18 - 1)) - 1; 558 559 // Max offset for compact branch instructions with 26-bit offset field 560 static const int kMaxCompactBranchOffset = (1 << (28 - 1)) - 1; 561 562 static const int kTrampolineSlotsSize = 2 * kInstrSize; 563 564 // --------------------------------------------------------------------------- 565 // Code generation. 566 567 // Insert the smallest number of nop instructions 568 // possible to align the pc offset to a multiple 569 // of m. m must be a power of 2 (>= 4). 570 void Align(int m); 571 // Insert the smallest number of zero bytes possible to align the pc offset 572 // to a mulitple of m. m must be a power of 2 (>= 2). 573 void DataAlign(int m); 574 // Aligns code to something that's optimal for a jump target for the platform. 575 void CodeTargetAlign(); 576 577 // Different nop operations are used by the code generator to detect certain 578 // states of the generated code. 579 enum NopMarkerTypes { 580 NON_MARKING_NOP = 0, 581 DEBUG_BREAK_NOP, 582 // IC markers. 583 PROPERTY_ACCESS_INLINED, 584 PROPERTY_ACCESS_INLINED_CONTEXT, 585 PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE, 586 // Helper values. 587 LAST_CODE_MARKER, 588 FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED, 589 // Code aging 590 CODE_AGE_MARKER_NOP = 6, 591 CODE_AGE_SEQUENCE_NOP 592 }; 593 594 // Type == 0 is the default non-marking nop. For mips this is a 595 // sll(zero_reg, zero_reg, 0). We use rt_reg == at for non-zero 596 // marking, to avoid conflict with ssnop and ehb instructions. 597 void nop(unsigned int type = 0) { 598 DCHECK(type < 32); 599 Register nop_rt_reg = (type == 0) ? zero_reg : at; 600 sll(zero_reg, nop_rt_reg, type, true); 601 } 602 603 604 // --------Branch-and-jump-instructions---------- 605 // We don't use likely variant of instructions. 606 void b(int16_t offset); 607 inline void b(Label* L) { b(shifted_branch_offset(L)); } 608 void bal(int16_t offset); 609 inline void bal(Label* L) { bal(shifted_branch_offset(L)); } 610 void bc(int32_t offset); 611 inline void bc(Label* L) { bc(shifted_branch_offset26(L)); } 612 void balc(int32_t offset); 613 inline void balc(Label* L) { balc(shifted_branch_offset26(L)); } 614 615 void beq(Register rs, Register rt, int16_t offset); 616 inline void beq(Register rs, Register rt, Label* L) { 617 beq(rs, rt, shifted_branch_offset(L)); 618 } 619 void bgez(Register rs, int16_t offset); 620 void bgezc(Register rt, int16_t offset); 621 inline void bgezc(Register rt, Label* L) { 622 bgezc(rt, shifted_branch_offset(L)); 623 } 624 void bgeuc(Register rs, Register rt, int16_t offset); 625 inline void bgeuc(Register rs, Register rt, Label* L) { 626 bgeuc(rs, rt, shifted_branch_offset(L)); 627 } 628 void bgec(Register rs, Register rt, int16_t offset); 629 inline void bgec(Register rs, Register rt, Label* L) { 630 bgec(rs, rt, shifted_branch_offset(L)); 631 } 632 void bgezal(Register rs, int16_t offset); 633 void bgezalc(Register rt, int16_t offset); 634 inline void bgezalc(Register rt, Label* L) { 635 bgezalc(rt, shifted_branch_offset(L)); 636 } 637 void bgezall(Register rs, int16_t offset); 638 inline void bgezall(Register rs, Label* L) { 639 bgezall(rs, branch_offset(L) >> 2); 640 } 641 void bgtz(Register rs, int16_t offset); 642 void bgtzc(Register rt, int16_t offset); 643 inline void bgtzc(Register rt, Label* L) { 644 bgtzc(rt, shifted_branch_offset(L)); 645 } 646 void blez(Register rs, int16_t offset); 647 void blezc(Register rt, int16_t offset); 648 inline void blezc(Register rt, Label* L) { 649 blezc(rt, shifted_branch_offset(L)); 650 } 651 void bltz(Register rs, int16_t offset); 652 void bltzc(Register rt, int16_t offset); 653 inline void bltzc(Register rt, Label* L) { 654 bltzc(rt, shifted_branch_offset(L)); 655 } 656 void bltuc(Register rs, Register rt, int16_t offset); 657 inline void bltuc(Register rs, Register rt, Label* L) { 658 bltuc(rs, rt, shifted_branch_offset(L)); 659 } 660 void bltc(Register rs, Register rt, int16_t offset); 661 inline void bltc(Register rs, Register rt, Label* L) { 662 bltc(rs, rt, shifted_branch_offset(L)); 663 } 664 void bltzal(Register rs, int16_t offset); 665 void blezalc(Register rt, int16_t offset); 666 inline void blezalc(Register rt, Label* L) { 667 blezalc(rt, shifted_branch_offset(L)); 668 } 669 void bltzalc(Register rt, int16_t offset); 670 inline void bltzalc(Register rt, Label* L) { 671 bltzalc(rt, shifted_branch_offset(L)); 672 } 673 void bgtzalc(Register rt, int16_t offset); 674 inline void bgtzalc(Register rt, Label* L) { 675 bgtzalc(rt, shifted_branch_offset(L)); 676 } 677 void beqzalc(Register rt, int16_t offset); 678 inline void beqzalc(Register rt, Label* L) { 679 beqzalc(rt, shifted_branch_offset(L)); 680 } 681 void beqc(Register rs, Register rt, int16_t offset); 682 inline void beqc(Register rs, Register rt, Label* L) { 683 beqc(rs, rt, shifted_branch_offset(L)); 684 } 685 void beqzc(Register rs, int32_t offset); 686 inline void beqzc(Register rs, Label* L) { 687 beqzc(rs, shifted_branch_offset21(L)); 688 } 689 void bnezalc(Register rt, int16_t offset); 690 inline void bnezalc(Register rt, Label* L) { 691 bnezalc(rt, shifted_branch_offset(L)); 692 } 693 void bnec(Register rs, Register rt, int16_t offset); 694 inline void bnec(Register rs, Register rt, Label* L) { 695 bnec(rs, rt, shifted_branch_offset(L)); 696 } 697 void bnezc(Register rt, int32_t offset); 698 inline void bnezc(Register rt, Label* L) { 699 bnezc(rt, shifted_branch_offset21(L)); 700 } 701 void bne(Register rs, Register rt, int16_t offset); 702 inline void bne(Register rs, Register rt, Label* L) { 703 bne(rs, rt, shifted_branch_offset(L)); 704 } 705 void bovc(Register rs, Register rt, int16_t offset); 706 inline void bovc(Register rs, Register rt, Label* L) { 707 bovc(rs, rt, shifted_branch_offset(L)); 708 } 709 void bnvc(Register rs, Register rt, int16_t offset); 710 inline void bnvc(Register rs, Register rt, Label* L) { 711 bnvc(rs, rt, shifted_branch_offset(L)); 712 } 713 714 // Never use the int16_t b(l)cond version with a branch offset 715 // instead of using the Label* version. 716 717 // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits. 718 void j(int64_t target); 719 void jal(int64_t target); 720 void j(Label* target); 721 void jal(Label* target); 722 void jalr(Register rs, Register rd = ra); 723 void jr(Register target); 724 void jic(Register rt, int16_t offset); 725 void jialc(Register rt, int16_t offset); 726 727 728 // -------Data-processing-instructions--------- 729 730 // Arithmetic. 731 void addu(Register rd, Register rs, Register rt); 732 void subu(Register rd, Register rs, Register rt); 733 734 void div(Register rs, Register rt); 735 void divu(Register rs, Register rt); 736 void ddiv(Register rs, Register rt); 737 void ddivu(Register rs, Register rt); 738 void div(Register rd, Register rs, Register rt); 739 void divu(Register rd, Register rs, Register rt); 740 void ddiv(Register rd, Register rs, Register rt); 741 void ddivu(Register rd, Register rs, Register rt); 742 void mod(Register rd, Register rs, Register rt); 743 void modu(Register rd, Register rs, Register rt); 744 void dmod(Register rd, Register rs, Register rt); 745 void dmodu(Register rd, Register rs, Register rt); 746 747 void mul(Register rd, Register rs, Register rt); 748 void muh(Register rd, Register rs, Register rt); 749 void mulu(Register rd, Register rs, Register rt); 750 void muhu(Register rd, Register rs, Register rt); 751 void mult(Register rs, Register rt); 752 void multu(Register rs, Register rt); 753 void dmul(Register rd, Register rs, Register rt); 754 void dmuh(Register rd, Register rs, Register rt); 755 void dmulu(Register rd, Register rs, Register rt); 756 void dmuhu(Register rd, Register rs, Register rt); 757 void daddu(Register rd, Register rs, Register rt); 758 void dsubu(Register rd, Register rs, Register rt); 759 void dmult(Register rs, Register rt); 760 void dmultu(Register rs, Register rt); 761 762 void addiu(Register rd, Register rs, int32_t j); 763 void daddiu(Register rd, Register rs, int32_t j); 764 765 // Logical. 766 void and_(Register rd, Register rs, Register rt); 767 void or_(Register rd, Register rs, Register rt); 768 void xor_(Register rd, Register rs, Register rt); 769 void nor(Register rd, Register rs, Register rt); 770 771 void andi(Register rd, Register rs, int32_t j); 772 void ori(Register rd, Register rs, int32_t j); 773 void xori(Register rd, Register rs, int32_t j); 774 void lui(Register rd, int32_t j); 775 void aui(Register rt, Register rs, int32_t j); 776 void daui(Register rt, Register rs, int32_t j); 777 void dahi(Register rs, int32_t j); 778 void dati(Register rs, int32_t j); 779 780 // Shifts. 781 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop 782 // and may cause problems in normal code. coming_from_nop makes sure this 783 // doesn't happen. 784 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false); 785 void sllv(Register rd, Register rt, Register rs); 786 void srl(Register rd, Register rt, uint16_t sa); 787 void srlv(Register rd, Register rt, Register rs); 788 void sra(Register rt, Register rd, uint16_t sa); 789 void srav(Register rt, Register rd, Register rs); 790 void rotr(Register rd, Register rt, uint16_t sa); 791 void rotrv(Register rd, Register rt, Register rs); 792 void dsll(Register rd, Register rt, uint16_t sa); 793 void dsllv(Register rd, Register rt, Register rs); 794 void dsrl(Register rd, Register rt, uint16_t sa); 795 void dsrlv(Register rd, Register rt, Register rs); 796 void drotr(Register rd, Register rt, uint16_t sa); 797 void drotr32(Register rd, Register rt, uint16_t sa); 798 void drotrv(Register rd, Register rt, Register rs); 799 void dsra(Register rt, Register rd, uint16_t sa); 800 void dsrav(Register rd, Register rt, Register rs); 801 void dsll32(Register rt, Register rd, uint16_t sa); 802 void dsrl32(Register rt, Register rd, uint16_t sa); 803 void dsra32(Register rt, Register rd, uint16_t sa); 804 805 // ------------Memory-instructions------------- 806 807 void lb(Register rd, const MemOperand& rs); 808 void lbu(Register rd, const MemOperand& rs); 809 void lh(Register rd, const MemOperand& rs); 810 void lhu(Register rd, const MemOperand& rs); 811 void lw(Register rd, const MemOperand& rs); 812 void lwu(Register rd, const MemOperand& rs); 813 void lwl(Register rd, const MemOperand& rs); 814 void lwr(Register rd, const MemOperand& rs); 815 void sb(Register rd, const MemOperand& rs); 816 void sh(Register rd, const MemOperand& rs); 817 void sw(Register rd, const MemOperand& rs); 818 void swl(Register rd, const MemOperand& rs); 819 void swr(Register rd, const MemOperand& rs); 820 void ldl(Register rd, const MemOperand& rs); 821 void ldr(Register rd, const MemOperand& rs); 822 void sdl(Register rd, const MemOperand& rs); 823 void sdr(Register rd, const MemOperand& rs); 824 void ld(Register rd, const MemOperand& rs); 825 void sd(Register rd, const MemOperand& rs); 826 827 828 // ---------PC-Relative-instructions----------- 829 830 void addiupc(Register rs, int32_t imm19); 831 void lwpc(Register rs, int32_t offset19); 832 void lwupc(Register rs, int32_t offset19); 833 void ldpc(Register rs, int32_t offset18); 834 void auipc(Register rs, int16_t imm16); 835 void aluipc(Register rs, int16_t imm16); 836 837 838 // ----------------Prefetch-------------------- 839 840 void pref(int32_t hint, const MemOperand& rs); 841 842 843 // -------------Misc-instructions-------------- 844 845 // Break / Trap instructions. 846 void break_(uint32_t code, bool break_as_stop = false); 847 void stop(const char* msg, uint32_t code = kMaxStopCode); 848 void tge(Register rs, Register rt, uint16_t code); 849 void tgeu(Register rs, Register rt, uint16_t code); 850 void tlt(Register rs, Register rt, uint16_t code); 851 void tltu(Register rs, Register rt, uint16_t code); 852 void teq(Register rs, Register rt, uint16_t code); 853 void tne(Register rs, Register rt, uint16_t code); 854 855 // Memory barrier instruction. 856 void sync(); 857 858 // Move from HI/LO register. 859 void mfhi(Register rd); 860 void mflo(Register rd); 861 862 // Set on less than. 863 void slt(Register rd, Register rs, Register rt); 864 void sltu(Register rd, Register rs, Register rt); 865 void slti(Register rd, Register rs, int32_t j); 866 void sltiu(Register rd, Register rs, int32_t j); 867 868 // Conditional move. 869 void movz(Register rd, Register rs, Register rt); 870 void movn(Register rd, Register rs, Register rt); 871 void movt(Register rd, Register rs, uint16_t cc = 0); 872 void movf(Register rd, Register rs, uint16_t cc = 0); 873 874 void sel(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 875 void sel_s(FPURegister fd, FPURegister fs, FPURegister ft); 876 void sel_d(FPURegister fd, FPURegister fs, FPURegister ft); 877 void seleqz(Register rd, Register rs, Register rt); 878 void seleqz(SecondaryField fmt, FPURegister fd, FPURegister fs, 879 FPURegister ft); 880 void selnez(Register rs, Register rt, Register rd); 881 void selnez(SecondaryField fmt, FPURegister fd, FPURegister fs, 882 FPURegister ft); 883 void seleqz_d(FPURegister fd, FPURegister fs, FPURegister ft); 884 void seleqz_s(FPURegister fd, FPURegister fs, FPURegister ft); 885 void selnez_d(FPURegister fd, FPURegister fs, FPURegister ft); 886 void selnez_s(FPURegister fd, FPURegister fs, FPURegister ft); 887 888 void movz_s(FPURegister fd, FPURegister fs, Register rt); 889 void movz_d(FPURegister fd, FPURegister fs, Register rt); 890 void movt_s(FPURegister fd, FPURegister fs, uint16_t cc = 0); 891 void movt_d(FPURegister fd, FPURegister fs, uint16_t cc = 0); 892 void movf_s(FPURegister fd, FPURegister fs, uint16_t cc = 0); 893 void movf_d(FPURegister fd, FPURegister fs, uint16_t cc = 0); 894 void movn_s(FPURegister fd, FPURegister fs, Register rt); 895 void movn_d(FPURegister fd, FPURegister fs, Register rt); 896 // Bit twiddling. 897 void clz(Register rd, Register rs); 898 void dclz(Register rd, Register rs); 899 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size); 900 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size); 901 void dext_(Register rt, Register rs, uint16_t pos, uint16_t size); 902 void dextm(Register rt, Register rs, uint16_t pos, uint16_t size); 903 void dextu(Register rt, Register rs, uint16_t pos, uint16_t size); 904 void dins_(Register rt, Register rs, uint16_t pos, uint16_t size); 905 void bitswap(Register rd, Register rt); 906 void dbitswap(Register rd, Register rt); 907 void align(Register rd, Register rs, Register rt, uint8_t bp); 908 void dalign(Register rd, Register rs, Register rt, uint8_t bp); 909 910 void wsbh(Register rd, Register rt); 911 void dsbh(Register rd, Register rt); 912 void dshd(Register rd, Register rt); 913 void seh(Register rd, Register rt); 914 void seb(Register rd, Register rt); 915 916 // --------Coprocessor-instructions---------------- 917 918 // Load, store, and move. 919 void lwc1(FPURegister fd, const MemOperand& src); 920 void ldc1(FPURegister fd, const MemOperand& src); 921 922 void swc1(FPURegister fs, const MemOperand& dst); 923 void sdc1(FPURegister fs, const MemOperand& dst); 924 925 void mtc1(Register rt, FPURegister fs); 926 void mthc1(Register rt, FPURegister fs); 927 void dmtc1(Register rt, FPURegister fs); 928 929 void mfc1(Register rt, FPURegister fs); 930 void mfhc1(Register rt, FPURegister fs); 931 void dmfc1(Register rt, FPURegister fs); 932 933 void ctc1(Register rt, FPUControlRegister fs); 934 void cfc1(Register rt, FPUControlRegister fs); 935 936 // Arithmetic. 937 void add_s(FPURegister fd, FPURegister fs, FPURegister ft); 938 void add_d(FPURegister fd, FPURegister fs, FPURegister ft); 939 void sub_s(FPURegister fd, FPURegister fs, FPURegister ft); 940 void sub_d(FPURegister fd, FPURegister fs, FPURegister ft); 941 void mul_s(FPURegister fd, FPURegister fs, FPURegister ft); 942 void mul_d(FPURegister fd, FPURegister fs, FPURegister ft); 943 void madd_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 944 void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 945 void msub_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 946 void msub_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 947 void maddf_s(FPURegister fd, FPURegister fs, FPURegister ft); 948 void maddf_d(FPURegister fd, FPURegister fs, FPURegister ft); 949 void msubf_s(FPURegister fd, FPURegister fs, FPURegister ft); 950 void msubf_d(FPURegister fd, FPURegister fs, FPURegister ft); 951 void div_s(FPURegister fd, FPURegister fs, FPURegister ft); 952 void div_d(FPURegister fd, FPURegister fs, FPURegister ft); 953 void abs_s(FPURegister fd, FPURegister fs); 954 void abs_d(FPURegister fd, FPURegister fs); 955 void mov_d(FPURegister fd, FPURegister fs); 956 void mov_s(FPURegister fd, FPURegister fs); 957 void neg_s(FPURegister fd, FPURegister fs); 958 void neg_d(FPURegister fd, FPURegister fs); 959 void sqrt_s(FPURegister fd, FPURegister fs); 960 void sqrt_d(FPURegister fd, FPURegister fs); 961 void rsqrt_s(FPURegister fd, FPURegister fs); 962 void rsqrt_d(FPURegister fd, FPURegister fs); 963 void recip_d(FPURegister fd, FPURegister fs); 964 void recip_s(FPURegister fd, FPURegister fs); 965 966 // Conversion. 967 void cvt_w_s(FPURegister fd, FPURegister fs); 968 void cvt_w_d(FPURegister fd, FPURegister fs); 969 void trunc_w_s(FPURegister fd, FPURegister fs); 970 void trunc_w_d(FPURegister fd, FPURegister fs); 971 void round_w_s(FPURegister fd, FPURegister fs); 972 void round_w_d(FPURegister fd, FPURegister fs); 973 void floor_w_s(FPURegister fd, FPURegister fs); 974 void floor_w_d(FPURegister fd, FPURegister fs); 975 void ceil_w_s(FPURegister fd, FPURegister fs); 976 void ceil_w_d(FPURegister fd, FPURegister fs); 977 void rint_s(FPURegister fd, FPURegister fs); 978 void rint_d(FPURegister fd, FPURegister fs); 979 void rint(SecondaryField fmt, FPURegister fd, FPURegister fs); 980 981 982 void cvt_l_s(FPURegister fd, FPURegister fs); 983 void cvt_l_d(FPURegister fd, FPURegister fs); 984 void trunc_l_s(FPURegister fd, FPURegister fs); 985 void trunc_l_d(FPURegister fd, FPURegister fs); 986 void round_l_s(FPURegister fd, FPURegister fs); 987 void round_l_d(FPURegister fd, FPURegister fs); 988 void floor_l_s(FPURegister fd, FPURegister fs); 989 void floor_l_d(FPURegister fd, FPURegister fs); 990 void ceil_l_s(FPURegister fd, FPURegister fs); 991 void ceil_l_d(FPURegister fd, FPURegister fs); 992 993 void class_s(FPURegister fd, FPURegister fs); 994 void class_d(FPURegister fd, FPURegister fs); 995 996 void min(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 997 void mina(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 998 void max(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 999 void maxa(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 1000 void min_s(FPURegister fd, FPURegister fs, FPURegister ft); 1001 void min_d(FPURegister fd, FPURegister fs, FPURegister ft); 1002 void max_s(FPURegister fd, FPURegister fs, FPURegister ft); 1003 void max_d(FPURegister fd, FPURegister fs, FPURegister ft); 1004 void mina_s(FPURegister fd, FPURegister fs, FPURegister ft); 1005 void mina_d(FPURegister fd, FPURegister fs, FPURegister ft); 1006 void maxa_s(FPURegister fd, FPURegister fs, FPURegister ft); 1007 void maxa_d(FPURegister fd, FPURegister fs, FPURegister ft); 1008 1009 void cvt_s_w(FPURegister fd, FPURegister fs); 1010 void cvt_s_l(FPURegister fd, FPURegister fs); 1011 void cvt_s_d(FPURegister fd, FPURegister fs); 1012 1013 void cvt_d_w(FPURegister fd, FPURegister fs); 1014 void cvt_d_l(FPURegister fd, FPURegister fs); 1015 void cvt_d_s(FPURegister fd, FPURegister fs); 1016 1017 // Conditions and branches for MIPSr6. 1018 void cmp(FPUCondition cond, SecondaryField fmt, 1019 FPURegister fd, FPURegister ft, FPURegister fs); 1020 void cmp_s(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft); 1021 void cmp_d(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft); 1022 1023 void bc1eqz(int16_t offset, FPURegister ft); 1024 inline void bc1eqz(Label* L, FPURegister ft) { 1025 bc1eqz(shifted_branch_offset(L), ft); 1026 } 1027 void bc1nez(int16_t offset, FPURegister ft); 1028 inline void bc1nez(Label* L, FPURegister ft) { 1029 bc1nez(shifted_branch_offset(L), ft); 1030 } 1031 1032 // Conditions and branches for non MIPSr6. 1033 void c(FPUCondition cond, SecondaryField fmt, 1034 FPURegister ft, FPURegister fs, uint16_t cc = 0); 1035 void c_s(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0); 1036 void c_d(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0); 1037 1038 void bc1f(int16_t offset, uint16_t cc = 0); 1039 inline void bc1f(Label* L, uint16_t cc = 0) { 1040 bc1f(shifted_branch_offset(L), cc); 1041 } 1042 void bc1t(int16_t offset, uint16_t cc = 0); 1043 inline void bc1t(Label* L, uint16_t cc = 0) { 1044 bc1t(shifted_branch_offset(L), cc); 1045 } 1046 void fcmp(FPURegister src1, const double src2, FPUCondition cond); 1047 1048 // Check the code size generated from label to here. 1049 int SizeOfCodeGeneratedSince(Label* label) { 1050 return pc_offset() - label->pos(); 1051 } 1052 1053 // Check the number of instructions generated from label to here. 1054 int InstructionsGeneratedSince(Label* label) { 1055 return SizeOfCodeGeneratedSince(label) / kInstrSize; 1056 } 1057 1058 // Class for scoping postponing the trampoline pool generation. 1059 class BlockTrampolinePoolScope { 1060 public: 1061 explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) { 1062 assem_->StartBlockTrampolinePool(); 1063 } 1064 ~BlockTrampolinePoolScope() { 1065 assem_->EndBlockTrampolinePool(); 1066 } 1067 1068 private: 1069 Assembler* assem_; 1070 1071 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope); 1072 }; 1073 1074 // Class for postponing the assembly buffer growth. Typically used for 1075 // sequences of instructions that must be emitted as a unit, before 1076 // buffer growth (and relocation) can occur. 1077 // This blocking scope is not nestable. 1078 class BlockGrowBufferScope { 1079 public: 1080 explicit BlockGrowBufferScope(Assembler* assem) : assem_(assem) { 1081 assem_->StartBlockGrowBuffer(); 1082 } 1083 ~BlockGrowBufferScope() { 1084 assem_->EndBlockGrowBuffer(); 1085 } 1086 1087 private: 1088 Assembler* assem_; 1089 1090 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope); 1091 }; 1092 1093 // Debugging. 1094 1095 // Mark address of a debug break slot. 1096 void RecordDebugBreakSlot(RelocInfo::Mode mode); 1097 1098 // Record the AST id of the CallIC being compiled, so that it can be placed 1099 // in the relocation information. 1100 void SetRecordedAstId(TypeFeedbackId ast_id) { 1101 DCHECK(recorded_ast_id_.IsNone()); 1102 recorded_ast_id_ = ast_id; 1103 } 1104 1105 TypeFeedbackId RecordedAstId() { 1106 DCHECK(!recorded_ast_id_.IsNone()); 1107 return recorded_ast_id_; 1108 } 1109 1110 void ClearRecordedAstId() { recorded_ast_id_ = TypeFeedbackId::None(); } 1111 1112 // Record a comment relocation entry that can be used by a disassembler. 1113 // Use --code-comments to enable. 1114 void RecordComment(const char* msg); 1115 1116 // Record a deoptimization reason that can be used by a log or cpu profiler. 1117 // Use --trace-deopt to enable. 1118 void RecordDeoptReason(DeoptimizeReason reason, SourcePosition position, 1119 int id); 1120 1121 static int RelocateInternalReference(RelocInfo::Mode rmode, byte* pc, 1122 intptr_t pc_delta); 1123 1124 // Writes a single byte or word of data in the code stream. Used for 1125 // inline tables, e.g., jump-tables. 1126 void db(uint8_t data); 1127 void dd(uint32_t data); 1128 void dq(uint64_t data); 1129 void dp(uintptr_t data) { dq(data); } 1130 void dd(Label* label); 1131 1132 // Postpone the generation of the trampoline pool for the specified number of 1133 // instructions. 1134 void BlockTrampolinePoolFor(int instructions); 1135 1136 // Check if there is less than kGap bytes available in the buffer. 1137 // If this is the case, we need to grow the buffer before emitting 1138 // an instruction or relocation information. 1139 inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; } 1140 1141 // Get the number of bytes available in the buffer. 1142 inline intptr_t available_space() const { 1143 return reloc_info_writer.pos() - pc_; 1144 } 1145 1146 // Read/patch instructions. 1147 static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); } 1148 static void instr_at_put(byte* pc, Instr instr) { 1149 *reinterpret_cast<Instr*>(pc) = instr; 1150 } 1151 Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); } 1152 void instr_at_put(int pos, Instr instr) { 1153 *reinterpret_cast<Instr*>(buffer_ + pos) = instr; 1154 } 1155 1156 // Check if an instruction is a branch of some kind. 1157 static bool IsBranch(Instr instr); 1158 static bool IsBc(Instr instr); 1159 static bool IsBzc(Instr instr); 1160 1161 static bool IsBeq(Instr instr); 1162 static bool IsBne(Instr instr); 1163 static bool IsBeqzc(Instr instr); 1164 static bool IsBnezc(Instr instr); 1165 static bool IsBeqc(Instr instr); 1166 static bool IsBnec(Instr instr); 1167 1168 1169 static bool IsJump(Instr instr); 1170 static bool IsJ(Instr instr); 1171 static bool IsLui(Instr instr); 1172 static bool IsOri(Instr instr); 1173 1174 static bool IsJal(Instr instr); 1175 static bool IsJr(Instr instr); 1176 static bool IsJalr(Instr instr); 1177 1178 static bool IsNop(Instr instr, unsigned int type); 1179 static bool IsPop(Instr instr); 1180 static bool IsPush(Instr instr); 1181 static bool IsLwRegFpOffset(Instr instr); 1182 static bool IsSwRegFpOffset(Instr instr); 1183 static bool IsLwRegFpNegOffset(Instr instr); 1184 static bool IsSwRegFpNegOffset(Instr instr); 1185 1186 static Register GetRtReg(Instr instr); 1187 static Register GetRsReg(Instr instr); 1188 static Register GetRdReg(Instr instr); 1189 1190 static uint32_t GetRt(Instr instr); 1191 static uint32_t GetRtField(Instr instr); 1192 static uint32_t GetRs(Instr instr); 1193 static uint32_t GetRsField(Instr instr); 1194 static uint32_t GetRd(Instr instr); 1195 static uint32_t GetRdField(Instr instr); 1196 static uint32_t GetSa(Instr instr); 1197 static uint32_t GetSaField(Instr instr); 1198 static uint32_t GetOpcodeField(Instr instr); 1199 static uint32_t GetFunction(Instr instr); 1200 static uint32_t GetFunctionField(Instr instr); 1201 static uint32_t GetImmediate16(Instr instr); 1202 static uint32_t GetLabelConst(Instr instr); 1203 1204 static int32_t GetBranchOffset(Instr instr); 1205 static bool IsLw(Instr instr); 1206 static int16_t GetLwOffset(Instr instr); 1207 static Instr SetLwOffset(Instr instr, int16_t offset); 1208 1209 static bool IsSw(Instr instr); 1210 static Instr SetSwOffset(Instr instr, int16_t offset); 1211 static bool IsAddImmediate(Instr instr); 1212 static Instr SetAddImmediateOffset(Instr instr, int16_t offset); 1213 1214 static bool IsAndImmediate(Instr instr); 1215 static bool IsEmittedConstant(Instr instr); 1216 1217 void CheckTrampolinePool(); 1218 1219 void PatchConstantPoolAccessInstruction(int pc_offset, int offset, 1220 ConstantPoolEntry::Access access, 1221 ConstantPoolEntry::Type type) { 1222 // No embedded constant pool support. 1223 UNREACHABLE(); 1224 } 1225 1226 bool IsPrevInstrCompactBranch() { return prev_instr_compact_branch_; } 1227 static bool IsCompactBranchSupported() { return kArchVariant == kMips64r6; } 1228 1229 inline int UnboundLabelsCount() { return unbound_labels_count_; } 1230 1231 protected: 1232 // Load Scaled Address instructions. 1233 void lsa(Register rd, Register rt, Register rs, uint8_t sa); 1234 void dlsa(Register rd, Register rt, Register rs, uint8_t sa); 1235 1236 // Helpers. 1237 void LoadRegPlusOffsetToAt(const MemOperand& src); 1238 int32_t LoadRegPlusUpperOffsetPartToAt(const MemOperand& src); 1239 1240 // Relocation for a type-recording IC has the AST id added to it. This 1241 // member variable is a way to pass the information from the call site to 1242 // the relocation info. 1243 TypeFeedbackId recorded_ast_id_; 1244 1245 inline static void set_target_internal_reference_encoded_at(Address pc, 1246 Address target); 1247 1248 int64_t buffer_space() const { return reloc_info_writer.pos() - pc_; } 1249 1250 // Decode branch instruction at pos and return branch target pos. 1251 int target_at(int pos, bool is_internal); 1252 1253 // Patch branch instruction at pos to branch to given branch target pos. 1254 void target_at_put(int pos, int target_pos, bool is_internal); 1255 1256 // Say if we need to relocate with this mode. 1257 bool MustUseReg(RelocInfo::Mode rmode); 1258 1259 // Record reloc info for current pc_. 1260 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 1261 1262 // Block the emission of the trampoline pool before pc_offset. 1263 void BlockTrampolinePoolBefore(int pc_offset) { 1264 if (no_trampoline_pool_before_ < pc_offset) 1265 no_trampoline_pool_before_ = pc_offset; 1266 } 1267 1268 void StartBlockTrampolinePool() { 1269 trampoline_pool_blocked_nesting_++; 1270 } 1271 1272 void EndBlockTrampolinePool() { 1273 trampoline_pool_blocked_nesting_--; 1274 } 1275 1276 bool is_trampoline_pool_blocked() const { 1277 return trampoline_pool_blocked_nesting_ > 0; 1278 } 1279 1280 bool has_exception() const { 1281 return internal_trampoline_exception_; 1282 } 1283 1284 void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi); 1285 1286 bool is_trampoline_emitted() const { 1287 return trampoline_emitted_; 1288 } 1289 1290 // Temporarily block automatic assembly buffer growth. 1291 void StartBlockGrowBuffer() { 1292 DCHECK(!block_buffer_growth_); 1293 block_buffer_growth_ = true; 1294 } 1295 1296 void EndBlockGrowBuffer() { 1297 DCHECK(block_buffer_growth_); 1298 block_buffer_growth_ = false; 1299 } 1300 1301 bool is_buffer_growth_blocked() const { 1302 return block_buffer_growth_; 1303 } 1304 1305 void EmitForbiddenSlotInstruction() { 1306 if (IsPrevInstrCompactBranch()) { 1307 nop(); 1308 } 1309 } 1310 1311 inline void CheckTrampolinePoolQuick(int extra_instructions = 0); 1312 1313 private: 1314 // Buffer size and constant pool distance are checked together at regular 1315 // intervals of kBufferCheckInterval emitted bytes. 1316 static const int kBufferCheckInterval = 1*KB/2; 1317 1318 // Code generation. 1319 // The relocation writer's position is at least kGap bytes below the end of 1320 // the generated instructions. This is so that multi-instruction sequences do 1321 // not have to check for overflow. The same is true for writes of large 1322 // relocation info entries. 1323 static const int kGap = 32; 1324 1325 1326 // Repeated checking whether the trampoline pool should be emitted is rather 1327 // expensive. By default we only check again once a number of instructions 1328 // has been generated. 1329 static const int kCheckConstIntervalInst = 32; 1330 static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize; 1331 1332 int next_buffer_check_; // pc offset of next buffer check. 1333 1334 // Emission of the trampoline pool may be blocked in some code sequences. 1335 int trampoline_pool_blocked_nesting_; // Block emission if this is not zero. 1336 int no_trampoline_pool_before_; // Block emission before this pc offset. 1337 1338 // Keep track of the last emitted pool to guarantee a maximal distance. 1339 int last_trampoline_pool_end_; // pc offset of the end of the last pool. 1340 1341 // Automatic growth of the assembly buffer may be blocked for some sequences. 1342 bool block_buffer_growth_; // Block growth when true. 1343 1344 // Relocation information generation. 1345 // Each relocation is encoded as a variable size value. 1346 static const int kMaxRelocSize = RelocInfoWriter::kMaxSize; 1347 RelocInfoWriter reloc_info_writer; 1348 1349 // The bound position, before this we cannot do instruction elimination. 1350 int last_bound_pos_; 1351 1352 // Readable constants for compact branch handling in emit() 1353 enum class CompactBranchType : bool { NO = false, COMPACT_BRANCH = true }; 1354 1355 // Code emission. 1356 inline void CheckBuffer(); 1357 void GrowBuffer(); 1358 inline void emit(Instr x, 1359 CompactBranchType is_compact_branch = CompactBranchType::NO); 1360 inline void emit(uint64_t x); 1361 inline void CheckForEmitInForbiddenSlot(); 1362 template <typename T> 1363 inline void EmitHelper(T x); 1364 inline void EmitHelper(Instr x, CompactBranchType is_compact_branch); 1365 1366 // Instruction generation. 1367 // We have 3 different kind of encoding layout on MIPS. 1368 // However due to many different types of objects encoded in the same fields 1369 // we have quite a few aliases for each mode. 1370 // Using the same structure to refer to Register and FPURegister would spare a 1371 // few aliases, but mixing both does not look clean to me. 1372 // Anyway we could surely implement this differently. 1373 1374 void GenInstrRegister(Opcode opcode, 1375 Register rs, 1376 Register rt, 1377 Register rd, 1378 uint16_t sa = 0, 1379 SecondaryField func = NULLSF); 1380 1381 void GenInstrRegister(Opcode opcode, 1382 Register rs, 1383 Register rt, 1384 uint16_t msb, 1385 uint16_t lsb, 1386 SecondaryField func); 1387 1388 void GenInstrRegister(Opcode opcode, 1389 SecondaryField fmt, 1390 FPURegister ft, 1391 FPURegister fs, 1392 FPURegister fd, 1393 SecondaryField func = NULLSF); 1394 1395 void GenInstrRegister(Opcode opcode, 1396 FPURegister fr, 1397 FPURegister ft, 1398 FPURegister fs, 1399 FPURegister fd, 1400 SecondaryField func = NULLSF); 1401 1402 void GenInstrRegister(Opcode opcode, 1403 SecondaryField fmt, 1404 Register rt, 1405 FPURegister fs, 1406 FPURegister fd, 1407 SecondaryField func = NULLSF); 1408 1409 void GenInstrRegister(Opcode opcode, 1410 SecondaryField fmt, 1411 Register rt, 1412 FPUControlRegister fs, 1413 SecondaryField func = NULLSF); 1414 1415 1416 void GenInstrImmediate( 1417 Opcode opcode, Register rs, Register rt, int32_t j, 1418 CompactBranchType is_compact_branch = CompactBranchType::NO); 1419 void GenInstrImmediate( 1420 Opcode opcode, Register rs, SecondaryField SF, int32_t j, 1421 CompactBranchType is_compact_branch = CompactBranchType::NO); 1422 void GenInstrImmediate( 1423 Opcode opcode, Register r1, FPURegister r2, int32_t j, 1424 CompactBranchType is_compact_branch = CompactBranchType::NO); 1425 void GenInstrImmediate( 1426 Opcode opcode, Register rs, int32_t offset21, 1427 CompactBranchType is_compact_branch = CompactBranchType::NO); 1428 void GenInstrImmediate(Opcode opcode, Register rs, uint32_t offset21); 1429 void GenInstrImmediate( 1430 Opcode opcode, int32_t offset26, 1431 CompactBranchType is_compact_branch = CompactBranchType::NO); 1432 1433 void GenInstrJump(Opcode opcode, 1434 uint32_t address); 1435 1436 // Labels. 1437 void print(Label* L); 1438 void bind_to(Label* L, int pos); 1439 void next(Label* L, bool is_internal); 1440 1441 // One trampoline consists of: 1442 // - space for trampoline slots, 1443 // - space for labels. 1444 // 1445 // Space for trampoline slots is equal to slot_count * 2 * kInstrSize. 1446 // Space for trampoline slots preceeds space for labels. Each label is of one 1447 // instruction size, so total amount for labels is equal to 1448 // label_count * kInstrSize. 1449 class Trampoline { 1450 public: 1451 Trampoline() { 1452 start_ = 0; 1453 next_slot_ = 0; 1454 free_slot_count_ = 0; 1455 end_ = 0; 1456 } 1457 Trampoline(int start, int slot_count) { 1458 start_ = start; 1459 next_slot_ = start; 1460 free_slot_count_ = slot_count; 1461 end_ = start + slot_count * kTrampolineSlotsSize; 1462 } 1463 int start() { 1464 return start_; 1465 } 1466 int end() { 1467 return end_; 1468 } 1469 int take_slot() { 1470 int trampoline_slot = kInvalidSlotPos; 1471 if (free_slot_count_ <= 0) { 1472 // We have run out of space on trampolines. 1473 // Make sure we fail in debug mode, so we become aware of each case 1474 // when this happens. 1475 DCHECK(0); 1476 // Internal exception will be caught. 1477 } else { 1478 trampoline_slot = next_slot_; 1479 free_slot_count_--; 1480 next_slot_ += kTrampolineSlotsSize; 1481 } 1482 return trampoline_slot; 1483 } 1484 1485 private: 1486 int start_; 1487 int end_; 1488 int next_slot_; 1489 int free_slot_count_; 1490 }; 1491 1492 int32_t get_trampoline_entry(int32_t pos); 1493 int unbound_labels_count_; 1494 // After trampoline is emitted, long branches are used in generated code for 1495 // the forward branches whose target offsets could be beyond reach of branch 1496 // instruction. We use this information to trigger different mode of 1497 // branch instruction generation, where we use jump instructions rather 1498 // than regular branch instructions. 1499 bool trampoline_emitted_; 1500 static const int kInvalidSlotPos = -1; 1501 1502 // Internal reference positions, required for unbounded internal reference 1503 // labels. 1504 std::set<int64_t> internal_reference_positions_; 1505 bool is_internal_reference(Label* L) { 1506 return internal_reference_positions_.find(L->pos()) != 1507 internal_reference_positions_.end(); 1508 } 1509 1510 void EmittedCompactBranchInstruction() { prev_instr_compact_branch_ = true; } 1511 void ClearCompactBranchState() { prev_instr_compact_branch_ = false; } 1512 bool prev_instr_compact_branch_ = false; 1513 1514 Trampoline trampoline_; 1515 bool internal_trampoline_exception_; 1516 1517 friend class RegExpMacroAssemblerMIPS; 1518 friend class RelocInfo; 1519 friend class CodePatcher; 1520 friend class BlockTrampolinePoolScope; 1521 friend class EnsureSpace; 1522 }; 1523 1524 1525 class EnsureSpace BASE_EMBEDDED { 1526 public: 1527 explicit EnsureSpace(Assembler* assembler) { 1528 assembler->CheckBuffer(); 1529 } 1530 }; 1531 1532 } // namespace internal 1533 } // namespace v8 1534 1535 #endif // V8_ARM_ASSEMBLER_MIPS_H_ 1536