| /prebuilts/clang/host/linux-x86/clang-4393122/include/llvm/CodeGen/ |
| AsmPrinter.h | 561 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
569 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
|
| /prebuilts/clang/host/linux-x86/clang-4479392/include/llvm/CodeGen/ |
| AsmPrinter.h | 561 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
569 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
|
| /prebuilts/clang/host/linux-x86/clang-4579689/include/llvm/CodeGen/ |
| AsmPrinter.h | 560 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
568 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
|
| /prebuilts/clang/host/linux-x86/clang-4630689/include/llvm/CodeGen/ |
| AsmPrinter.h | 560 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
568 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
|
| /prebuilts/clang/host/linux-x86/clang-4639204/include/llvm/CodeGen/ |
| AsmPrinter.h | 560 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
568 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
|
| /prebuilts/clang/host/linux-x86/clang-4691093/include/llvm/CodeGen/ |
| AsmPrinter.h | 560 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
568 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 738 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
742 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
748 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
758 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
759 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
767 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
772 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
773 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
774 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break
[all...] |
| LegalizeFloatTypes.cpp | 571 bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
572 DEBUG(dbgs() << "Soften float operand " << OpNo << ": "; N->dump(&DAG);
579 dbgs() << "SoftenFloatOperand Op #" << OpNo << ": ";
592 case ISD::STORE: Res = SoftenFloatOp_STORE(N, OpNo); break;
[all...] |
| LegalizeVectorTypes.cpp | 298 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
299 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
308 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
323 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
374 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
376 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineVerifier.cpp | 820 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
822 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
823 const MachineOperand &MO = MI->getOperand(OpNo);
830 if (OpNo > MI->getNumOperands())
834 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
835 ++OpNo;
838 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
[all...] |
| MachineRegisterInfo.cpp | 81 unsigned OpNo = &MO - &MI->getOperand(0);
82 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUAsmPrinter.cpp | 723 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
733 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
739 AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
|
| AMDGPUISelDAGToDAG.cpp | 81 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
184 /// \brief Determine the register class for \p OpNo
186 /// the given operand number \OpNo or NULL if the register class cannot be
189 unsigned OpNo) const {
197 unsigned OpIdx = Desc.getNumDefs() + OpNo;
211 SDValue SubRegOp = N->getOperand(OpNo + 1);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXAsmPrinter.cpp | 171 unsigned OpNo, MCOperand &MCOp) {
172 const MachineOperand &MO = MI->getOperand(OpNo);
178 if (OpNo == 4 && MO.isImm()) {
182 if (OpNo == 5 && MO.isImm() && !(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) {
193 if (OpNo == VecSize && MO.isImm()) {
201 if (OpNo == 0 && MO.isImm()) {
209 if (OpNo == 1 && MO.isImm()) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/Utils/ |
| AddrModeMatcher.cpp | 428 unsigned opNo = UI.getOperandNo();
429 if (opNo == 0) return true; // Storing addr, not into addr.
430 MemoryUses.push_back(std::make_pair(SI, opNo));
553 unsigned OpNo = MemoryUses[i].second;
557 Value *Address = User->getOperand(OpNo);
|
| /external/llvm/utils/TableGen/ |
| DAGISelMatcherGen.cpp | 354 unsigned OpNo = 0;
365 OpNo = 1;
432 for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
435 AddMatcher(new MoveChildMatcher(OpNo));
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.h | 39 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
| /external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 27 static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
30 assert(OpNo < I->getNumOperands() && "Operand index too large");
33 ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo));
43 I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded));
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| DAGISelMatcherGen.cpp | 319 unsigned OpNo = 0;
330 OpNo = 1;
399 for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
402 AddMatcher(new MoveChildMatcher(OpNo));
[all...] |
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| Instructions.cpp | 245 unsigned OpNo = getNumOperands();
247 assert(OpNo < ReservedSpace && "Growing didn't work!");
249 OperandList[OpNo] = Val;
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 28 static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
31 assert(OpNo < I->getNumOperands() && "Operand index too large");
34 ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo));
44 I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded));
[all...] |
| /external/llvm/lib/IR/ |
| Instructions.cpp | 234 unsigned OpNo = getNumOperands();
236 assert(OpNo < ReservedSpace && "Growing didn't work!");
238 getOperandList()[OpNo] = Val;
[all...] |
| /external/llvm/lib/Transforms/IPO/ |
| GlobalOpt.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/IPO/ |
| GlobalOpt.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
