| /external/dtc/tests/ |
| base01.dts | 19 b101 = < 0x5>; // hex: 0x5
|
| base01.asm | 162 .string "b101"
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64SystemOperands.td | 44 def : AT<"S12E1W", 0b01, 0b100, 0b0111, 0b1000, 0b101>;
232 def : TLBI<"IPAS2LE1IS", 0b01, 0b100, 0b1000, 0b0000, 0b101>;
242 def : TLBI<"VALE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b101>;
243 def : TLBI<"VALE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b101>;
244 def : TLBI<"VALE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b101>;
248 def : TLBI<"IPAS2LE1", 0b01, 0b100, 0b1000, 0b0100, 0b101>;
258 def : TLBI<"VALE1", 0b01, 0b000, 0b1000, 0b0111, 0b101>;
259 def : TLBI<"VALE2", 0b01, 0b100, 0b1000, 0b0111, 0b101>;
260 def : TLBI<"VALE3", 0b01, 0b110, 0b1000, 0b0111, 0b101>;
323 def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>;
[all...] |
| AArch64InstrInfo.td | 391 def : InstAlias<"sevl", (HINT 0b101)>;
404 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
[all...] |
| AArch64InstrFormats.td | [all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| unwind.d | 37 0010 (8402b101 b0b0b005 2a000000 00c60281|01b10284 05b0b0b0 0000002a 8102c600) .*
|
| unwind_vxworks.d | 36 0010 (8402b101 b0b0b005 2a000000 00c60281|01b10284 05b0b0b0 0000002a 8102c600) .*
|
| /external/v8/tools/sanitizers/ |
| sancov_formatter_test.py | 122 # has a coverage mask of 0b101, e.g. line 2 in src/baz.cc.
128 'src/baz.cc': [[1, 0b0], [2, 0b101]],
155 'src/baz.cc': [[1, 0b0], [2, 0b101]],
|
| sancov_formatter.py | 26 executable1 and executable3 will have bit_mask == 5 == 0b101. The number of
|
| /external/llvm/lib/Target/Mips/ |
| MipsMSAInstrInfo.td | 436 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
437 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
438 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
439 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
446 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
447 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
448 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
449 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
499 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
500 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>
[all...] |
| /frameworks/native/include/private/ui/ |
| RegionHelper.h | 38 * value is computed as 0b101 op 0b110
43 static const uint32_t LHS = 0x5; // 0b101
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfoV3.td | 35 let Inst{27-25} = 0b101;
98 def A2_addpsat : T_ALU64_arith<"add", 0b011, 0b101, 1, 0, 1>;
217 def M2_vrcmpys_s1_h: T_vrcmpRaw<"hi", 0b101>;
247 def M2_vrcmpys_acc_s1_h: T_vrcmpys_acc<"hi", 0b101>;
259 def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>;
260 def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>;
|
| HexagonInstrInfo.td | 178 def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
195 def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>;
240 def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
243 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
246 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
247 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
248 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
249 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
720 let Inst{27-25} = 0b101;
804 defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel
[all...] |
| HexagonIsetDx.td | 38 let Inst{2-0} = 0b101;
59 let Inst{2-0} = 0b101;
617 let Inst{6-4} = 0b101;
|
| HexagonInstrInfoV5.td | 27 def M5_vdmpybsu: T_M2_vmpy<"vdmpybsu", 0b101, 0b001, 0, 0, 1>;
632 def F2_conv_df2uw_chop : F2_RD_RSS_CONVERT <"convert_df2uw", 0b101,
646 def F2_conv_sf2ud_chop : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b101,
[all...] |
| HexagonInstrInfoV4.td | 137 def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
191 def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
407 let Inst{27-25} = 0b101;
[all...] |
| /external/llvm/docs/TableGen/ |
| LangIntro.rst | 398 defm SUB : ri_inst<0b101, "sub">;
426 def SUB_rr : rrinst<0b101, "sub">;
427 def SUB_ri : riinst<0b101, "sub">;
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrFormats.td | [all...] |
| ARMInstrThumb2.td | [all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.td | 322 defm OR_ : ALUlogic<0b101, "or", or, i32lo16z, i32hi16>;
388 defm OR_F_ : ALUlogic<0b101, "or.f", or, i32lo16z, i32hi16>;
693 def JR : InstRR<0b101, (outs), (ins GPR:$Rs2), "bt\t$Rs2",
794 def BRIND_CC : InstRR<0b101, (outs), (ins GPR:$Rs1, CCOp:$DDDI),
802 def BRIND_CCA : InstRR<0b101, (outs), (ins GPR:$Rs1, GPR:$Rs2, CCOp:$DDDI),
|
| /external/tensorflow/tensorflow/compiler/tests/ |
| binary_ops_test.py | 216 np.array([0b1, 0b101, 0b1000], dtype=dtype),
217 np.array([0b0, 0b101, 0b1001], dtype=dtype),
218 expected=np.array([0b0, 0b101, 0b1000], dtype=dtype))
221 np.array([0b1, 0b101, 0b1000], dtype=dtype),
222 np.array([0b0, 0b101, 0b1001], dtype=dtype),
223 expected=np.array([0b1, 0b101, 0b1001], dtype=dtype))
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstr64Bit.td | 371 defm BPNZ : BranchOnReg<0b101, "brnz">;
396 defm MOVRNZ : MOVR<0b101, "movrnz">;
421 defm FMOVRNZ : FMOVR<0b101, "nz">;
|
| /frameworks/minikin/include/minikin/ |
| Hyphenator.h | 82 INSERT_UCAS_HYPHEN = 0b101,
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMInstrFormats.td | [all...] |
| ARMInstrThumb2.td | [all...] |
