| /external/llvm/test/MC/ARM/ |
| coproc-diag.s | 7 ldc2 p11, cr0, [r0], {0x21}
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| octeon-ill.s | 30 ldc2 $10,0($25)
40 ldc2 $8,foo
|
| r6.s | 89 ldc2 $2,0($4)
90 ldc2 $2,-1024($4)
91 ldc2 $2,1023($4)
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips5-wrong-error.s | 12 ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
13 ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
14 ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
|
| invalid.s | 70 ldc2 $20, -1025($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
71 ldc2 $20, 1024($s2) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled
112 ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
113 ldc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
114 ldc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips2-wrong-error.s | 9 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
10 ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
|
| invalid-mips3-wrong-error.s | 9 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
10 ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
|
| invalid-mips4-wrong-error.s | 11 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
12 ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
|
| /bionic/tests/headers/posix/ |
| tgmath_h.c | 37 #define TGMATH2C(f_) f_(f1, f2); f_(d1, d2); f_(ld1, ld2); f_(fc1, fc2); f_(dc1, dc2); f_(ldc1, ldc2);
51 long double complex ldc1, ldc2, ldc3; local
52 ldc1 = ldc2 = ldc3 = 0;
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| copro.s | 30 ldc2 5, c5, [r2], {2}
|
| group-reloc-ldc-parsing-bad.s | 27 ldctest ldc2 c0
|
| group-reloc-ldc-encoding-bad.s | 5 @ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
45 ldctest ldc2 stc2 0x1
50 ldctest ldc2 stc2 0x808
|
| copro.d | 28 0+048 <[^>]*> fc925502 ldc2 5, cr5, \[r2\], \{2\}
|
| group-reloc-ldc.s | 5 @ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
45 ldctest ldc2 stc2
|
| group-reloc-ldc-parsing-bad.l | 12 [^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
13 [^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
14 [^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
15 [^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
16 [^:]*:27: Error: unknown group relocation -- `ldc2 0,c0,\[r0,#:foo:\(sym\)\]'
|
| group-reloc-ldc.d | 104 0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\].*
106 0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\].*
108 0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\].*
110 0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\].*
112 0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\].*
114 0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\].*
128 0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\].*
130 0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\].*
132 0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\].*
134 0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\].
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| intrinsics-coprocessor.ll | 26 ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
27 tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
49 declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| invalid-wrong-error.s | 31 ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
32 ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
33 ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| invalid-armv8.txt | 154 # CHECK-V7: ldc2
159 # CHECK-V7: ldc2
164 # CHECK-V7: ldc2
|
| invalid-thumbv8.txt | 154 # CHECK-V7: ldc2
159 # CHECK-V7: ldc2
164 # CHECK-V7: ldc2
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| invalid-wrong-error.s | 41 ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
42 ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
43 ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| invalid.s | 47 ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
48 ldc2 $1, -32769($12) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
49 ldc2 $1, 32768($12) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
50 ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| invalid.s | 46 ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
47 ldc2 $1, -32769($12) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
48 ldc2 $1, 32768($12) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
49 ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset
|
| /external/clang/test/CodeGen/ |
| builtins-arm.c | 103 void ldc2(const void *i) { function
104 // CHECK: define void @ldc2(i8* %i)
105 // CHECK: call void @llvm.arm.ldc2(i32 1, i32 2, i8* %i)
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| diagnostics.s | 309 ldc2 p2, c8, [r1], { 256 }
310 ldc2 p2, c8, [r1], { -1 }
313 @ CHECK-ERRORS: ldc2 p2, c8, [r1], { 256 }
316 @ CHECK-ERRORS: ldc2 p2, c8, [r1], { -1 }
|
