1 @ Tests for LDC group relocations that are meant to fail during parsing. 2 3 .macro ldctest insn reg 4 5 \insn 0, \reg, [r0, #:pc_g0_nc:(sym)] 6 \insn 0, \reg, [r0, #:pc_g1_nc:(sym)] 7 \insn 0, \reg, [r0, #:sb_g0_nc:(sym)] 8 \insn 0, \reg, [r0, #:sb_g1_nc:(sym)] 9 10 \insn 0, \reg, [r0, #:foo:(sym)] 11 12 .endm 13 14 .macro ldctest2 insn reg 15 16 \insn \reg, [r0, #:pc_g0_nc:(sym)] 17 \insn \reg, [r0, #:pc_g1_nc:(sym)] 18 \insn \reg, [r0, #:sb_g0_nc:(sym)] 19 \insn \reg, [r0, #:sb_g1_nc:(sym)] 20 21 \insn \reg, [r0, #:foo:(sym)] 22 23 .endm 24 25 ldctest ldc c0 26 ldctest ldcl c0 27 ldctest ldc2 c0 28 ldctest ldc2l c0 29 30 ldctest stc c0 31 ldctest stcl c0 32 ldctest stc2 c0 33 ldctest stc2l c0 34 35 .fpu fpa 36 37 ldctest2 ldfs f0 38 ldctest2 stfs f0 39 ldctest2 ldfd f0 40 ldctest2 stfd f0 41 ldctest2 ldfe f0 42 ldctest2 stfe f0 43 ldctest2 ldfp f0 44 ldctest2 stfp f0 45 46 .fpu vfp 47 48 ldctest2 flds s0 49 ldctest2 fsts s0 50 51 ldctest2 fldd d0 52 ldctest2 fstd d0 53 54 ldctest2 vldr d0 FIXME 55 ldctest2 vstr d0 56 57 .cpu ep9312 58 59 ldctest2 cfldrs mvf0 60 ldctest2 cfstrs mvf0 61 ldctest2 cfldrd mvd0 62 ldctest2 cfstrd mvd0 63 ldctest2 cfldr32 mvfx0 64 ldctest2 cfstr32 mvfx0 65 ldctest2 cfldr64 mvdx0 66 ldctest2 cfstr64 mvdx0 67 68
