1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #define PLAT_PRIMARY_CPU 0x0 11 12 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 13 #define MT_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 14 15 #define IO_PHYS (0x10000000) 16 #define INFRACFG_AO_BASE (IO_PHYS + 0x1000) 17 #define MCUCFG_BASE (IO_PHYS + 0x200000) 18 #define PERI_BASE (IO_PHYS + 0x1000000) 19 20 21 #define GPIO_BASE (IO_PHYS + 0x370000) 22 #define SPM_BASE (IO_PHYS + 0x6000) 23 #define RGU_BASE (MCUCFG_BASE + 0x11000) 24 #define PMIC_WRAP_BASE (IO_PHYS + 0x10000) 25 26 #define TRNG_base (MCUCFG_BASE + 0x230000) 27 #define MT_GIC_BASE (0x10220000) 28 #define MCU_SYS_SIZE (0x700000) 29 #define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000) 30 31 /* Aggregate of all devices in the first GB */ 32 #define MTK_DEV_RNG0_BASE IO_PHYS 33 #define MTK_DEV_RNG0_SIZE 0x400000 34 #define MTK_DEV_RNG1_BASE (PERI_BASE) 35 #define MTK_DEV_RNG1_SIZE 0x4000000 36 37 /******************************************************************************* 38 * UART related constants 39 ******************************************************************************/ 40 #define UART0_BASE (PERI_BASE + 0x2000) 41 42 #define UART_BAUDRATE (921600) 43 #define UART_CLOCK (26000000) 44 45 /******************************************************************************* 46 * System counter frequency related constants 47 ******************************************************************************/ 48 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 49 #define SYS_COUNTER_FREQ_IN_MHZ (SYS_COUNTER_FREQ_IN_TICKS/1000000) 50 51 /******************************************************************************* 52 * GIC-400 & interrupt handling related constants 53 ******************************************************************************/ 54 55 /* Base MTK_platform compatible GIC memory map */ 56 #define BASE_GICD_BASE (MT_GIC_BASE+0x1000) 57 #define BASE_GICC_BASE (MT_GIC_BASE + 0x2000) 58 #define BASE_GICR_BASE (MT_GIC_BASE + 0x200000) 59 #define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) 60 #define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) 61 62 #define INT_POL_CTL0 0x10200620 63 #define GIC_PRIVATE_SIGNALS (32) 64 65 /******************************************************************************* 66 * CCI-400 related constants 67 ******************************************************************************/ 68 #define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 69 #define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 70 71 /******************************************************************************* 72 * WDT Registers 73 ******************************************************************************/ 74 #define MTK_WDT_BASE (RGU_BASE) 75 #define MTK_WDT_SIZE (0x1000) 76 #define MTK_WDT_MODE (MTK_WDT_BASE+0x0000) 77 #define MTK_WDT_LENGTH (MTK_WDT_BASE+0x0004) 78 #define MTK_WDT_RESTART (MTK_WDT_BASE+0x0008) 79 #define MTK_WDT_STATUS (MTK_WDT_BASE+0x000C) 80 #define MTK_WDT_INTERVAL (MTK_WDT_BASE+0x0010) 81 #define MTK_WDT_SWRST (MTK_WDT_BASE+0x0014) 82 #define MTK_WDT_SWSYSRST (MTK_WDT_BASE+0x0018) 83 #define MTK_WDT_NONRST_REG (MTK_WDT_BASE+0x0020) 84 #define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE+0x0024) 85 #define MTK_WDT_REQ_MODE (MTK_WDT_BASE+0x0030) 86 #define MTK_WDT_REQ_IRQ_EN (MTK_WDT_BASE+0x0034) 87 #define MTK_WDT_DEBUG_CTL (MTK_WDT_BASE+0x0040) 88 89 /*WDT_STATUS*/ 90 #define MTK_WDT_STATUS_HWWDT_RST (0x80000000) 91 #define MTK_WDT_STATUS_SWWDT_RST (0x40000000) 92 #define MTK_WDT_STATUS_IRQWDT_RST (0x20000000) 93 #define MTK_WDT_STATUS_DEBUGWDT_RST (0x00080000) 94 #define MTK_WDT_STATUS_SPMWDT_RST (0x0002) 95 #define MTK_WDT_STATUS_SPM_THERMAL_RST (0x0001) 96 #define MTK_WDT_STATUS_THERMAL_DIRECT_RST (1<<18) 97 #define MTK_WDT_STATUS_SECURITY_RST (1<<28) 98 99 #define MTK_WDT_MODE_DUAL_MODE 0x0040 100 #define MTK_WDT_MODE_IRQ 0x0008 101 #define MTK_WDT_MODE_KEY 0x22000000 102 #define MTK_WDT_MODE_EXTEN 0x0004 103 #define MTK_WDT_SWRST_KEY 0x1209 104 #define MTK_WDT_RESTART_KEY (0x1971) 105 106 /* FIQ platform related define */ 107 #define MT_IRQ_SEC_SGI_0 8 108 #define MT_IRQ_SEC_SGI_1 9 109 #define MT_IRQ_SEC_SGI_2 10 110 #define MT_IRQ_SEC_SGI_3 11 111 #define MT_IRQ_SEC_SGI_4 12 112 #define MT_IRQ_SEC_SGI_5 13 113 #define MT_IRQ_SEC_SGI_6 14 114 #define MT_IRQ_SEC_SGI_7 15 115 116 #define FIQ_SMP_CALL_SGI MT_IRQ_SEC_SGI_5 117 118 #define PLAT_ARM_G0_IRQS FIQ_SMP_CALL_SGI 119 120 #define DEBUG_XLAT_TABLE 0 121 122 /******************************************************************************* 123 * Platform binary types for linking 124 ******************************************************************************/ 125 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 126 #define PLATFORM_LINKER_ARCH aarch64 127 128 /******************************************************************************* 129 * Generic platform constants 130 ******************************************************************************/ 131 132 /* Size of cacheable stacks */ 133 #if DEBUG_XLAT_TABLE 134 #define PLATFORM_STACK_SIZE 0x800 135 #elif defined(IMAGE_BL1) 136 #define PLATFORM_STACK_SIZE 0x440 137 #elif defined(IMAGE_BL2) 138 #define PLATFORM_STACK_SIZE 0x400 139 #elif defined(IMAGE_BL31) 140 #define PLATFORM_STACK_SIZE 0x800 141 #elif defined(IMAGE_BL32) 142 #define PLATFORM_STACK_SIZE 0x440 143 #endif 144 145 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 146 #if ENABLE_PLAT_COMPAT 147 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 148 #else 149 #define PLAT_MAX_PWR_LVL 2 /* MPIDR_AFFLVL2 */ 150 #endif 151 152 #define PLATFORM_CACHE_LINE_SIZE 64 153 #define PLATFORM_SYSTEM_COUNT 1 154 #define PLATFORM_CLUSTER_COUNT 2 155 #define PLATFORM_CLUSTER0_CORE_COUNT 4 156 #define PLATFORM_CLUSTER1_CORE_COUNT 4 157 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 158 PLATFORM_CLUSTER0_CORE_COUNT) 159 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 160 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 161 PLATFORM_CLUSTER_COUNT + \ 162 PLATFORM_CORE_COUNT) 163 164 /******************************************************************************* 165 * Platform memory map related constants 166 ******************************************************************************/ 167 /* ATF Argument */ 168 #define ATF_ARG_SIZE (0x800) 169 170 /* TF txet, ro, rw, internal SRAM, Size: release: 80KB, debug: 92KB */ 171 #define TZRAM_BASE (0x110000) 172 #if DEBUG 173 #define TZRAM_SIZE (0x1C400) 174 #else 175 #define TZRAM_SIZE (0x1C400) 176 #endif 177 #define TZRAM2_BASE 0x00100000 178 #define TZRAM2_SIZE 0xDC00 179 #define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE) 180 181 #define RAM_CONSOLE_BASE 0x0012D000 182 #define RAM_CONSOLE_SIZE 0x00001000 183 /******************************************************************************* 184 * BL31 specific defines. 185 ******************************************************************************/ 186 /* 187 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 188 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 189 * little space for growth. 190 */ 191 #define BL31_BASE (TZRAM_BASE + 0x1000) 192 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 193 #define BSS1_STACK_LIMIT (TZRAM_BASE + TZRAM_SIZE) 194 #define BL31_TZRAM_SIZE (TZRAM_SIZE - ATF_ARG_SIZE) 195 196 /******************************************************************************* 197 * Platform specific page table and MMU setup constants 198 ******************************************************************************/ 199 #define ADDR_SPACE_SIZE (1ull << 32) 200 #define MAX_XLAT_TABLES 7 201 #define MAX_MMAP_REGIONS 16 202 203 204 /******************************************************************************* 205 * CCI-400 related constants 206 ******************************************************************************/ 207 #define CCI400_BASE 0x10390000 208 #define CCI400_SL_IFACE_CLUSTER0 4 209 #define CCI400_SL_IFACE_CLUSTER1 3 210 #define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \ 211 CCI400_SL_IFACE_CLUSTER1 : \ 212 CCI400_SL_IFACE_CLUSTER0) 213 #define CCI_SEC_ACCESS_OFFSET (0x8) 214 215 216 /******************************************************************************* 217 * Declarations and constants to access the mailboxes safely. Each mailbox is 218 * aligned on the biggest cache line size in the platform. This is known only 219 * to the platform as it might have a combination of integrated and external 220 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 221 * line at any cache level. They could belong to different cpus/clusters & 222 * get written while being protected by different locks causing corruption of 223 * a valid mailbox address. 224 ******************************************************************************/ 225 #define CACHE_WRITEBACK_SHIFT 6 226 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 227 228 #define BL32_BASE (0x0) 229 230 /* 231 * Load address of BL3-3 for this platform port 232 */ 233 #define LK_SIZE_LIMIT (0x100000) 234 #define PLAT_MTK_NS_IMAGE_OFFSET (0x41E00000) 235 /* 16KB */ 236 #define ATF_AEE_BUFFER_SIZE (0x4000) 237 #define PAGE_SIZE_2MB_MASK (PAGE_SIZE_2MB - 1) 238 #define IS_PAGE_2MB_ALIGNED(addr) (((addr) & PAGE_SIZE_2MB_MASK) == 0) 239 #define PAGE_SIZE_2MB (1 << PAGE_SIZE_2MB_SHIFT) 240 #define PAGE_SIZE_2MB_SHIFT TWO_MB_SHIFT 241 242 #endif /* __PLATFORM_DEF_H__ */ 243
