1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <bl_common.h> 9 #include <console.h> 10 #include <gic_common.h> 11 #include <gicv2.h> 12 #include <platform_def.h> 13 #include "qemu_private.h" 14 15 /* 16 * The next 3 constants identify the extents of the code, RO data region and the 17 * limit of the BL3-1 image. These addresses are used by the MMU setup code and 18 * therefore they must be page-aligned. It is the responsibility of the linker 19 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 20 * refer to page-aligned addresses. 21 */ 22 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 23 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 24 #define BL31_END (unsigned long)(&__BL31_END__) 25 26 /* 27 * Placeholder variables for copying the arguments that have been passed to 28 * BL3-1 from BL2. 29 */ 30 static entry_point_info_t bl32_image_ep_info; 31 static entry_point_info_t bl33_image_ep_info; 32 33 /******************************************************************************* 34 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 35 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before 36 * they are lost (potentially). This needs to be done before the MMU is 37 * initialized so that the memory layout can be used while creating page 38 * tables. BL2 has flushed this information to memory, so we are guaranteed 39 * to pick up good data. 40 ******************************************************************************/ 41 #if LOAD_IMAGE_V2 42 void bl31_early_platform_setup(void *from_bl2, 43 void *plat_params_from_bl2) 44 #else 45 void bl31_early_platform_setup(bl31_params_t *from_bl2, 46 void *plat_params_from_bl2) 47 #endif 48 { 49 /* Initialize the console to provide early debug support */ 50 console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ, 51 PLAT_QEMU_CONSOLE_BAUDRATE); 52 53 #if LOAD_IMAGE_V2 54 /* 55 * Check params passed from BL2 56 */ 57 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 58 59 assert(params_from_bl2); 60 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 61 assert(params_from_bl2->h.version >= VERSION_2); 62 63 bl_params_node_t *bl_params = params_from_bl2->head; 64 65 /* 66 * Copy BL33 and BL32 (if present), entry point information. 67 * They are stored in Secure RAM, in BL2's address space. 68 */ 69 while (bl_params) { 70 if (bl_params->image_id == BL32_IMAGE_ID) 71 bl32_image_ep_info = *bl_params->ep_info; 72 73 if (bl_params->image_id == BL33_IMAGE_ID) 74 bl33_image_ep_info = *bl_params->ep_info; 75 76 bl_params = bl_params->next_params_info; 77 } 78 79 if (!bl33_image_ep_info.pc) 80 panic(); 81 82 #else /* LOAD_IMAGE_V2 */ 83 84 /* 85 * Check params passed from BL2 should not be NULL, 86 */ 87 assert(from_bl2 != NULL); 88 assert(from_bl2->h.type == PARAM_BL31); 89 assert(from_bl2->h.version >= VERSION_1); 90 /* 91 * In debug builds, we pass a special value in 'plat_params_from_bl2' 92 * to verify platform parameters from BL2 to BL3-1. 93 * In release builds, it's not used. 94 */ 95 assert(((unsigned long long)plat_params_from_bl2) == 96 QEMU_BL31_PLAT_PARAM_VAL); 97 98 /* 99 * Copy BL3-2 (if populated by BL2) and BL3-3 entry point information. 100 * They are stored in Secure RAM, in BL2's address space. 101 */ 102 if (from_bl2->bl32_ep_info) 103 bl32_image_ep_info = *from_bl2->bl32_ep_info; 104 bl33_image_ep_info = *from_bl2->bl33_ep_info; 105 106 #endif /* !LOAD_IMAGE_V2 */ 107 } 108 109 void bl31_plat_arch_setup(void) 110 { 111 qemu_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE), 112 BL31_RO_BASE, BL31_RO_LIMIT, 113 BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); 114 } 115 116 /****************************************************************************** 117 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 118 * interrupts. 119 *****************************************************************************/ 120 #define PLATFORM_G1S_PROPS(grp) \ 121 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ 122 grp, GIC_INTR_CFG_EDGE), \ 123 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 124 grp, GIC_INTR_CFG_EDGE), \ 125 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 126 grp, GIC_INTR_CFG_EDGE), \ 127 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 128 grp, GIC_INTR_CFG_EDGE), \ 129 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 130 grp, GIC_INTR_CFG_EDGE), \ 131 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 132 grp, GIC_INTR_CFG_EDGE), \ 133 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 134 grp, GIC_INTR_CFG_EDGE), \ 135 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 136 grp, GIC_INTR_CFG_EDGE) 137 138 #define PLATFORM_G0_PROPS(grp) 139 140 static const interrupt_prop_t qemu_interrupt_props[] = { 141 PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), 142 PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) 143 }; 144 145 static const struct gicv2_driver_data plat_gicv2_driver_data = { 146 .gicd_base = GICD_BASE, 147 .gicc_base = GICC_BASE, 148 .interrupt_props = qemu_interrupt_props, 149 .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), 150 }; 151 152 void bl31_platform_setup(void) 153 { 154 /* Initialize the gic cpu and distributor interfaces */ 155 gicv2_driver_init(&plat_gicv2_driver_data); 156 gicv2_distif_init(); 157 gicv2_pcpu_distif_init(); 158 gicv2_cpuif_enable(); 159 } 160 161 unsigned int plat_get_syscnt_freq2(void) 162 { 163 return SYS_COUNTER_FREQ_IN_TICKS; 164 } 165 166 /******************************************************************************* 167 * Return a pointer to the 'entry_point_info' structure of the next image 168 * for the security state specified. BL3-3 corresponds to the non-secure 169 * image type while BL3-2 corresponds to the secure image type. A NULL 170 * pointer is returned if the image does not exist. 171 ******************************************************************************/ 172 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 173 { 174 entry_point_info_t *next_image_info; 175 176 assert(sec_state_is_valid(type)); 177 next_image_info = (type == NON_SECURE) 178 ? &bl33_image_ep_info : &bl32_image_ep_info; 179 /* 180 * None of the images on the ARM development platforms can have 0x0 181 * as the entrypoint 182 */ 183 if (next_image_info->pc) 184 return next_image_info; 185 else 186 return NULL; 187 } 188
