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      1 //===-- Mips16RegisterInfo.cpp - MIPS16 Register Information --------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the MIPS16 implementation of the TargetRegisterInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "Mips16RegisterInfo.h"
     15 #include "Mips.h"
     16 #include "Mips16InstrInfo.h"
     17 #include "MipsInstrInfo.h"
     18 #include "MipsMachineFunction.h"
     19 #include "MipsSubtarget.h"
     20 #include "llvm/ADT/STLExtras.h"
     21 #include "llvm/CodeGen/MachineFrameInfo.h"
     22 #include "llvm/CodeGen/MachineFunction.h"
     23 #include "llvm/CodeGen/MachineInstrBuilder.h"
     24 #include "llvm/CodeGen/MachineRegisterInfo.h"
     25 #include "llvm/IR/Constants.h"
     26 #include "llvm/IR/DebugInfo.h"
     27 #include "llvm/IR/Function.h"
     28 #include "llvm/IR/Type.h"
     29 #include "llvm/Support/Debug.h"
     30 #include "llvm/Support/ErrorHandling.h"
     31 #include "llvm/Support/raw_ostream.h"
     32 #include "llvm/Target/TargetFrameLowering.h"
     33 #include "llvm/Target/TargetInstrInfo.h"
     34 #include "llvm/Target/TargetMachine.h"
     35 #include "llvm/Target/TargetOptions.h"
     36 
     37 using namespace llvm;
     38 
     39 #define DEBUG_TYPE "mips16-registerinfo"
     40 
     41 Mips16RegisterInfo::Mips16RegisterInfo() : MipsRegisterInfo() {}
     42 
     43 bool Mips16RegisterInfo::requiresRegisterScavenging
     44   (const MachineFunction &MF) const {
     45   return false;
     46 }
     47 bool Mips16RegisterInfo::requiresFrameIndexScavenging
     48   (const MachineFunction &MF) const {
     49   return false;
     50 }
     51 
     52 bool Mips16RegisterInfo::useFPForScavengingIndex
     53   (const MachineFunction &MF) const {
     54   return false;
     55 }
     56 
     57 bool Mips16RegisterInfo::saveScavengerRegister
     58   (MachineBasicBlock &MBB,
     59    MachineBasicBlock::iterator I,
     60    MachineBasicBlock::iterator &UseMI,
     61    const TargetRegisterClass *RC,
     62    unsigned Reg) const {
     63   DebugLoc DL;
     64   const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
     65   TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
     66   TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
     67   return true;
     68 }
     69 
     70 const TargetRegisterClass *
     71 Mips16RegisterInfo::intRegClass(unsigned Size) const {
     72   assert(Size == 4);
     73   return &Mips::CPU16RegsRegClass;
     74 }
     75 
     76 void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
     77                                      unsigned OpNo, int FrameIndex,
     78                                      uint64_t StackSize,
     79                                      int64_t SPOffset) const {
     80   MachineInstr &MI = *II;
     81   MachineFunction &MF = *MI.getParent()->getParent();
     82   MachineFrameInfo *MFI = MF.getFrameInfo();
     83 
     84   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
     85   int MinCSFI = 0;
     86   int MaxCSFI = -1;
     87 
     88   if (CSI.size()) {
     89     MinCSFI = CSI[0].getFrameIdx();
     90     MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
     91   }
     92 
     93   // The following stack frame objects are always
     94   // referenced relative to $sp:
     95   //  1. Outgoing arguments.
     96   //  2. Pointer to dynamically allocated stack space.
     97   //  3. Locations for callee-saved registers.
     98   // Everything else is referenced relative to whatever register
     99   // getFrameRegister() returns.
    100   unsigned FrameReg;
    101 
    102   if (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)
    103     FrameReg = Mips::SP;
    104   else {
    105     const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
    106     if (TFI->hasFP(MF)) {
    107       FrameReg = Mips::S0;
    108     }
    109     else {
    110       if ((MI.getNumOperands()> OpNo+2) && MI.getOperand(OpNo+2).isReg())
    111         FrameReg = MI.getOperand(OpNo+2).getReg();
    112       else
    113         FrameReg = Mips::SP;
    114     }
    115   }
    116   // Calculate final offset.
    117   // - There is no need to change the offset if the frame object
    118   //   is one of the
    119   //   following: an outgoing argument, pointer to a dynamically allocated
    120   //   stack space or a $gp restore location,
    121   // - If the frame object is any of the following,
    122   //   its offset must be adjusted
    123   //   by adding the size of the stack:
    124   //   incoming argument, callee-saved register location or local variable.
    125   int64_t Offset;
    126   bool IsKill = false;
    127   Offset = SPOffset + (int64_t)StackSize;
    128   Offset += MI.getOperand(OpNo + 1).getImm();
    129 
    130 
    131   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
    132 
    133   if (!MI.isDebugValue() &&
    134       !Mips16InstrInfo::validImmediate(MI.getOpcode(), FrameReg, Offset)) {
    135     MachineBasicBlock &MBB = *MI.getParent();
    136     DebugLoc DL = II->getDebugLoc();
    137     unsigned NewImm;
    138     const Mips16InstrInfo &TII =
    139         *static_cast<const Mips16InstrInfo *>(MF.getSubtarget().getInstrInfo());
    140     FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
    141     Offset = SignExtend64<16>(NewImm);
    142     IsKill = true;
    143   }
    144   MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
    145   MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
    146 
    147 
    148 }
    149