1 //===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern, 11 InstrItinClass itin = NoItinerary> 12 : Instruction { 13 field bits<32> Inst; 14 15 let Namespace = "SP"; 16 let Size = 4; 17 18 bits<2> op; 19 let Inst{31-30} = op; // Top two bits are the 'op' field 20 21 dag OutOperandList = outs; 22 dag InOperandList = ins; 23 let AsmString = asmstr; 24 let Pattern = pattern; 25 26 let DecoderNamespace = "Sparc"; 27 field bits<32> SoftFail = 0; 28 29 let Itinerary = itin; 30 } 31 32 //===----------------------------------------------------------------------===// 33 // Format #2 instruction classes in the Sparc 34 //===----------------------------------------------------------------------===// 35 36 // Format 2 instructions 37 class F2<dag outs, dag ins, string asmstr, list<dag> pattern, 38 InstrItinClass itin = NoItinerary> 39 : InstSP<outs, ins, asmstr, pattern, itin> { 40 bits<3> op2; 41 bits<22> imm22; 42 let op = 0; // op = 0 43 let Inst{24-22} = op2; 44 let Inst{21-0} = imm22; 45 } 46 47 // Specific F2 classes: SparcV8 manual, page 44 48 // 49 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern, 50 InstrItinClass itin = NoItinerary> 51 : F2<outs, ins, asmstr, pattern, itin> { 52 bits<5> rd; 53 54 let op2 = op2Val; 55 56 let Inst{29-25} = rd; 57 } 58 59 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr, 60 list<dag> pattern, InstrItinClass itin = NoItinerary> 61 : F2<outs, ins, asmstr, pattern, itin> { 62 bits<4> cond; 63 let op2 = op2Val; 64 65 let Inst{29} = annul; 66 let Inst{28-25} = cond; 67 } 68 69 class F2_3<bits<3> op2Val, bit annul, bit pred, 70 dag outs, dag ins, string asmstr, list<dag> pattern, 71 InstrItinClass itin = NoItinerary> 72 : InstSP<outs, ins, asmstr, pattern, itin> { 73 bits<2> cc; 74 bits<4> cond; 75 bits<19> imm19; 76 77 let op = 0; // op = 0 78 79 let Inst{29} = annul; 80 let Inst{28-25} = cond; 81 let Inst{24-22} = op2Val; 82 let Inst{21-20} = cc; 83 let Inst{19} = pred; 84 let Inst{18-0} = imm19; 85 } 86 87 class F2_4<bits<3> cond, bit annul, bit pred, dag outs, dag ins, 88 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 89 : InstSP<outs, ins, asmstr, pattern, itin> { 90 bits<16> imm16; 91 bits<5> rs1; 92 93 let op = 0; // op = 0 94 95 let Inst{29} = annul; 96 let Inst{28} = 0; 97 let Inst{27-25} = cond; 98 let Inst{24-22} = 0b011; 99 let Inst{21-20} = imm16{15-14}; 100 let Inst{19} = pred; 101 let Inst{18-14} = rs1; 102 let Inst{13-0} = imm16{13-0}; 103 } 104 105 106 //===----------------------------------------------------------------------===// 107 // Format #3 instruction classes in the Sparc 108 //===----------------------------------------------------------------------===// 109 110 class F3<dag outs, dag ins, string asmstr, list<dag> pattern, 111 InstrItinClass itin = NoItinerary> 112 : InstSP<outs, ins, asmstr, pattern, itin> { 113 bits<5> rd; 114 bits<6> op3; 115 bits<5> rs1; 116 let op{1} = 1; // Op = 2 or 3 117 let Inst{29-25} = rd; 118 let Inst{24-19} = op3; 119 let Inst{18-14} = rs1; 120 } 121 122 // Specific F3 classes: SparcV8 manual, page 44 123 // 124 class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 125 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 126 : F3<outs, ins, asmstr, pattern, itin> { 127 bits<8> asi; 128 bits<5> rs2; 129 130 let op = opVal; 131 let op3 = op3val; 132 133 let Inst{13} = 0; // i field = 0 134 let Inst{12-5} = asi; // address space identifier 135 let Inst{4-0} = rs2; 136 } 137 138 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, 139 list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 140 : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> { 141 let asi = 0; 142 } 143 144 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 145 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 146 : F3<outs, ins, asmstr, pattern, itin> { 147 bits<13> simm13; 148 149 let op = opVal; 150 let op3 = op3val; 151 152 let Inst{13} = 1; // i field = 1 153 let Inst{12-0} = simm13; 154 } 155 156 // floating-point 157 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 158 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 159 : F3<outs, ins, asmstr, pattern, itin> { 160 bits<5> rs2; 161 162 let op = opVal; 163 let op3 = op3val; 164 165 let Inst{13-5} = opfval; // fp opcode 166 let Inst{4-0} = rs2; 167 } 168 169 // floating-point unary operations. 170 class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 171 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 172 : F3<outs, ins, asmstr, pattern, itin> { 173 bits<5> rs2; 174 175 let op = opVal; 176 let op3 = op3val; 177 let rs1 = 0; 178 179 let Inst{13-5} = opfval; // fp opcode 180 let Inst{4-0} = rs2; 181 } 182 183 // floating-point compares. 184 class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 185 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 186 : F3<outs, ins, asmstr, pattern, itin> { 187 bits<5> rs2; 188 189 let op = opVal; 190 let op3 = op3val; 191 192 let Inst{13-5} = opfval; // fp opcode 193 let Inst{4-0} = rs2; 194 } 195 196 // Shift by register rs2. 197 class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 198 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 199 : F3<outs, ins, asmstr, pattern, itin> { 200 bit x = xVal; // 1 for 64-bit shifts. 201 bits<5> rs2; 202 203 let op = opVal; 204 let op3 = op3val; 205 206 let Inst{13} = 0; // i field = 0 207 let Inst{12} = x; // extended registers. 208 let Inst{4-0} = rs2; 209 } 210 211 // Shift by immediate. 212 class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 213 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 214 : F3<outs, ins, asmstr, pattern, itin> { 215 bit x = xVal; // 1 for 64-bit shifts. 216 bits<6> shcnt; // shcnt32 / shcnt64. 217 218 let op = opVal; 219 let op3 = op3val; 220 221 let Inst{13} = 1; // i field = 1 222 let Inst{12} = x; // extended registers. 223 let Inst{5-0} = shcnt; 224 } 225 226 // Define rr and ri shift instructions with patterns. 227 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, 228 ValueType VT, RegisterClass RC, 229 InstrItinClass itin = IIC_iu_instr> { 230 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), 231 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 232 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))], 233 itin>; 234 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt), 235 !strconcat(OpcStr, " $rs1, $shcnt, $rd"), 236 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))], 237 itin>; 238 } 239 240 class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern, 241 InstrItinClass itin = NoItinerary> 242 : InstSP<outs, ins, asmstr, pattern, itin> { 243 bits<5> rd; 244 245 let op = 2; 246 let Inst{29-25} = rd; 247 let Inst{24-19} = op3; 248 } 249 250 251 class F4_1<bits<6> op3, dag outs, dag ins, 252 string asmstr, list<dag> pattern, 253 InstrItinClass itin = NoItinerary> 254 : F4<op3, outs, ins, asmstr, pattern, itin> { 255 bit intcc; 256 bits<2> cc; 257 bits<4> cond; 258 bits<5> rs2; 259 260 let Inst{4-0} = rs2; 261 let Inst{12-11} = cc; 262 let Inst{13} = 0; 263 let Inst{17-14} = cond; 264 let Inst{18} = intcc; 265 } 266 267 class F4_2<bits<6> op3, dag outs, dag ins, 268 string asmstr, list<dag> pattern, 269 InstrItinClass itin = NoItinerary> 270 : F4<op3, outs, ins, asmstr, pattern, itin> { 271 bit intcc; 272 bits<2> cc; 273 bits<4> cond; 274 bits<11> simm11; 275 276 let Inst{10-0} = simm11; 277 let Inst{12-11} = cc; 278 let Inst{13} = 1; 279 let Inst{17-14} = cond; 280 let Inst{18} = intcc; 281 } 282 283 class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins, 284 string asmstr, list<dag> pattern, 285 InstrItinClass itin = NoItinerary> 286 : F4<op3, outs, ins, asmstr, pattern, itin> { 287 bits<4> cond; 288 bit intcc; 289 bits<2> opf_cc; 290 bits<5> rs2; 291 292 let Inst{18} = 0; 293 let Inst{17-14} = cond; 294 let Inst{13} = intcc; 295 let Inst{12-11} = opf_cc; 296 let Inst{10-5} = opf_low; 297 let Inst{4-0} = rs2; 298 } 299 300 class F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins, 301 string asmstr, list<dag> pattern, 302 InstrItinClass itin = NoItinerary> 303 : F4<op3, outs, ins, asmstr, pattern, itin> { 304 bits <5> rs1; 305 bits <5> rs2; 306 let Inst{18-14} = rs1; 307 let Inst{13} = 0; // IsImm 308 let Inst{12-10} = rcond; 309 let Inst{9-5} = opf_low; 310 let Inst{4-0} = rs2; 311 } 312 313 314 class F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins, 315 string asmstr, list<dag> pattern, 316 InstrItinClass itin = NoItinerary> 317 : F4<op3, outs, ins, asmstr, pattern, itin> { 318 bits<5> rs1; 319 bits<10> simm10; 320 let Inst{18-14} = rs1; 321 let Inst{13} = 1; // IsImm 322 let Inst{12-10} = rcond; 323 let Inst{9-0} = simm10; 324 } 325 326 327 class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins, 328 string asmstr, list<dag> pattern, 329 InstrItinClass itin = NoItinerary> 330 : F3<outs, ins, asmstr, pattern, itin> { 331 bits<4> cond; 332 bits<2> cc; 333 334 let op = 0b10; 335 let rd{4} = 0; 336 let rd{3-0} = cond; 337 let op3 = op3Val; 338 let Inst{13} = isimm; 339 let Inst{12-11} = cc; 340 341 } 342 343 class TRAPSPrr<bits<6> op3Val, dag outs, dag ins, 344 string asmstr, list<dag> pattern, 345 InstrItinClass itin = NoItinerary> 346 : TRAPSP<op3Val, 0, outs, ins, asmstr, pattern, itin> { 347 bits<5> rs2; 348 349 let Inst{10-5} = 0; 350 let Inst{4-0} = rs2; 351 } 352 353 class TRAPSPri<bits<6> op3Val, dag outs, dag ins, 354 string asmstr, list<dag> pattern, 355 InstrItinClass itin = NoItinerary> 356 : TRAPSP<op3Val, 1, outs, ins, asmstr, pattern, itin> { 357 bits<8> imm; 358 359 let Inst{10-8} = 0; 360 let Inst{7-0} = imm; 361 } 362 363 // Pseudo-instructions for alternate assembly syntax (never used by codegen). 364 // These are aliases that require C++ handling to convert to the target 365 // instruction, while InstAliases can be handled directly by tblgen. 366 class AsmPseudoInst<dag outs, dag ins, string asm> 367 : InstSP<outs, ins, asm, []> { 368 let isPseudo = 1; 369 } 370
