1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides X86 specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H 15 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H 16 17 #include "llvm/MC/MCStreamer.h" 18 #include "llvm/Support/DataTypes.h" 19 #include <string> 20 21 namespace llvm { 22 class MCAsmBackend; 23 class MCCodeEmitter; 24 class MCContext; 25 class MCInstrInfo; 26 class MCObjectWriter; 27 class MCRegisterInfo; 28 class MCSubtargetInfo; 29 class MCRelocationInfo; 30 class Target; 31 class Triple; 32 class StringRef; 33 class raw_ostream; 34 class raw_pwrite_stream; 35 36 extern Target TheX86_32Target, TheX86_64Target; 37 38 /// Flavour of dwarf regnumbers 39 /// 40 namespace DWARFFlavour { 41 enum { 42 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 43 }; 44 } 45 46 /// Native X86 register numbers 47 /// 48 namespace N86 { 49 enum { 50 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 51 }; 52 } 53 54 namespace X86_MC { 55 std::string ParseX86Triple(const Triple &TT); 56 57 unsigned getDwarfRegFlavour(const Triple &TT, bool isEH); 58 59 void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI); 60 61 /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc. 62 /// do not need to go through TargetRegistry. 63 MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, 64 StringRef FS); 65 } 66 67 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, 68 const MCRegisterInfo &MRI, 69 MCContext &Ctx); 70 71 MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, 72 const Triple &TT, StringRef CPU); 73 MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, 74 const Triple &TT, StringRef CPU); 75 76 /// Construct an X86 Windows COFF machine code streamer which will generate 77 /// PE/COFF format object files. 78 /// 79 /// Takes ownership of \p AB and \p CE. 80 MCStreamer *createX86WinCOFFStreamer(MCContext &C, MCAsmBackend &AB, 81 raw_pwrite_stream &OS, MCCodeEmitter *CE, 82 bool RelaxAll, bool IncrementalLinkerCompatible); 83 84 /// Construct an X86 Mach-O object writer. 85 MCObjectWriter *createX86MachObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, 86 uint32_t CPUType, 87 uint32_t CPUSubtype); 88 89 /// Construct an X86 ELF object writer. 90 MCObjectWriter *createX86ELFObjectWriter(raw_pwrite_stream &OS, bool IsELF64, 91 uint8_t OSABI, uint16_t EMachine); 92 /// Construct an X86 Win COFF object writer. 93 MCObjectWriter *createX86WinCOFFObjectWriter(raw_pwrite_stream &OS, 94 bool Is64Bit); 95 96 /// Returns the sub or super register of a specific X86 register. 97 /// e.g. getX86SubSuperRegister(X86::EAX, 16) returns X86::AX. 98 /// Aborts on error. 99 unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false); 100 101 /// Returns the sub or super register of a specific X86 register. 102 /// Like getX86SubSuperRegister() but returns 0 on error. 103 unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned, 104 bool High = false); 105 106 } // End llvm namespace 107 108 109 // Defines symbolic names for X86 registers. This defines a mapping from 110 // register name to register number. 111 // 112 #define GET_REGINFO_ENUM 113 #include "X86GenRegisterInfo.inc" 114 115 // Defines symbolic names for the X86 instructions. 116 // 117 #define GET_INSTRINFO_ENUM 118 #include "X86GenInstrInfo.inc" 119 120 #define GET_SUBTARGETINFO_ENUM 121 #include "X86GenSubtargetInfo.inc" 122 123 #endif 124
