1 /* 2 * Copyright 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * \file brw_tcs.c 26 * 27 * Tessellation control shader state upload code. 28 */ 29 30 #include "brw_context.h" 31 #include "brw_nir.h" 32 #include "brw_program.h" 33 #include "brw_shader.h" 34 #include "brw_state.h" 35 #include "program/prog_parameter.h" 36 #include "nir_builder.h" 37 38 static nir_shader * 39 create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compiler, 40 const nir_shader_compiler_options *options, 41 const struct brw_tcs_prog_key *key) 42 { 43 nir_builder b; 44 nir_builder_init_simple_shader(&b, mem_ctx, MESA_SHADER_TESS_CTRL, 45 options); 46 nir_shader *nir = b.shader; 47 nir_variable *var; 48 nir_intrinsic_instr *load; 49 nir_intrinsic_instr *store; 50 nir_ssa_def *zero = nir_imm_int(&b, 0); 51 nir_ssa_def *invoc_id = 52 nir_load_system_value(&b, nir_intrinsic_load_invocation_id, 0); 53 54 nir->info->inputs_read = key->outputs_written & 55 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER); 56 nir->info->outputs_written = key->outputs_written; 57 nir->info->tess.tcs_vertices_out = key->input_vertices; 58 nir->info->name = ralloc_strdup(nir, "passthrough"); 59 nir->num_uniforms = 8 * sizeof(uint32_t); 60 61 var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_0"); 62 var->data.location = 0; 63 var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_1"); 64 var->data.location = 1; 65 66 /* Write the patch URB header. */ 67 for (int i = 0; i <= 1; i++) { 68 load = nir_intrinsic_instr_create(nir, nir_intrinsic_load_uniform); 69 load->num_components = 4; 70 load->src[0] = nir_src_for_ssa(zero); 71 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL); 72 nir_intrinsic_set_base(load, i * 4 * sizeof(uint32_t)); 73 nir_builder_instr_insert(&b, &load->instr); 74 75 store = nir_intrinsic_instr_create(nir, nir_intrinsic_store_output); 76 store->num_components = 4; 77 store->src[0] = nir_src_for_ssa(&load->dest.ssa); 78 store->src[1] = nir_src_for_ssa(zero); 79 nir_intrinsic_set_base(store, VARYING_SLOT_TESS_LEVEL_INNER - i); 80 nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW); 81 nir_builder_instr_insert(&b, &store->instr); 82 } 83 84 /* Copy inputs to outputs. */ 85 uint64_t varyings = nir->info->inputs_read; 86 87 while (varyings != 0) { 88 const int varying = ffsll(varyings) - 1; 89 90 load = nir_intrinsic_instr_create(nir, 91 nir_intrinsic_load_per_vertex_input); 92 load->num_components = 4; 93 load->src[0] = nir_src_for_ssa(invoc_id); 94 load->src[1] = nir_src_for_ssa(zero); 95 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL); 96 nir_intrinsic_set_base(load, varying); 97 nir_builder_instr_insert(&b, &load->instr); 98 99 store = nir_intrinsic_instr_create(nir, 100 nir_intrinsic_store_per_vertex_output); 101 store->num_components = 4; 102 store->src[0] = nir_src_for_ssa(&load->dest.ssa); 103 store->src[1] = nir_src_for_ssa(invoc_id); 104 store->src[2] = nir_src_for_ssa(zero); 105 nir_intrinsic_set_base(store, varying); 106 nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW); 107 nir_builder_instr_insert(&b, &store->instr); 108 109 varyings &= ~BITFIELD64_BIT(varying); 110 } 111 112 nir_validate_shader(nir); 113 114 nir = brw_preprocess_nir(compiler, nir); 115 116 return nir; 117 } 118 119 static void 120 brw_tcs_debug_recompile(struct brw_context *brw, struct gl_program *prog, 121 const struct brw_tcs_prog_key *key) 122 { 123 perf_debug("Recompiling tessellation control shader for program %d\n", 124 prog->Id); 125 126 bool found = false; 127 const struct brw_tcs_prog_key *old_key = 128 brw_find_previous_compile(&brw->cache, BRW_CACHE_TCS_PROG, 129 key->program_string_id); 130 131 if (!old_key) { 132 perf_debug(" Didn't find previous compile in the shader cache for " 133 "debug\n"); 134 return; 135 } 136 137 found |= key_debug(brw, "input vertices", old_key->input_vertices, 138 key->input_vertices); 139 found |= key_debug(brw, "outputs written", old_key->outputs_written, 140 key->outputs_written); 141 found |= key_debug(brw, "patch outputs written", old_key->patch_outputs_written, 142 key->patch_outputs_written); 143 found |= key_debug(brw, "TES primitive mode", old_key->tes_primitive_mode, 144 key->tes_primitive_mode); 145 found |= key_debug(brw, "quads and equal_spacing workaround", 146 old_key->quads_workaround, key->quads_workaround); 147 found |= brw_debug_recompile_sampler_key(brw, &old_key->tex, &key->tex); 148 149 if (!found) { 150 perf_debug(" Something else\n"); 151 } 152 } 153 154 static bool 155 brw_codegen_tcs_prog(struct brw_context *brw, struct brw_program *tcp, 156 struct brw_program *tep, struct brw_tcs_prog_key *key) 157 { 158 struct gl_context *ctx = &brw->ctx; 159 const struct brw_compiler *compiler = brw->screen->compiler; 160 const struct gen_device_info *devinfo = compiler->devinfo; 161 struct brw_stage_state *stage_state = &brw->tcs.base; 162 nir_shader *nir; 163 struct brw_tcs_prog_data prog_data; 164 bool start_busy = false; 165 double start_time = 0; 166 167 void *mem_ctx = ralloc_context(NULL); 168 if (tcp) { 169 nir = tcp->program.nir; 170 } else { 171 /* Create a dummy nir_shader. We won't actually use NIR code to 172 * generate assembly (it's easier to generate assembly directly), 173 * but the whole compiler assumes one of these exists. 174 */ 175 const nir_shader_compiler_options *options = 176 ctx->Const.ShaderCompilerOptions[MESA_SHADER_TESS_CTRL].NirOptions; 177 nir = create_passthrough_tcs(mem_ctx, compiler, options, key); 178 } 179 180 memset(&prog_data, 0, sizeof(prog_data)); 181 182 /* Allocate the references to the uniforms that will end up in the 183 * prog_data associated with the compiled program, and which will be freed 184 * by the state cache. 185 * 186 * Note: param_count needs to be num_uniform_components * 4, since we add 187 * padding around uniform values below vec4 size, so the worst case is that 188 * every uniform is a float which gets padded to the size of a vec4. 189 */ 190 int param_count = nir->num_uniforms / 4; 191 192 prog_data.base.base.param = 193 rzalloc_array(NULL, const gl_constant_value *, param_count); 194 prog_data.base.base.pull_param = 195 rzalloc_array(NULL, const gl_constant_value *, param_count); 196 prog_data.base.base.nr_params = param_count; 197 198 if (tcp) { 199 brw_assign_common_binding_table_offsets(devinfo, &tcp->program, 200 &prog_data.base.base, 0); 201 202 prog_data.base.base.image_param = 203 rzalloc_array(NULL, struct brw_image_param, 204 tcp->program.info.num_images); 205 prog_data.base.base.nr_image_params = tcp->program.info.num_images; 206 207 brw_nir_setup_glsl_uniforms(nir, &tcp->program, &prog_data.base.base, 208 compiler->scalar_stage[MESA_SHADER_TESS_CTRL]); 209 } else { 210 /* Upload the Patch URB Header as the first two uniforms. 211 * Do the annoying scrambling so the shader doesn't have to. 212 */ 213 const float **param = (const float **) prog_data.base.base.param; 214 static float zero = 0.0f; 215 for (int i = 0; i < 8; i++) 216 param[i] = &zero; 217 218 if (key->tes_primitive_mode == GL_QUADS) { 219 for (int i = 0; i < 4; i++) 220 param[7 - i] = &ctx->TessCtrlProgram.patch_default_outer_level[i]; 221 222 param[3] = &ctx->TessCtrlProgram.patch_default_inner_level[0]; 223 param[2] = &ctx->TessCtrlProgram.patch_default_inner_level[1]; 224 } else if (key->tes_primitive_mode == GL_TRIANGLES) { 225 for (int i = 0; i < 3; i++) 226 param[7 - i] = &ctx->TessCtrlProgram.patch_default_outer_level[i]; 227 228 param[4] = &ctx->TessCtrlProgram.patch_default_inner_level[0]; 229 } else { 230 assert(key->tes_primitive_mode == GL_ISOLINES); 231 param[7] = &ctx->TessCtrlProgram.patch_default_outer_level[1]; 232 param[6] = &ctx->TessCtrlProgram.patch_default_outer_level[0]; 233 } 234 } 235 236 int st_index = -1; 237 if (unlikely((INTEL_DEBUG & DEBUG_SHADER_TIME) && tep)) 238 st_index = brw_get_shader_time_index(brw, &tep->program, ST_TCS, true); 239 240 if (unlikely(brw->perf_debug)) { 241 start_busy = brw->batch.last_bo && drm_intel_bo_busy(brw->batch.last_bo); 242 start_time = get_time(); 243 } 244 245 unsigned program_size; 246 char *error_str; 247 const unsigned *program = 248 brw_compile_tcs(compiler, brw, mem_ctx, key, &prog_data, nir, st_index, 249 &program_size, &error_str); 250 if (program == NULL) { 251 if (tep) { 252 tep->program.sh.data->LinkStatus = false; 253 ralloc_strcat(&tep->program.sh.data->InfoLog, error_str); 254 } 255 256 _mesa_problem(NULL, "Failed to compile tessellation control shader: " 257 "%s\n", error_str); 258 259 ralloc_free(mem_ctx); 260 return false; 261 } 262 263 if (unlikely(brw->perf_debug)) { 264 if (tcp) { 265 if (tcp->compiled_once) { 266 brw_tcs_debug_recompile(brw, &tcp->program, key); 267 } 268 tcp->compiled_once = true; 269 } 270 271 if (start_busy && !drm_intel_bo_busy(brw->batch.last_bo)) { 272 perf_debug("TCS compile took %.03f ms and stalled the GPU\n", 273 (get_time() - start_time) * 1000); 274 } 275 } 276 277 /* Scratch space is used for register spilling */ 278 brw_alloc_stage_scratch(brw, stage_state, 279 prog_data.base.base.total_scratch, 280 devinfo->max_tcs_threads); 281 282 brw_upload_cache(&brw->cache, BRW_CACHE_TCS_PROG, 283 key, sizeof(*key), 284 program, program_size, 285 &prog_data, sizeof(prog_data), 286 &stage_state->prog_offset, &brw->tcs.base.prog_data); 287 ralloc_free(mem_ctx); 288 289 return true; 290 } 291 292 void 293 brw_tcs_populate_key(struct brw_context *brw, 294 struct brw_tcs_prog_key *key) 295 { 296 struct brw_program *tcp = (struct brw_program *) brw->tess_ctrl_program; 297 struct brw_program *tep = (struct brw_program *) brw->tess_eval_program; 298 struct gl_program *tes_prog = &tep->program; 299 300 uint64_t per_vertex_slots = tes_prog->info.inputs_read; 301 uint32_t per_patch_slots = tes_prog->info.patch_inputs_read; 302 303 memset(key, 0, sizeof(*key)); 304 305 if (tcp) { 306 struct gl_program *prog = &tcp->program; 307 per_vertex_slots |= prog->info.outputs_written; 308 per_patch_slots |= prog->info.patch_outputs_written; 309 } 310 311 if (brw->gen < 8 || !tcp) 312 key->input_vertices = brw->ctx.TessCtrlProgram.patch_vertices; 313 key->outputs_written = per_vertex_slots; 314 key->patch_outputs_written = per_patch_slots; 315 316 /* We need to specialize our code generation for tessellation levels 317 * based on the domain the DS is expecting to tessellate. 318 */ 319 key->tes_primitive_mode = tep->program.info.tess.primitive_mode; 320 key->quads_workaround = brw->gen < 9 && 321 tep->program.info.tess.primitive_mode == GL_QUADS && 322 tep->program.info.tess.spacing == TESS_SPACING_EQUAL; 323 324 if (tcp) { 325 key->program_string_id = tcp->id; 326 327 /* _NEW_TEXTURE */ 328 brw_populate_sampler_prog_key_data(&brw->ctx, &tcp->program, &key->tex); 329 } 330 } 331 332 void 333 brw_upload_tcs_prog(struct brw_context *brw) 334 { 335 struct brw_stage_state *stage_state = &brw->tcs.base; 336 struct brw_tcs_prog_key key; 337 /* BRW_NEW_TESS_PROGRAMS */ 338 struct brw_program *tcp = (struct brw_program *) brw->tess_ctrl_program; 339 MAYBE_UNUSED struct brw_program *tep = 340 (struct brw_program *) brw->tess_eval_program; 341 assert(tep); 342 343 if (!brw_state_dirty(brw, 344 _NEW_TEXTURE, 345 BRW_NEW_PATCH_PRIMITIVE | 346 BRW_NEW_TESS_PROGRAMS)) 347 return; 348 349 brw_tcs_populate_key(brw, &key); 350 351 if (!brw_search_cache(&brw->cache, BRW_CACHE_TCS_PROG, 352 &key, sizeof(key), 353 &stage_state->prog_offset, 354 &brw->tcs.base.prog_data)) { 355 bool success = brw_codegen_tcs_prog(brw, tcp, tep, &key); 356 assert(success); 357 (void)success; 358 } 359 } 360 361 362 bool 363 brw_tcs_precompile(struct gl_context *ctx, 364 struct gl_shader_program *shader_prog, 365 struct gl_program *prog) 366 { 367 struct brw_context *brw = brw_context(ctx); 368 struct brw_tcs_prog_key key; 369 uint32_t old_prog_offset = brw->tcs.base.prog_offset; 370 struct brw_stage_prog_data *old_prog_data = brw->tcs.base.prog_data; 371 bool success; 372 373 struct brw_program *btcp = brw_program(prog); 374 const struct gl_linked_shader *tes = 375 shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL]; 376 377 memset(&key, 0, sizeof(key)); 378 379 key.program_string_id = btcp->id; 380 brw_setup_tex_for_precompile(brw, &key.tex, prog); 381 382 /* Guess that the input and output patches have the same dimensionality. */ 383 if (brw->gen < 8) { 384 key.input_vertices = shader_prog-> 385 _LinkedShaders[MESA_SHADER_TESS_CTRL]->info.TessCtrl.VerticesOut; 386 } 387 388 struct brw_program *btep; 389 if (tes) { 390 btep = brw_program(tes->Program); 391 key.tes_primitive_mode = tes->info.TessEval.PrimitiveMode; 392 key.quads_workaround = brw->gen < 9 && 393 tes->info.TessEval.PrimitiveMode == GL_QUADS && 394 tes->info.TessEval.Spacing == TESS_SPACING_EQUAL; 395 } else { 396 btep = NULL; 397 key.tes_primitive_mode = GL_TRIANGLES; 398 } 399 400 key.outputs_written = prog->nir->info->outputs_written; 401 key.patch_outputs_written = prog->nir->info->patch_outputs_written; 402 403 success = brw_codegen_tcs_prog(brw, btcp, btep, &key); 404 405 brw->tcs.base.prog_offset = old_prog_offset; 406 brw->tcs.base.prog_data = old_prog_data; 407 408 return success; 409 } 410
