/external/mesa3d/src/mesa/drivers/dri/i965/ |
gen6_constant_state.c | 32 const struct brw_stage_state *stage_state, 38 active = active && stage_state->push_const_size != 0; 57 OUT_BATCH(stage_state->push_const_size); 59 OUT_BATCH(active ? stage_state->push_const_size : 0); 74 stage_state->push_const_offset); 78 OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0); 87 OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0); 122 struct brw_stage_state *stage_state, 128 stage_state->push_const_size = 0; 142 32, &stage_state->push_const_offset) [all...] |
gen7_ds_state.c | 33 struct brw_stage_state *stage_state = &brw->tes.base; local 41 gen6_upload_push_constants(brw, &tep->program, prog_data, stage_state, 45 gen7_upload_constant_state(brw, stage_state, tep, _3DSTATE_CONSTANT_DS); 64 const struct brw_stage_state *stage_state = &brw->tes.base; local 69 const struct brw_stage_prog_data *prog_data = stage_state->prog_data; 71 brw_vue_prog_data(stage_state->prog_data); 73 brw_tes_prog_data(stage_state->prog_data); 81 OUT_BATCH(stage_state->prog_offset); 82 OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4), 87 OUT_RELOC(stage_state->scratch_bo [all...] |
gen7_hs_state.c | 33 struct brw_stage_state *stage_state = &brw->tcs.base; local 43 gen6_upload_push_constants(brw, &tcp->program, prog_data, stage_state, 47 gen7_upload_constant_state(brw, stage_state, active, _3DSTATE_CONSTANT_HS); 67 const struct brw_stage_state *stage_state = &brw->tcs.base; local 71 const struct brw_stage_prog_data *prog_data = stage_state->prog_data; 73 brw_tcs_prog_data(stage_state->prog_data); 78 OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4), 87 OUT_BATCH(stage_state->prog_offset); 89 OUT_RELOC(stage_state->scratch_bo, 91 ffs(stage_state->per_thread_scratch) - 11) [all...] |
gen6_vs_state.c | 40 struct brw_stage_state *stage_state = &brw->vs.base; local 48 gen6_upload_push_constants(brw, &vp->program, prog_data, stage_state, 55 gen7_upload_constant_state(brw, stage_state, true /* active */, 77 const struct brw_stage_state *stage_state = &brw->vs.base; local 78 const struct brw_stage_prog_data *prog_data = stage_state->prog_data; 80 brw_vue_prog_data(stage_state->prog_data); 95 if (stage_state->push_const_size == 0) { 112 OUT_BATCH(stage_state->push_const_offset + 113 stage_state->push_const_size - 1); 125 OUT_BATCH(stage_state->prog_offset) [all...] |
gen7_vs_state.c | 36 const struct brw_stage_state *stage_state = &brw->vs.base; local 37 const struct brw_stage_prog_data *prog_data = stage_state->prog_data; 39 brw_vue_prog_data(stage_state->prog_data); 52 OUT_BATCH(stage_state->prog_offset); 54 ((ALIGN(stage_state->sampler_count, 4)/4) << 60 OUT_RELOC(stage_state->scratch_bo, 62 ffs(stage_state->per_thread_scratch) - 11);
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gen8_hs_state.c | 33 const struct brw_stage_state *stage_state = &brw->tcs.base; local 37 const struct brw_stage_prog_data *prog_data = stage_state->prog_data; 39 brw_tcs_prog_data(stage_state->prog_data); 44 OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4), 53 OUT_BATCH(stage_state->prog_offset); 56 OUT_RELOC64(stage_state->scratch_bo, 58 ffs(stage_state->per_thread_scratch) - 11);
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gen8_vs_state.c | 36 const struct brw_stage_state *stage_state = &brw->vs.base; local 40 const struct brw_stage_prog_data *prog_data = stage_state->prog_data; 42 brw_vue_prog_data(stage_state->prog_data); 52 OUT_BATCH(stage_state->prog_offset); 55 ((ALIGN(stage_state->sampler_count, 4) / 4) << 61 OUT_RELOC64(stage_state->scratch_bo, 63 ffs(stage_state->per_thread_scratch) - 11);
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gen7_gs_state.c | 33 const struct brw_stage_state *stage_state = &brw->gs.base; local 39 const struct brw_stage_prog_data *prog_data = stage_state->prog_data; 41 brw_vue_prog_data(stage_state->prog_data); 43 brw_gs_prog_data(stage_state->prog_data); 63 OUT_BATCH(stage_state->prog_offset); 64 OUT_BATCH(((ALIGN(stage_state->sampler_count, 4)/4) << 70 OUT_RELOC(stage_state->scratch_bo, 72 ffs(stage_state->per_thread_scratch) - 11);
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gen8_ds_state.c | 33 const struct brw_stage_state *stage_state = &brw->tes.base; local 38 const struct brw_stage_prog_data *prog_data = stage_state->prog_data; 40 brw_vue_prog_data(stage_state->prog_data); 42 brw_tes_prog_data(stage_state->prog_data); 48 OUT_BATCH(stage_state->prog_offset); 50 OUT_BATCH(SET_FIELD(DIV_ROUND_UP(stage_state->sampler_count, 4), 55 OUT_RELOC64(stage_state->scratch_bo, 57 ffs(stage_state->per_thread_scratch) - 11);
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gen8_gs_state.c | 33 const struct brw_stage_state *stage_state = &brw->gs.base; local 37 const struct brw_stage_prog_data *prog_data = stage_state->prog_data; 39 brw_vue_prog_data(stage_state->prog_data); 41 brw_gs_prog_data(stage_state->prog_data); 53 OUT_BATCH(stage_state->prog_offset); 56 ((ALIGN(stage_state->sampler_count, 4)/4) << 62 OUT_RELOC64(stage_state->scratch_bo, 64 ffs(stage_state->per_thread_scratch) - 11);
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brw_vs_state.c | 43 struct brw_stage_state *stage_state = &brw->vs.base; local 44 const struct brw_stage_prog_data *prog_data = stage_state->prog_data; 46 brw_vue_prog_data(stage_state->prog_data); 51 sizeof(*vs), 32, &stage_state->state_offset); 58 stage_state->state_offset + 60 stage_state->prog_offset + 87 stage_state->scratch_bo->offset64 >> 10; /* reloc */ 89 ffs(stage_state->per_thread_scratch) - 11; 146 vs->vs5.sampler_count = (stage_state->sampler_count + 3) / 4; 159 if (stage_state->sampler_count) [all...] |
gen7_cs_state.c | 46 struct brw_stage_state *stage_state = &brw->cs.base; local 47 struct brw_stage_prog_data *prog_data = stage_state->prog_data; 53 brw, &stage_state->surf_offset[ 61 32, &stage_state->bind_bo_offset); 72 OUT_RELOC64(stage_state->scratch_bo, 74 ffs(stage_state->per_thread_scratch) - 11); 79 OUT_RELOC(stage_state->scratch_bo, 81 ffs(stage_state->per_thread_scratch) - 12); 86 OUT_RELOC(stage_state->scratch_bo, 88 stage_state->per_thread_scratch / 1024 - 1) 280 struct brw_stage_state *stage_state = &brw->cs.base; local 315 struct brw_stage_state *stage_state = &brw->cs.base; local [all...] |
gen6_gs_state.c | 37 struct brw_stage_state *stage_state = &brw->gs.base; local 47 gen6_upload_push_constants(brw, &gp->program, prog_data, stage_state, 52 gen7_upload_constant_state(brw, stage_state, gp, _3DSTATE_CONSTANT_GS); 99 const struct brw_stage_state *stage_state = &brw->gs.base; local 100 const struct brw_stage_prog_data *prog_data = stage_state->prog_data; 102 brw_vue_prog_data(stage_state->prog_data); 104 if (!active || stage_state->push_const_size == 0) { 121 OUT_BATCH(stage_state->push_const_offset + 122 stage_state->push_const_size - 1); 132 OUT_BATCH(stage_state->prog_offset) [all...] |
gen6_wm_state.c | 43 struct brw_stage_state *stage_state = &brw->wm.base; local 52 stage_state, AUB_TRACE_WM_CONSTANTS); 75 const struct brw_stage_state *stage_state, 108 OUT_BATCH(stage_state->push_const_offset + 109 stage_state->push_const_size - 1); 127 dw2 |= (ALIGN(stage_state->sampler_count, 4) / 4) << 146 ksp0 = stage_state->prog_offset; 147 ksp2 = stage_state->prog_offset + prog_data->prog_offset_2; 224 OUT_RELOC(stage_state->scratch_bo, 226 ffs(stage_state->per_thread_scratch) - 11) [all...] |
brw_vs_surface_state.c | 56 struct brw_stage_state *stage_state, 63 if (stage_state->surf_offset[surf_index]) { 64 stage_state->surf_offset[surf_index] = 0; 97 &stage_state->surf_offset[surf_index]); 113 struct brw_stage_state *stage_state = &brw->vs.base; local 124 stage_state, prog_data);
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gen8_ps_state.c | 191 const struct brw_stage_state *stage_state, 204 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); 259 ksp0 = stage_state->prog_offset; 260 ksp2 = stage_state->prog_offset + prog_data->prog_offset_2; 268 OUT_RELOC64(stage_state->scratch_bo, 270 ffs(stage_state->per_thread_scratch) - 11);
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brw_binding_tables.c | 92 struct brw_stage_state *stage_state) 96 if (stage_state->bind_bo_offset == 0 && brw->gen < 9) 99 stage_state->bind_bo_offset = 0; 104 brw, &stage_state->surf_offset[ 113 gen7_update_binding_table_from_array(brw, stage_state->stage, 114 stage_state->surf_offset, 121 &stage_state->bind_bo_offset); 124 memcpy(bind, stage_state->surf_offset, 133 stage_state->bind_bo_offset = 142 (stage_state->bind_bo_offset >> 1) [all...] |
brw_gs_surface_state.c | 41 struct brw_stage_state *stage_state = &brw->gs.base; local 55 stage_state, prog_data);
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brw_tcs_surface_state.c | 41 struct brw_stage_state *stage_state = &brw->tcs.base; local 55 stage_state, prog_data);
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brw_tes_surface_state.c | 41 struct brw_stage_state *stage_state = &brw->tes.base; local 55 stage_state, prog_data);
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brw_gs.c | 84 struct brw_stage_state *stage_state = &brw->gs.base; local 159 brw_alloc_stage_scratch(brw, stage_state, 167 &stage_state->prog_offset, &brw->gs.base.prog_data); 200 struct brw_stage_state *stage_state = &brw->gs.base; local 228 &stage_state->prog_offset,
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brw_tes.c | 73 struct brw_stage_state *stage_state = &brw->tes.base; local 149 brw_alloc_stage_scratch(brw, stage_state, 157 &stage_state->prog_offset, &brw->tes.base.prog_data); 199 struct brw_stage_state *stage_state = &brw->tes.base; local 213 &stage_state->prog_offset,
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gen7_wm_state.c | 149 const struct brw_stage_state *stage_state, 162 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); 231 ksp0 = stage_state->prog_offset; 232 ksp2 = stage_state->prog_offset + prog_data->prog_offset_2; 241 ffs(stage_state->per_thread_scratch) - 11);
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brw_sampler_state.c | 54 struct brw_stage_state *stage_state) 66 stage_state->stage == MESA_SHADER_VERTEX) { 71 OUT_BATCH(packet_headers[stage_state->stage] << 16 | (2 - 2)); 72 OUT_BATCH(stage_state->sampler_offset); 585 struct brw_stage_state *stage_state) 588 uint32_t sampler_count = stage_state->sampler_count; 601 32, &stage_state->sampler_offset); 604 uint32_t batch_offset_for_sampler_state = stage_state->sampler_offset; 619 if (brw->gen >= 7 && stage_state->stage != MESA_SHADER_COMPUTE) { 621 gen7_emit_sampler_state_pointers_xs(brw, stage_state); [all...] |
brw_state.h | 184 struct brw_stage_state *stage_state); 310 const struct brw_stage_state *stage_state, 350 const struct brw_stage_state *stage_state, 373 struct brw_stage_state *stage_state, 379 const struct brw_stage_state *stage_state,
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