Home | History | Annotate | Download | only in ARM
      1 //===- Thumb1RegisterInfo.h - Thumb-1 Register Information Impl -*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the Thumb-1 implementation of the TargetRegisterInfo
     11 // class.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef THUMB1REGISTERINFO_H
     16 #define THUMB1REGISTERINFO_H
     17 
     18 #include "ARM.h"
     19 #include "ARMRegisterInfo.h"
     20 #include "llvm/Target/TargetRegisterInfo.h"
     21 
     22 namespace llvm {
     23   class ARMSubtarget;
     24   class ARMBaseInstrInfo;
     25   class Type;
     26 
     27 struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
     28 public:
     29   Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
     30 
     31   const TargetRegisterClass*
     32   getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
     33 
     34   const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
     35 
     36   /// emitLoadConstPool - Emits a load from constpool to materialize the
     37   /// specified immediate.
     38  void emitLoadConstPool(MachineBasicBlock &MBB,
     39                         MachineBasicBlock::iterator &MBBI,
     40                         DebugLoc dl,
     41                         unsigned DestReg, unsigned SubIdx, int Val,
     42                         ARMCC::CondCodes Pred = ARMCC::AL,
     43                         unsigned PredReg = 0,
     44                         unsigned MIFlags = MachineInstr::NoFlags) const;
     45 
     46   /// Code Generation virtual methods...
     47   void eliminateCallFramePseudoInstr(MachineFunction &MF,
     48                                      MachineBasicBlock &MBB,
     49                                      MachineBasicBlock::iterator I) const;
     50 
     51   // rewrite MI to access 'Offset' bytes from the FP. Update Offset to be
     52   // however much remains to be handled. Return 'true' if no further
     53   // work is required.
     54   bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
     55                          unsigned FrameReg, int &Offset,
     56                          const ARMBaseInstrInfo &TII) const;
     57   void resolveFrameIndex(MachineBasicBlock::iterator I,
     58                          unsigned BaseReg, int64_t Offset) const;
     59   bool saveScavengerRegister(MachineBasicBlock &MBB,
     60                              MachineBasicBlock::iterator I,
     61                              MachineBasicBlock::iterator &UseMI,
     62                              const TargetRegisterClass *RC,
     63                              unsigned Reg) const;
     64   void eliminateFrameIndex(MachineBasicBlock::iterator II,
     65                            int SPAdj, RegScavenger *RS = NULL) const;
     66 };
     67 }
     68 
     69 #endif // THUMB1REGISTERINFO_H
     70