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      1 //===- llvm/InlineAsm.h - Class to represent inline asm strings -*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This class represents the inline asm strings, which are Value*'s that are
     11 // used as the callee operand of call instructions.  InlineAsm's are uniqued
     12 // like constants, and created via InlineAsm::get(...).
     13 //
     14 //===----------------------------------------------------------------------===//
     15 
     16 #ifndef LLVM_IR_INLINEASM_H
     17 #define LLVM_IR_INLINEASM_H
     18 
     19 #include "llvm/ADT/StringRef.h"
     20 #include "llvm/IR/Value.h"
     21 #include <cassert>
     22 #include <string>
     23 #include <vector>
     24 
     25 namespace llvm {
     26 
     27 class FunctionType;
     28 class PointerType;
     29 template <class ConstantClass> class ConstantUniqueMap;
     30 
     31 class InlineAsm : public Value {
     32 public:
     33   enum AsmDialect {
     34     AD_ATT,
     35     AD_Intel
     36   };
     37 
     38 private:
     39   friend struct InlineAsmKeyType;
     40   friend class ConstantUniqueMap<InlineAsm>;
     41 
     42   std::string AsmString, Constraints;
     43   FunctionType *FTy;
     44   bool HasSideEffects;
     45   bool IsAlignStack;
     46   AsmDialect Dialect;
     47 
     48   InlineAsm(FunctionType *Ty, const std::string &AsmString,
     49             const std::string &Constraints, bool hasSideEffects,
     50             bool isAlignStack, AsmDialect asmDialect);
     51   ~InlineAsm() override;
     52 
     53   /// When the ConstantUniqueMap merges two types and makes two InlineAsms
     54   /// identical, it destroys one of them with this method.
     55   void destroyConstant();
     56 
     57 public:
     58   InlineAsm(const InlineAsm &) = delete;
     59   InlineAsm &operator=(const InlineAsm &) = delete;
     60 
     61   /// InlineAsm::get - Return the specified uniqued inline asm string.
     62   ///
     63   static InlineAsm *get(FunctionType *Ty, StringRef AsmString,
     64                         StringRef Constraints, bool hasSideEffects,
     65                         bool isAlignStack = false,
     66                         AsmDialect asmDialect = AD_ATT);
     67 
     68   bool hasSideEffects() const { return HasSideEffects; }
     69   bool isAlignStack() const { return IsAlignStack; }
     70   AsmDialect getDialect() const { return Dialect; }
     71 
     72   /// getType - InlineAsm's are always pointers.
     73   ///
     74   PointerType *getType() const {
     75     return reinterpret_cast<PointerType*>(Value::getType());
     76   }
     77 
     78   /// getFunctionType - InlineAsm's are always pointers to functions.
     79   ///
     80   FunctionType *getFunctionType() const;
     81 
     82   const std::string &getAsmString() const { return AsmString; }
     83   const std::string &getConstraintString() const { return Constraints; }
     84 
     85   /// Verify - This static method can be used by the parser to check to see if
     86   /// the specified constraint string is legal for the type.  This returns true
     87   /// if legal, false if not.
     88   ///
     89   static bool Verify(FunctionType *Ty, StringRef Constraints);
     90 
     91   // Constraint String Parsing
     92   enum ConstraintPrefix {
     93     isInput,            // 'x'
     94     isOutput,           // '=x'
     95     isClobber           // '~x'
     96   };
     97 
     98   typedef std::vector<std::string> ConstraintCodeVector;
     99 
    100   struct SubConstraintInfo {
    101     /// MatchingInput - If this is not -1, this is an output constraint where an
    102     /// input constraint is required to match it (e.g. "0").  The value is the
    103     /// constraint number that matches this one (for example, if this is
    104     /// constraint #0 and constraint #4 has the value "0", this will be 4).
    105     signed char MatchingInput = -1;
    106 
    107     /// Code - The constraint code, either the register name (in braces) or the
    108     /// constraint letter/number.
    109     ConstraintCodeVector Codes;
    110 
    111     /// Default constructor.
    112     SubConstraintInfo() = default;
    113   };
    114 
    115   typedef std::vector<SubConstraintInfo> SubConstraintInfoVector;
    116   struct ConstraintInfo;
    117   typedef std::vector<ConstraintInfo> ConstraintInfoVector;
    118 
    119   struct ConstraintInfo {
    120     /// Type - The basic type of the constraint: input/output/clobber
    121     ///
    122     ConstraintPrefix Type = isInput;
    123 
    124     /// isEarlyClobber - "&": output operand writes result before inputs are all
    125     /// read.  This is only ever set for an output operand.
    126     bool isEarlyClobber = false;
    127 
    128     /// MatchingInput - If this is not -1, this is an output constraint where an
    129     /// input constraint is required to match it (e.g. "0").  The value is the
    130     /// constraint number that matches this one (for example, if this is
    131     /// constraint #0 and constraint #4 has the value "0", this will be 4).
    132     signed char MatchingInput = -1;
    133 
    134     /// hasMatchingInput - Return true if this is an output constraint that has
    135     /// a matching input constraint.
    136     bool hasMatchingInput() const { return MatchingInput != -1; }
    137 
    138     /// isCommutative - This is set to true for a constraint that is commutative
    139     /// with the next operand.
    140     bool isCommutative = false;
    141 
    142     /// isIndirect - True if this operand is an indirect operand.  This means
    143     /// that the address of the source or destination is present in the call
    144     /// instruction, instead of it being returned or passed in explicitly.  This
    145     /// is represented with a '*' in the asm string.
    146     bool isIndirect = false;
    147 
    148     /// Code - The constraint code, either the register name (in braces) or the
    149     /// constraint letter/number.
    150     ConstraintCodeVector Codes;
    151 
    152     /// isMultipleAlternative - '|': has multiple-alternative constraints.
    153     bool isMultipleAlternative = false;
    154 
    155     /// multipleAlternatives - If there are multiple alternative constraints,
    156     /// this array will contain them.  Otherwise it will be empty.
    157     SubConstraintInfoVector multipleAlternatives;
    158 
    159     /// The currently selected alternative constraint index.
    160     unsigned currentAlternativeIndex = 0;
    161 
    162     /// Default constructor.
    163     ConstraintInfo() = default;
    164 
    165     /// Parse - Analyze the specified string (e.g. "=*&{eax}") and fill in the
    166     /// fields in this structure.  If the constraint string is not understood,
    167     /// return true, otherwise return false.
    168     bool Parse(StringRef Str, ConstraintInfoVector &ConstraintsSoFar);
    169 
    170     /// selectAlternative - Point this constraint to the alternative constraint
    171     /// indicated by the index.
    172     void selectAlternative(unsigned index);
    173   };
    174 
    175   /// ParseConstraints - Split up the constraint string into the specific
    176   /// constraints and their prefixes.  If this returns an empty vector, and if
    177   /// the constraint string itself isn't empty, there was an error parsing.
    178   static ConstraintInfoVector ParseConstraints(StringRef ConstraintString);
    179 
    180   /// ParseConstraints - Parse the constraints of this inlineasm object,
    181   /// returning them the same way that ParseConstraints(str) does.
    182   ConstraintInfoVector ParseConstraints() const {
    183     return ParseConstraints(Constraints);
    184   }
    185 
    186   // Methods for support type inquiry through isa, cast, and dyn_cast:
    187   static inline bool classof(const Value *V) {
    188     return V->getValueID() == Value::InlineAsmVal;
    189   }
    190 
    191   // These are helper methods for dealing with flags in the INLINEASM SDNode
    192   // in the backend.
    193   //
    194   // The encoding of the flag word is currently:
    195   //   Bits 2-0 - A Kind_* value indicating the kind of the operand.
    196   //   Bits 15-3 - The number of SDNode operands associated with this inline
    197   //               assembly operand.
    198   //   If bit 31 is set:
    199   //     Bit 30-16 - The operand number that this operand must match.
    200   //                 When bits 2-0 are Kind_Mem, the Constraint_* value must be
    201   //                 obtained from the flags for this operand number.
    202   //   Else if bits 2-0 are Kind_Mem:
    203   //     Bit 30-16 - A Constraint_* value indicating the original constraint
    204   //                 code.
    205   //   Else:
    206   //     Bit 30-16 - The register class ID to use for the operand.
    207 
    208   enum : uint32_t {
    209     // Fixed operands on an INLINEASM SDNode.
    210     Op_InputChain = 0,
    211     Op_AsmString = 1,
    212     Op_MDNode = 2,
    213     Op_ExtraInfo = 3,    // HasSideEffects, IsAlignStack, AsmDialect.
    214     Op_FirstOperand = 4,
    215 
    216     // Fixed operands on an INLINEASM MachineInstr.
    217     MIOp_AsmString = 0,
    218     MIOp_ExtraInfo = 1,    // HasSideEffects, IsAlignStack, AsmDialect.
    219     MIOp_FirstOperand = 2,
    220 
    221     // Interpretation of the MIOp_ExtraInfo bit field.
    222     Extra_HasSideEffects = 1,
    223     Extra_IsAlignStack = 2,
    224     Extra_AsmDialect = 4,
    225     Extra_MayLoad = 8,
    226     Extra_MayStore = 16,
    227     Extra_IsConvergent = 32,
    228 
    229     // Inline asm operands map to multiple SDNode / MachineInstr operands.
    230     // The first operand is an immediate describing the asm operand, the low
    231     // bits is the kind:
    232     Kind_RegUse = 1,             // Input register, "r".
    233     Kind_RegDef = 2,             // Output register, "=r".
    234     Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
    235     Kind_Clobber = 4,            // Clobbered register, "~r".
    236     Kind_Imm = 5,                // Immediate.
    237     Kind_Mem = 6,                // Memory operand, "m".
    238 
    239     // Memory constraint codes.
    240     // These could be tablegenerated but there's little need to do that since
    241     // there's plenty of space in the encoding to support the union of all
    242     // constraint codes for all targets.
    243     Constraint_Unknown = 0,
    244     Constraint_es,
    245     Constraint_i,
    246     Constraint_m,
    247     Constraint_o,
    248     Constraint_v,
    249     Constraint_Q,
    250     Constraint_R,
    251     Constraint_S,
    252     Constraint_T,
    253     Constraint_Um,
    254     Constraint_Un,
    255     Constraint_Uq,
    256     Constraint_Us,
    257     Constraint_Ut,
    258     Constraint_Uv,
    259     Constraint_Uy,
    260     Constraint_X,
    261     Constraint_Z,
    262     Constraint_ZC,
    263     Constraint_Zy,
    264     Constraints_Max = Constraint_Zy,
    265     Constraints_ShiftAmount = 16,
    266 
    267     Flag_MatchingOperand = 0x80000000
    268   };
    269 
    270   static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
    271     assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
    272     assert(Kind >= Kind_RegUse && Kind <= Kind_Mem && "Invalid Kind");
    273     return Kind | (NumOps << 3);
    274   }
    275 
    276   static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;}
    277   static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; }
    278   static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; }
    279   static bool isRegDefEarlyClobberKind(unsigned Flag) {
    280     return getKind(Flag) == Kind_RegDefEarlyClobber;
    281   }
    282   static bool isClobberKind(unsigned Flag) {
    283     return getKind(Flag) == Kind_Clobber;
    284   }
    285 
    286   /// getFlagWordForMatchingOp - Augment an existing flag word returned by
    287   /// getFlagWord with information indicating that this input operand is tied
    288   /// to a previous output operand.
    289   static unsigned getFlagWordForMatchingOp(unsigned InputFlag,
    290                                            unsigned MatchedOperandNo) {
    291     assert(MatchedOperandNo <= 0x7fff && "Too big matched operand");
    292     assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
    293     return InputFlag | Flag_MatchingOperand | (MatchedOperandNo << 16);
    294   }
    295 
    296   /// getFlagWordForRegClass - Augment an existing flag word returned by
    297   /// getFlagWord with the required register class for the following register
    298   /// operands.
    299   /// A tied use operand cannot have a register class, use the register class
    300   /// from the def operand instead.
    301   static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) {
    302     // Store RC + 1, reserve the value 0 to mean 'no register class'.
    303     ++RC;
    304     assert(!isImmKind(InputFlag) && "Immediates cannot have a register class");
    305     assert(!isMemKind(InputFlag) && "Memory operand cannot have a register class");
    306     assert(RC <= 0x7fff && "Too large register class ID");
    307     assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
    308     return InputFlag | (RC << 16);
    309   }
    310 
    311   /// Augment an existing flag word returned by getFlagWord with the constraint
    312   /// code for a memory constraint.
    313   static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint) {
    314     assert(isMemKind(InputFlag) && "InputFlag is not a memory constraint!");
    315     assert(Constraint <= 0x7fff && "Too large a memory constraint ID");
    316     assert(Constraint <= Constraints_Max && "Unknown constraint ID");
    317     assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
    318     return InputFlag | (Constraint << Constraints_ShiftAmount);
    319   }
    320 
    321   static unsigned convertMemFlagWordToMatchingFlagWord(unsigned InputFlag) {
    322     assert(isMemKind(InputFlag));
    323     return InputFlag & ~(0x7fff << Constraints_ShiftAmount);
    324   }
    325 
    326   static unsigned getKind(unsigned Flags) {
    327     return Flags & 7;
    328   }
    329 
    330   static unsigned getMemoryConstraintID(unsigned Flag) {
    331     assert(isMemKind(Flag));
    332     return (Flag >> Constraints_ShiftAmount) & 0x7fff;
    333   }
    334 
    335   /// getNumOperandRegisters - Extract the number of registers field from the
    336   /// inline asm operand flag.
    337   static unsigned getNumOperandRegisters(unsigned Flag) {
    338     return (Flag & 0xffff) >> 3;
    339   }
    340 
    341   /// isUseOperandTiedToDef - Return true if the flag of the inline asm
    342   /// operand indicates it is an use operand that's matched to a def operand.
    343   static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx) {
    344     if ((Flag & Flag_MatchingOperand) == 0)
    345       return false;
    346     Idx = (Flag & ~Flag_MatchingOperand) >> 16;
    347     return true;
    348   }
    349 
    350   /// hasRegClassConstraint - Returns true if the flag contains a register
    351   /// class constraint.  Sets RC to the register class ID.
    352   static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) {
    353     if (Flag & Flag_MatchingOperand)
    354       return false;
    355     unsigned High = Flag >> 16;
    356     // getFlagWordForRegClass() uses 0 to mean no register class, and otherwise
    357     // stores RC + 1.
    358     if (!High)
    359       return false;
    360     RC = High - 1;
    361     return true;
    362   }
    363 };
    364 
    365 } // end namespace llvm
    366 
    367 #endif // LLVM_IR_INLINEASM_H
    368