1 //===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes an abstract interface used to get information about a 11 // target machines register file. This information is used for a variety of 12 // purposed, especially register allocation. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_MC_MCREGISTERINFO_H 17 #define LLVM_MC_MCREGISTERINFO_H 18 19 #include "llvm/ADT/DenseMap.h" 20 #include "llvm/ADT/iterator_range.h" 21 #include "llvm/MC/LaneBitmask.h" 22 #include <cassert> 23 #include <cstdint> 24 #include <utility> 25 26 namespace llvm { 27 28 /// An unsigned integer type large enough to represent all physical registers, 29 /// but not necessarily virtual registers. 30 using MCPhysReg = uint16_t; 31 32 /// MCRegisterClass - Base class of TargetRegisterClass. 33 class MCRegisterClass { 34 public: 35 using iterator = const MCPhysReg*; 36 using const_iterator = const MCPhysReg*; 37 38 const iterator RegsBegin; 39 const uint8_t *const RegSet; 40 const uint32_t NameIdx; 41 const uint16_t RegsSize; 42 const uint16_t RegSetSize; 43 const uint16_t ID; 44 const uint16_t PhysRegSize; 45 const int8_t CopyCost; 46 const bool Allocatable; 47 48 /// getID() - Return the register class ID number. 49 /// 50 unsigned getID() const { return ID; } 51 52 /// begin/end - Return all of the registers in this class. 53 /// 54 iterator begin() const { return RegsBegin; } 55 iterator end() const { return RegsBegin + RegsSize; } 56 57 /// getNumRegs - Return the number of registers in this class. 58 /// 59 unsigned getNumRegs() const { return RegsSize; } 60 61 /// getRegister - Return the specified register in the class. 62 /// 63 unsigned getRegister(unsigned i) const { 64 assert(i < getNumRegs() && "Register number out of range!"); 65 return RegsBegin[i]; 66 } 67 68 /// contains - Return true if the specified register is included in this 69 /// register class. This does not include virtual registers. 70 bool contains(unsigned Reg) const { 71 unsigned InByte = Reg % 8; 72 unsigned Byte = Reg / 8; 73 if (Byte >= RegSetSize) 74 return false; 75 return (RegSet[Byte] & (1 << InByte)) != 0; 76 } 77 78 /// contains - Return true if both registers are in this class. 79 bool contains(unsigned Reg1, unsigned Reg2) const { 80 return contains(Reg1) && contains(Reg2); 81 } 82 83 /// Return the size of the physical register in bytes. 84 unsigned getPhysRegSize() const { return PhysRegSize; } 85 /// Temporary function to allow out-of-tree targets to switch. 86 unsigned getSize() const { return getPhysRegSize(); } 87 88 /// getCopyCost - Return the cost of copying a value between two registers in 89 /// this class. A negative number means the register class is very expensive 90 /// to copy e.g. status flag register classes. 91 int getCopyCost() const { return CopyCost; } 92 93 /// isAllocatable - Return true if this register class may be used to create 94 /// virtual registers. 95 bool isAllocatable() const { return Allocatable; } 96 }; 97 98 /// MCRegisterDesc - This record contains information about a particular 99 /// register. The SubRegs field is a zero terminated array of registers that 100 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers 101 /// of AX. The SuperRegs field is a zero terminated array of registers that are 102 /// super-registers of the specific register, e.g. RAX, EAX, are 103 /// super-registers of AX. 104 /// 105 struct MCRegisterDesc { 106 uint32_t Name; // Printable name for the reg (for debugging) 107 uint32_t SubRegs; // Sub-register set, described above 108 uint32_t SuperRegs; // Super-register set, described above 109 110 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each 111 // sub-register in SubRegs. 112 uint32_t SubRegIndices; 113 114 // RegUnits - Points to the list of register units. The low 4 bits holds the 115 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. 116 uint32_t RegUnits; 117 118 /// Index into list with lane mask sequences. The sequence contains a lanemask 119 /// for every register unit. 120 uint16_t RegUnitLaneMasks; 121 }; 122 123 /// MCRegisterInfo base class - We assume that the target defines a static 124 /// array of MCRegisterDesc objects that represent all of the machine 125 /// registers that the target has. As such, we simply have to track a pointer 126 /// to this array so that we can turn register number into a register 127 /// descriptor. 128 /// 129 /// Note this class is designed to be a base class of TargetRegisterInfo, which 130 /// is the interface used by codegen. However, specific targets *should never* 131 /// specialize this class. MCRegisterInfo should only contain getters to access 132 /// TableGen generated physical register data. It must not be extended with 133 /// virtual methods. 134 /// 135 class MCRegisterInfo { 136 public: 137 using regclass_iterator = const MCRegisterClass *; 138 139 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be 140 /// performed with a binary search. 141 struct DwarfLLVMRegPair { 142 unsigned FromReg; 143 unsigned ToReg; 144 145 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } 146 }; 147 148 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg 149 /// index, -1 in any being invalid. 150 struct SubRegCoveredBits { 151 uint16_t Offset; 152 uint16_t Size; 153 }; 154 155 private: 156 const MCRegisterDesc *Desc; // Pointer to the descriptor array 157 unsigned NumRegs; // Number of entries in the array 158 unsigned RAReg; // Return address register 159 unsigned PCReg; // Program counter register 160 const MCRegisterClass *Classes; // Pointer to the regclass array 161 unsigned NumClasses; // Number of entries in the array 162 unsigned NumRegUnits; // Number of regunits. 163 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table. 164 const MCPhysReg *DiffLists; // Pointer to the difflists array 165 const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences 166 // for register units. 167 const char *RegStrings; // Pointer to the string table. 168 const char *RegClassStrings; // Pointer to the class strings. 169 const uint16_t *SubRegIndices; // Pointer to the subreg lookup 170 // array. 171 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered 172 // bit ranges array. 173 unsigned NumSubRegIndices; // Number of subreg indices. 174 const uint16_t *RegEncodingTable; // Pointer to array of register 175 // encodings. 176 177 unsigned L2DwarfRegsSize; 178 unsigned EHL2DwarfRegsSize; 179 unsigned Dwarf2LRegsSize; 180 unsigned EHDwarf2LRegsSize; 181 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping 182 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 183 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping 184 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 185 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping 186 DenseMap<unsigned, int> L2CVRegs; // LLVM to CV regs mapping 187 188 public: 189 /// DiffListIterator - Base iterator class that can traverse the 190 /// differentially encoded register and regunit lists in DiffLists. 191 /// Don't use this class directly, use one of the specialized sub-classes 192 /// defined below. 193 class DiffListIterator { 194 uint16_t Val = 0; 195 const MCPhysReg *List = nullptr; 196 197 protected: 198 /// Create an invalid iterator. Call init() to point to something useful. 199 DiffListIterator() = default; 200 201 /// init - Point the iterator to InitVal, decoding subsequent values from 202 /// DiffList. The iterator will initially point to InitVal, sub-classes are 203 /// responsible for skipping the seed value if it is not part of the list. 204 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) { 205 Val = InitVal; 206 List = DiffList; 207 } 208 209 /// advance - Move to the next list position, return the applied 210 /// differential. This function does not detect the end of the list, that 211 /// is the caller's responsibility (by checking for a 0 return value). 212 unsigned advance() { 213 assert(isValid() && "Cannot move off the end of the list."); 214 MCPhysReg D = *List++; 215 Val += D; 216 return D; 217 } 218 219 public: 220 /// isValid - returns true if this iterator is not yet at the end. 221 bool isValid() const { return List; } 222 223 /// Dereference the iterator to get the value at the current position. 224 unsigned operator*() const { return Val; } 225 226 /// Pre-increment to move to the next position. 227 void operator++() { 228 // The end of the list is encoded as a 0 differential. 229 if (!advance()) 230 List = nullptr; 231 } 232 }; 233 234 // These iterators are allowed to sub-class DiffListIterator and access 235 // internal list pointers. 236 friend class MCSubRegIterator; 237 friend class MCSubRegIndexIterator; 238 friend class MCSuperRegIterator; 239 friend class MCRegUnitIterator; 240 friend class MCRegUnitMaskIterator; 241 friend class MCRegUnitRootIterator; 242 243 /// \brief Initialize MCRegisterInfo, called by TableGen 244 /// auto-generated routines. *DO NOT USE*. 245 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, 246 unsigned PC, 247 const MCRegisterClass *C, unsigned NC, 248 const MCPhysReg (*RURoots)[2], 249 unsigned NRU, 250 const MCPhysReg *DL, 251 const LaneBitmask *RUMS, 252 const char *Strings, 253 const char *ClassStrings, 254 const uint16_t *SubIndices, 255 unsigned NumIndices, 256 const SubRegCoveredBits *SubIdxRanges, 257 const uint16_t *RET) { 258 Desc = D; 259 NumRegs = NR; 260 RAReg = RA; 261 PCReg = PC; 262 Classes = C; 263 DiffLists = DL; 264 RegUnitMaskSequences = RUMS; 265 RegStrings = Strings; 266 RegClassStrings = ClassStrings; 267 NumClasses = NC; 268 RegUnitRoots = RURoots; 269 NumRegUnits = NRU; 270 SubRegIndices = SubIndices; 271 NumSubRegIndices = NumIndices; 272 SubRegIdxRanges = SubIdxRanges; 273 RegEncodingTable = RET; 274 275 // Initialize DWARF register mapping variables 276 EHL2DwarfRegs = nullptr; 277 EHL2DwarfRegsSize = 0; 278 L2DwarfRegs = nullptr; 279 L2DwarfRegsSize = 0; 280 EHDwarf2LRegs = nullptr; 281 EHDwarf2LRegsSize = 0; 282 Dwarf2LRegs = nullptr; 283 Dwarf2LRegsSize = 0; 284 } 285 286 /// \brief Used to initialize LLVM register to Dwarf 287 /// register number mapping. Called by TableGen auto-generated routines. 288 /// *DO NOT USE*. 289 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, 290 bool isEH) { 291 if (isEH) { 292 EHL2DwarfRegs = Map; 293 EHL2DwarfRegsSize = Size; 294 } else { 295 L2DwarfRegs = Map; 296 L2DwarfRegsSize = Size; 297 } 298 } 299 300 /// \brief Used to initialize Dwarf register to LLVM 301 /// register number mapping. Called by TableGen auto-generated routines. 302 /// *DO NOT USE*. 303 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, 304 bool isEH) { 305 if (isEH) { 306 EHDwarf2LRegs = Map; 307 EHDwarf2LRegsSize = Size; 308 } else { 309 Dwarf2LRegs = Map; 310 Dwarf2LRegsSize = Size; 311 } 312 } 313 314 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 315 /// number mapping. By default the SEH register number is just the same 316 /// as the LLVM register number. 317 /// FIXME: TableGen these numbers. Currently this requires target specific 318 /// initialization code. 319 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { 320 L2SEHRegs[LLVMReg] = SEHReg; 321 } 322 323 void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) { 324 L2CVRegs[LLVMReg] = CVReg; 325 } 326 327 /// \brief This method should return the register where the return 328 /// address can be found. 329 unsigned getRARegister() const { 330 return RAReg; 331 } 332 333 /// Return the register which is the program counter. 334 unsigned getProgramCounter() const { 335 return PCReg; 336 } 337 338 const MCRegisterDesc &operator[](unsigned RegNo) const { 339 assert(RegNo < NumRegs && 340 "Attempting to access record for invalid register number!"); 341 return Desc[RegNo]; 342 } 343 344 /// \brief Provide a get method, equivalent to [], but more useful with a 345 /// pointer to this object. 346 const MCRegisterDesc &get(unsigned RegNo) const { 347 return operator[](RegNo); 348 } 349 350 /// \brief Returns the physical register number of sub-register "Index" 351 /// for physical register RegNo. Return zero if the sub-register does not 352 /// exist. 353 unsigned getSubReg(unsigned Reg, unsigned Idx) const; 354 355 /// \brief Return a super-register of the specified register 356 /// Reg so its sub-register of index SubIdx is Reg. 357 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 358 const MCRegisterClass *RC) const; 359 360 /// \brief For a given register pair, return the sub-register index 361 /// if the second register is a sub-register of the first. Return zero 362 /// otherwise. 363 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const; 364 365 /// \brief Get the size of the bit range covered by a sub-register index. 366 /// If the index isn't continuous, return the sum of the sizes of its parts. 367 /// If the index is used to access subregisters of different sizes, return -1. 368 unsigned getSubRegIdxSize(unsigned Idx) const; 369 370 /// \brief Get the offset of the bit range covered by a sub-register index. 371 /// If an Offset doesn't make sense (the index isn't continuous, or is used to 372 /// access sub-registers at different offsets), return -1. 373 unsigned getSubRegIdxOffset(unsigned Idx) const; 374 375 /// \brief Return the human-readable symbolic target-specific name for the 376 /// specified physical register. 377 const char *getName(unsigned RegNo) const { 378 return RegStrings + get(RegNo).Name; 379 } 380 381 /// \brief Return the number of registers this target has (useful for 382 /// sizing arrays holding per register information) 383 unsigned getNumRegs() const { 384 return NumRegs; 385 } 386 387 /// \brief Return the number of sub-register indices 388 /// understood by the target. Index 0 is reserved for the no-op sub-register, 389 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers. 390 unsigned getNumSubRegIndices() const { 391 return NumSubRegIndices; 392 } 393 394 /// \brief Return the number of (native) register units in the 395 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They 396 /// can be accessed through MCRegUnitIterator defined below. 397 unsigned getNumRegUnits() const { 398 return NumRegUnits; 399 } 400 401 /// \brief Map a target register to an equivalent dwarf register 402 /// number. Returns -1 if there is no equivalent value. The second 403 /// parameter allows targets to use different numberings for EH info and 404 /// debugging info. 405 int getDwarfRegNum(unsigned RegNum, bool isEH) const; 406 407 /// \brief Map a dwarf register back to a target register. 408 int getLLVMRegNum(unsigned RegNum, bool isEH) const; 409 410 /// \brief Map a target register to an equivalent SEH register 411 /// number. Returns LLVM register number if there is no equivalent value. 412 int getSEHRegNum(unsigned RegNum) const; 413 414 /// \brief Map a target register to an equivalent CodeView register 415 /// number. 416 int getCodeViewRegNum(unsigned RegNum) const; 417 418 regclass_iterator regclass_begin() const { return Classes; } 419 regclass_iterator regclass_end() const { return Classes+NumClasses; } 420 iterator_range<regclass_iterator> regclasses() const { 421 return make_range(regclass_begin(), regclass_end()); 422 } 423 424 unsigned getNumRegClasses() const { 425 return (unsigned)(regclass_end()-regclass_begin()); 426 } 427 428 /// \brief Returns the register class associated with the enumeration 429 /// value. See class MCOperandInfo. 430 const MCRegisterClass& getRegClass(unsigned i) const { 431 assert(i < getNumRegClasses() && "Register Class ID out of range"); 432 return Classes[i]; 433 } 434 435 const char *getRegClassName(const MCRegisterClass *Class) const { 436 return RegClassStrings + Class->NameIdx; 437 } 438 439 /// \brief Returns the encoding for RegNo 440 uint16_t getEncodingValue(unsigned RegNo) const { 441 assert(RegNo < NumRegs && 442 "Attempting to get encoding for invalid register number!"); 443 return RegEncodingTable[RegNo]; 444 } 445 446 /// \brief Returns true if RegB is a sub-register of RegA. 447 bool isSubRegister(unsigned RegA, unsigned RegB) const { 448 return isSuperRegister(RegB, RegA); 449 } 450 451 /// \brief Returns true if RegB is a super-register of RegA. 452 bool isSuperRegister(unsigned RegA, unsigned RegB) const; 453 454 /// \brief Returns true if RegB is a sub-register of RegA or if RegB == RegA. 455 bool isSubRegisterEq(unsigned RegA, unsigned RegB) const { 456 return isSuperRegisterEq(RegB, RegA); 457 } 458 459 /// \brief Returns true if RegB is a super-register of RegA or if 460 /// RegB == RegA. 461 bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const { 462 return RegA == RegB || isSuperRegister(RegA, RegB); 463 } 464 465 /// \brief Returns true if RegB is a super-register or sub-register of RegA 466 /// or if RegB == RegA. 467 bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const { 468 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); 469 } 470 }; 471 472 //===----------------------------------------------------------------------===// 473 // Register List Iterators 474 //===----------------------------------------------------------------------===// 475 476 // MCRegisterInfo provides lists of super-registers, sub-registers, and 477 // aliasing registers. Use these iterator classes to traverse the lists. 478 479 /// MCSubRegIterator enumerates all sub-registers of Reg. 480 /// If IncludeSelf is set, Reg itself is included in the list. 481 class MCSubRegIterator : public MCRegisterInfo::DiffListIterator { 482 public: 483 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, 484 bool IncludeSelf = false) { 485 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs); 486 // Initially, the iterator points to Reg itself. 487 if (!IncludeSelf) 488 ++*this; 489 } 490 }; 491 492 /// Iterator that enumerates the sub-registers of a Reg and the associated 493 /// sub-register indices. 494 class MCSubRegIndexIterator { 495 MCSubRegIterator SRIter; 496 const uint16_t *SRIndex; 497 498 public: 499 /// Constructs an iterator that traverses subregisters and their 500 /// associated subregister indices. 501 MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI) 502 : SRIter(Reg, MCRI) { 503 SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; 504 } 505 506 /// Returns current sub-register. 507 unsigned getSubReg() const { 508 return *SRIter; 509 } 510 511 /// Returns sub-register index of the current sub-register. 512 unsigned getSubRegIndex() const { 513 return *SRIndex; 514 } 515 516 /// Returns true if this iterator is not yet at the end. 517 bool isValid() const { return SRIter.isValid(); } 518 519 /// Moves to the next position. 520 void operator++() { 521 ++SRIter; 522 ++SRIndex; 523 } 524 }; 525 526 /// MCSuperRegIterator enumerates all super-registers of Reg. 527 /// If IncludeSelf is set, Reg itself is included in the list. 528 class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator { 529 public: 530 MCSuperRegIterator() = default; 531 532 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, 533 bool IncludeSelf = false) { 534 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs); 535 // Initially, the iterator points to Reg itself. 536 if (!IncludeSelf) 537 ++*this; 538 } 539 }; 540 541 // Definition for isSuperRegister. Put it down here since it needs the 542 // iterator defined above in addition to the MCRegisterInfo class itself. 543 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{ 544 for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I) 545 if (*I == RegB) 546 return true; 547 return false; 548 } 549 550 //===----------------------------------------------------------------------===// 551 // Register Units 552 //===----------------------------------------------------------------------===// 553 554 // Register units are used to compute register aliasing. Every register has at 555 // least one register unit, but it can have more. Two registers overlap if and 556 // only if they have a common register unit. 557 // 558 // A target with a complicated sub-register structure will typically have many 559 // fewer register units than actual registers. MCRI::getNumRegUnits() returns 560 // the number of register units in the target. 561 562 // MCRegUnitIterator enumerates a list of register units for Reg. The list is 563 // in ascending numerical order. 564 class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator { 565 public: 566 /// MCRegUnitIterator - Create an iterator that traverses the register units 567 /// in Reg. 568 MCRegUnitIterator() = default; 569 570 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) { 571 assert(Reg && "Null register has no regunits"); 572 // Decode the RegUnits MCRegisterDesc field. 573 unsigned RU = MCRI->get(Reg).RegUnits; 574 unsigned Scale = RU & 15; 575 unsigned Offset = RU >> 4; 576 577 // Initialize the iterator to Reg * Scale, and the List pointer to 578 // DiffLists + Offset. 579 init(Reg * Scale, MCRI->DiffLists + Offset); 580 581 // That may not be a valid unit, we need to advance by one to get the real 582 // unit number. The first differential can be 0 which would normally 583 // terminate the list, but since we know every register has at least one 584 // unit, we can allow a 0 differential here. 585 advance(); 586 } 587 }; 588 589 /// MCRegUnitMaskIterator enumerates a list of register units and their 590 /// associated lane masks for Reg. The register units are in ascending 591 /// numerical order. 592 class MCRegUnitMaskIterator { 593 MCRegUnitIterator RUIter; 594 const LaneBitmask *MaskListIter; 595 596 public: 597 MCRegUnitMaskIterator() = default; 598 599 /// Constructs an iterator that traverses the register units and their 600 /// associated LaneMasks in Reg. 601 MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI) 602 : RUIter(Reg, MCRI) { 603 uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks; 604 MaskListIter = &MCRI->RegUnitMaskSequences[Idx]; 605 } 606 607 /// Returns a (RegUnit, LaneMask) pair. 608 std::pair<unsigned,LaneBitmask> operator*() const { 609 return std::make_pair(*RUIter, *MaskListIter); 610 } 611 612 /// Returns true if this iterator is not yet at the end. 613 bool isValid() const { return RUIter.isValid(); } 614 615 /// Moves to the next position. 616 void operator++() { 617 ++MaskListIter; 618 ++RUIter; 619 } 620 }; 621 622 // Each register unit has one or two root registers. The complete set of 623 // registers containing a register unit is the union of the roots and their 624 // super-registers. All registers aliasing Unit can be visited like this: 625 // 626 // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) { 627 // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI) 628 // visit(*SI); 629 // } 630 631 /// MCRegUnitRootIterator enumerates the root registers of a register unit. 632 class MCRegUnitRootIterator { 633 uint16_t Reg0 = 0; 634 uint16_t Reg1 = 0; 635 636 public: 637 MCRegUnitRootIterator() = default; 638 639 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { 640 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); 641 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; 642 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; 643 } 644 645 /// \brief Dereference to get the current root register. 646 unsigned operator*() const { 647 return Reg0; 648 } 649 650 /// \brief Check if the iterator is at the end of the list. 651 bool isValid() const { 652 return Reg0; 653 } 654 655 /// \brief Preincrement to move to the next root register. 656 void operator++() { 657 assert(isValid() && "Cannot move off the end of the list."); 658 Reg0 = Reg1; 659 Reg1 = 0; 660 } 661 }; 662 663 /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is 664 /// set, Reg itself is included in the list. This iterator does not guarantee 665 /// any ordering or that entries are unique. 666 class MCRegAliasIterator { 667 private: 668 unsigned Reg; 669 const MCRegisterInfo *MCRI; 670 bool IncludeSelf; 671 672 MCRegUnitIterator RI; 673 MCRegUnitRootIterator RRI; 674 MCSuperRegIterator SI; 675 676 public: 677 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, 678 bool IncludeSelf) 679 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) { 680 // Initialize the iterators. 681 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) { 682 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) { 683 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) { 684 if (!(!IncludeSelf && Reg == *SI)) 685 return; 686 } 687 } 688 } 689 } 690 691 bool isValid() const { return RI.isValid(); } 692 693 unsigned operator*() const { 694 assert(SI.isValid() && "Cannot dereference an invalid iterator."); 695 return *SI; 696 } 697 698 void advance() { 699 // Assuming SI is valid. 700 ++SI; 701 if (SI.isValid()) return; 702 703 ++RRI; 704 if (RRI.isValid()) { 705 SI = MCSuperRegIterator(*RRI, MCRI, true); 706 return; 707 } 708 709 ++RI; 710 if (RI.isValid()) { 711 RRI = MCRegUnitRootIterator(*RI, MCRI); 712 SI = MCSuperRegIterator(*RRI, MCRI, true); 713 } 714 } 715 716 void operator++() { 717 assert(isValid() && "Cannot move off the end of the list."); 718 do advance(); 719 while (!IncludeSelf && isValid() && *SI == Reg); 720 } 721 }; 722 723 } // end namespace llvm 724 725 #endif // LLVM_MC_MCREGISTERINFO_H 726