1 # Check for illegal conditional Neon instructions in ARM mode. The instructions 2 # which overlap with VFP are the tricky cases, so test those. 3 .include "itblock.s" 4 .syntax unified 5 .arch armv7-a 6 .fpu neon 7 .text 8 func: 9 itblock 4 eq 10 vmoveq q0,q1 11 vmoveq d0,d1 12 vmoveq.i32 q0,#0 13 vmoveq.i32 d0,#0 14 @ Following four *can* be conditional. 15 itblock 4 eq 16 vmoveq.32 d0[1], r2 17 vmoveq d0,r1,r2 18 vmoveq.32 r2,d1[0] 19 vmoveq r0,r1,d2 20 21 .macro dyadic_eq op eq="eq" f32=".f32" 22 itblock 2 eq 23 \op\eq\f32 d0,d1,d2 24 \op\eq\f32 q0,q1,q2 25 .endm 26 27 dyadic_eq vmul 28 dyadic_eq vmla 29 dyadic_eq vmls 30 dyadic_eq vadd 31 dyadic_eq vsub 32 33 .macro monadic_eq op eq="eq" f32=".f32" 34 itblock 2 eq 35 \op\eq\f32 d0,d1 36 \op\eq\f32 q0,q1 37 .endm 38 39 monadic_eq vabs 40 monadic_eq vneg 41 42 .macro cvt to from dot="." 43 itblock 2 eq 44 vcvteq\dot\to\dot\from d0,d1 45 vcvteq\dot\to\dot\from q0,q1 46 .endm 47 48 cvt s32 f32 49 cvt u32 f32 50 cvt f32 s32 51 cvt f32 u32 52 53 itblock 4 eq 54 vdupeq.32 d0,r1 55 vdupeq.32 q0,r1 56 vdupeq.32 d0,d1[0] 57 vdupeq.32 q0,d1[1] 58
