1 #objdump: -dr 2 #as: -mfix-24k -32 3 #source: 24k-triple-stores-1.s 4 #name: 24K: Triple Store (Opcode Check) 5 6 .*: +file format .*mips.* 7 8 Disassembly of section .text: 9 0+ <.*>: 10 0: a3a20000 sb v0,0\(sp\) 11 4: a3a30008 sb v1,8\(sp\) 12 8: 00000000 nop 13 c: a3a40010 sb a0,16\(sp\) 14 10: a3a50018 sb a1,24\(sp\) 15 14: 00000000 nop 16 18: a3a60020 sb a2,32\(sp\) 17 1c: a7a20000 sh v0,0\(sp\) 18 20: a7a30008 sh v1,8\(sp\) 19 24: 00000000 nop 20 28: a7a40010 sh a0,16\(sp\) 21 2c: a7a50018 sh a1,24\(sp\) 22 30: 00000000 nop 23 34: a7a60020 sh a2,32\(sp\) 24 38: afa20000 sw v0,0\(sp\) 25 3c: afa30008 sw v1,8\(sp\) 26 40: 00000000 nop 27 44: afa40010 sw a0,16\(sp\) 28 48: afa50018 sw a1,24\(sp\) 29 4c: 00000000 nop 30 50: afa60020 sw a2,32\(sp\) 31 54: 7fa20026 sc v0,0\(sp\) 32 58: 00000000 nop 33 5c: 7fa30426 sc v1,8\(sp\) 34 60: 7fa40826 sc a0,16\(sp\) 35 64: 00000000 nop 36 68: 7fa50c26 sc a1,24\(sp\) 37 6c: 7fa61026 sc a2,32\(sp\) 38 70: 00000000 nop 39 74: e7a20000 swc1 \$f2,0\(sp\) 40 78: e7a30008 swc1 \$f3,8\(sp\) 41 7c: 00000000 nop 42 80: e7a40010 swc1 \$f4,16\(sp\) 43 84: e7a50018 swc1 \$f5,24\(sp\) 44 88: 00000000 nop 45 8c: e7a60020 swc1 \$f6,32\(sp\) 46 90: 4962e800 swc2 \$2,0\(sp\) 47 94: 00000000 nop 48 98: 4963e808 swc2 \$3,8\(sp\) 49 9c: 4964e810 swc2 \$4,16\(sp\) 50 a0: 00000000 nop 51 a4: 4965e818 swc2 \$5,24\(sp\) 52 a8: 4966e820 swc2 \$6,32\(sp\) 53 ac: 00000000 nop 54 b0: f7a20000 sdc1 \$f2,0\(sp\) 55 b4: f7a30008 sdc1 \$f3,8\(sp\) 56 b8: 00000000 nop 57 bc: f7a40010 sdc1 \$f4,16\(sp\) 58 c0: f7a50018 sdc1 \$f5,24\(sp\) 59 c4: 00000000 nop 60 c8: f7a60020 sdc1 \$f6,32\(sp\) 61 cc: 49e2e800 sdc2 \$2,0\(sp\) 62 d0: 00000000 nop 63 d4: 49e3e808 sdc2 \$3,8\(sp\) 64 d8: 49e4e810 sdc2 \$4,16\(sp\) 65 dc: 00000000 nop 66 e0: 49e5e818 sdc2 \$5,24\(sp\) 67 e4: 49e6e820 sdc2 \$6,32\(sp\) 68 ... 69
