1 2 /*++ 3 4 Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved 5 6 This program and the accompanying materials are licensed and made available under 7 the terms and conditions of the BSD License that accompanies this distribution. 8 The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php. 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 15 16 Module Name: 17 18 VlvCommonDefinitions.h 19 20 Abstract: 21 22 Macros to simplify and abstract the interface to PCI configuration. 23 24 --*/ 25 26 /// 27 /// PCI CONFIGURATION MAP REGISTER OFFSETS 28 /// 29 #ifndef PCI_VID 30 #define PCI_VID 0x0000 ///< Vendor ID Register 31 #define PCI_DID 0x0002 ///< Device ID Register 32 #define PCI_CMD 0x0004 ///< PCI Command Register 33 #define PCI_STS 0x0006 ///< PCI Status Register 34 #define PCI_RID 0x0008 ///< Revision ID Register 35 #define PCI_IFT 0x0009 ///< Interface Type 36 #define PCI_SCC 0x000A ///< Sub Class Code Register 37 #define PCI_BCC 0x000B ///< Base Class Code Register 38 #define PCI_CLS 0x000C ///< Cache Line Size 39 #define PCI_PMLT 0x000D ///< Primary Master Latency Timer 40 #define PCI_HDR 0x000E ///< Header Type Register 41 #define PCI_BIST 0x000F ///< Built in Self Test Register 42 #define PCI_BAR0 0x0010 ///< Base Address Register 0 43 #define PCI_BAR1 0x0014 ///< Base Address Register 1 44 #define PCI_BAR2 0x0018 ///< Base Address Register 2 45 #define PCI_PBUS 0x0018 ///< Primary Bus Number Register 46 #define PCI_SBUS 0x0019 ///< Secondary Bus Number Register 47 #define PCI_SUBUS 0x001A ///< Subordinate Bus Number Register 48 #define PCI_SMLT 0x001B ///< Secondary Master Latency Timer 49 #define PCI_BAR3 0x001C ///< Base Address Register 3 50 #define PCI_IOBASE 0x001C ///< I/O base Register 51 #define PCI_IOLIMIT 0x001D ///< I/O Limit Register 52 #define PCI_SECSTATUS 0x001E ///< Secondary Status Register 53 #define PCI_BAR4 0x0020 ///< Base Address Register 4 54 #define PCI_MEMBASE 0x0020 ///< Memory Base Register 55 #define PCI_MEMLIMIT 0x0022 ///< Memory Limit Register 56 #define PCI_BAR5 0x0024 ///< Base Address Register 5 57 #define PCI_PRE_MEMBASE 0x0024 ///< Prefetchable memory Base register 58 #define PCI_PRE_MEMLIMIT 0x0026 ///< Prefetchable memory Limit register 59 #define PCI_PRE_MEMBASE_U 0x0028 ///< Prefetchable memory base upper 32 bits 60 #define PCI_PRE_MEMLIMIT_U 0x002C ///< Prefetchable memory limit upper 32 bits 61 #define PCI_SVID 0x002C ///< Subsystem Vendor ID 62 #define PCI_SID 0x002E ///< Subsystem ID 63 #define PCI_IOBASE_U 0x0030 ///< I/O base Upper Register 64 #define PCI_IOLIMIT_U 0x0032 ///< I/O Limit Upper Register 65 #define PCI_CAPP 0x0034 ///< Capabilities Pointer 66 #define PCI_EROM 0x0038 ///< Expansion ROM Base Address 67 #define PCI_INTLINE 0x003C ///< Interrupt Line Register 68 #define PCI_INTPIN 0x003D ///< Interrupt Pin Register 69 #define PCI_MAXGNT 0x003E ///< Max Grant Register 70 #define PCI_BRIDGE_CNTL 0x003E ///< Bridge Control Register 71 #define PCI_MAXLAT 0x003F ///< Max Latency Register 72 #endif 73 // 74 // Bit Difinitions 75 // 76 #ifndef BIT0 77 #define BIT0 0x0001 78 #define BIT1 0x0002 79 #define BIT2 0x0004 80 #define BIT3 0x0008 81 #define BIT4 0x0010 82 #define BIT5 0x0020 83 #define BIT6 0x0040 84 #define BIT7 0x0080 85 #define BIT8 0x0100 86 #define BIT9 0x0200 87 #define BIT10 0x0400 88 #define BIT11 0x0800 89 #define BIT12 0x1000 90 #define BIT13 0x2000 91 #define BIT14 0x4000 92 #define BIT15 0x8000 93 #define BIT16 0x00010000 94 #define BIT17 0x00020000 95 #define BIT18 0x00040000 96 #define BIT19 0x00080000 97 #define BIT20 0x00100000 98 #define BIT21 0x00200000 99 #define BIT22 0x00400000 100 #define BIT23 0x00800000 101 #define BIT24 0x01000000 102 #define BIT25 0x02000000 103 #define BIT26 0x04000000 104 #define BIT27 0x08000000 105 #define BIT28 0x10000000 106 #define BIT29 0x20000000 107 #define BIT30 0x40000000 108 #define BIT31 0x80000000 109 #endif 110 111 #ifndef _PCIACCESS_H_INCLUDED_ 112 #define _PCIACCESS_H_INCLUDED_ 113 #ifndef PCI_EXPRESS_BASE_ADDRESS 114 #define PCI_EXPRESS_BASE_ADDRESS 0xE0000000 115 #endif 116 117 #ifndef MmPciAddress 118 #define MmPciAddress( Segment, Bus, Device, Function, Register ) \ 119 ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \ 120 (UINTN)(Bus << 20) + \ 121 (UINTN)(Device << 15) + \ 122 (UINTN)(Function << 12) + \ 123 (UINTN)(Register) \ 124 ) 125 #endif 126 127 // 128 // UINT64 129 // 130 #define MmPci64Ptr( Segment, Bus, Device, Function, Register ) \ 131 ( (volatile UINT64 *)MmPciAddress( Segment, Bus, Device, Function, Register ) ) 132 133 #define MmPci64( Segment, Bus, Device, Function, Register ) \ 134 *MmPci64Ptr( Segment, Bus, Device, Function, Register ) 135 136 #define MmPci64Or( Segment, Bus, Device, Function, Register, OrData ) \ 137 MmPci64( Segment, Bus, Device, Function, Register ) = \ 138 (UINT64) ( \ 139 MmPci64( Segment, Bus, Device, Function, Register ) | \ 140 (UINT64)(OrData) \ 141 ) 142 143 #define MmPci64And( Segment, Bus, Device, Function, Register, AndData ) \ 144 MmPci64( Segment, Bus, Device, Function, Register ) = \ 145 (UINT64) ( \ 146 MmPci64( Segment, Bus, Device, Function, Register ) & \ 147 (UINT64)(AndData) \ 148 ) 149 150 #define MmPci64AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \ 151 MmPci64( Segment, Bus, Device, Function, Register ) = \ 152 (UINT64) ( \ 153 ( MmPci64( Segment, Bus, Device, Function, Register ) & \ 154 (UINT64)(AndData) \ 155 ) | \ 156 (UINT64)(OrData) \ 157 ) 158 159 // 160 // UINT32 161 // 162 163 #define MmPci32Ptr( Segment, Bus, Device, Function, Register ) \ 164 ( (volatile UINT32 *) MmPciAddress( Segment, Bus, Device, Function, Register ) ) 165 166 #define MmPci32( Segment, Bus, Device, Function, Register ) \ 167 *MmPci32Ptr( Segment, Bus, Device, Function, Register ) 168 169 #define MmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \ 170 MmPci32( Segment, Bus, Device, Function, Register ) = \ 171 (UINT32) ( \ 172 MmPci32( Segment, Bus, Device, Function, Register ) | \ 173 (UINT32)(OrData) \ 174 ) 175 176 #define MmPci32And( Segment, Bus, Device, Function, Register, AndData ) \ 177 MmPci32( Segment, Bus, Device, Function, Register ) = \ 178 (UINT32) ( \ 179 MmPci32( Segment, Bus, Device, Function, Register ) & \ 180 (UINT32)(AndData) \ 181 ) 182 183 #define MmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \ 184 MmPci32( Segment, Bus, Device, Function, Register ) = \ 185 (UINT32) ( \ 186 ( MmPci32( Segment, Bus, Device, Function, Register ) & \ 187 (UINT32)(AndData) \ 188 ) | \ 189 (UINT32)(OrData) \ 190 ) 191 192 // 193 // UINT16 194 // 195 196 #define MmPci16Ptr( Segment, Bus, Device, Function, Register ) \ 197 ( (volatile UINT16 *)MmPciAddress( Segment, Bus, Device, Function, Register ) ) 198 199 #define MmPci16( Segment, Bus, Device, Function, Register ) \ 200 *MmPci16Ptr( Segment, Bus, Device, Function, Register ) 201 202 #define MmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \ 203 MmPci16( Segment, Bus, Device, Function, Register ) = \ 204 (UINT16) ( \ 205 MmPci16( Segment, Bus, Device, Function, Register ) | \ 206 (UINT16)(OrData) \ 207 ) 208 209 #define MmPci16And( Segment, Bus, Device, Function, Register, AndData ) \ 210 MmPci16( Segment, Bus, Device, Function, Register ) = \ 211 (UINT16) ( \ 212 MmPci16( Segment, Bus, Device, Function, Register ) & \ 213 (UINT16)(AndData) \ 214 ) 215 216 #define MmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \ 217 MmPci16( Segment, Bus, Device, Function, Register ) = \ 218 (UINT16) ( \ 219 ( MmPci16( Segment, Bus, Device, Function, Register ) & \ 220 (UINT16)(AndData) \ 221 ) | \ 222 (UINT16)(OrData) \ 223 ) 224 225 // 226 // UINT8 227 // 228 229 #define MmPci8Ptr( Segment, Bus, Device, Function, Register ) \ 230 ( (volatile UINT8 *)MmPciAddress( Segment, Bus, Device, Function, Register ) ) 231 232 #define MmPci8( Segment, Bus, Device, Function, Register ) \ 233 *MmPci8Ptr( Segment, Bus, Device, Function, Register ) 234 235 #define MmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \ 236 MmPci8( Segment, Bus, Device, Function, Register ) = \ 237 (UINT8) ( \ 238 MmPci8( Segment, Bus, Device, Function, Register ) | \ 239 (UINT8)(OrData) \ 240 ) 241 242 #define MmPci8And( Segment, Bus, Device, Function, Register, AndData ) \ 243 MmPci8( Segment, Bus, Device, Function, Register ) = \ 244 (UINT8) ( \ 245 MmPci8( Segment, Bus, Device, Function, Register ) & \ 246 (UINT8)(AndData) \ 247 ) 248 249 #define MmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \ 250 MmPci8( Segment, Bus, Device, Function, Register ) = \ 251 (UINT8) ( \ 252 ( MmPci8( Segment, Bus, Device, Function, Register ) & \ 253 (UINT8)(AndData) \ 254 ) | \ 255 (UINT8)(OrData) \ 256 ) 257 258 #endif 259
