1 //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Implementation of the MachineRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/CodeGen/MachineRegisterInfo.h" 15 #include "llvm/ADT/iterator_range.h" 16 #include "llvm/CodeGen/LowLevelType.h" 17 #include "llvm/CodeGen/MachineBasicBlock.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineInstr.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineOperand.h" 22 #include "llvm/CodeGen/TargetInstrInfo.h" 23 #include "llvm/CodeGen/TargetRegisterInfo.h" 24 #include "llvm/CodeGen/TargetSubtargetInfo.h" 25 #include "llvm/Config/llvm-config.h" 26 #include "llvm/IR/Attributes.h" 27 #include "llvm/IR/DebugLoc.h" 28 #include "llvm/IR/Function.h" 29 #include "llvm/MC/MCRegisterInfo.h" 30 #include "llvm/Support/Casting.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/Compiler.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/raw_ostream.h" 35 #include <cassert> 36 37 using namespace llvm; 38 39 static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, 40 cl::init(true), cl::desc("Enable subregister liveness tracking.")); 41 42 // Pin the vtable to this file. 43 void MachineRegisterInfo::Delegate::anchor() {} 44 45 MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF) 46 : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() && 47 EnableSubRegLiveness), 48 IsUpdatedCSRsInitialized(false) { 49 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs(); 50 VRegInfo.reserve(256); 51 RegAllocHints.reserve(256); 52 UsedPhysRegMask.resize(NumRegs); 53 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]()); 54 } 55 56 /// setRegClass - Set the register class of the specified virtual register. 57 /// 58 void 59 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 60 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); 61 VRegInfo[Reg].first = RC; 62 } 63 64 void MachineRegisterInfo::setRegBank(unsigned Reg, 65 const RegisterBank &RegBank) { 66 VRegInfo[Reg].first = &RegBank; 67 } 68 69 static const TargetRegisterClass * 70 constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, 71 const TargetRegisterClass *OldRC, 72 const TargetRegisterClass *RC, unsigned MinNumRegs) { 73 if (OldRC == RC) 74 return RC; 75 const TargetRegisterClass *NewRC = 76 MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC); 77 if (!NewRC || NewRC == OldRC) 78 return NewRC; 79 if (NewRC->getNumRegs() < MinNumRegs) 80 return nullptr; 81 MRI.setRegClass(Reg, NewRC); 82 return NewRC; 83 } 84 85 const TargetRegisterClass * 86 MachineRegisterInfo::constrainRegClass(unsigned Reg, 87 const TargetRegisterClass *RC, 88 unsigned MinNumRegs) { 89 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); 90 } 91 92 bool 93 MachineRegisterInfo::constrainRegAttrs(unsigned Reg, 94 unsigned ConstrainingReg, 95 unsigned MinNumRegs) { 96 auto const *OldRC = getRegClassOrNull(Reg); 97 auto const *RC = getRegClassOrNull(ConstrainingReg); 98 // A virtual register at any point must have either a low-level type 99 // or a class assigned, but not both. The only exception is the internals of 100 // GlobalISel's instruction selection pass, which is allowed to temporarily 101 // introduce registers with types and classes both. 102 assert((OldRC || getType(Reg).isValid()) && "Reg has neither class nor type"); 103 assert((!OldRC || !getType(Reg).isValid()) && "Reg has class and type both"); 104 assert((RC || getType(ConstrainingReg).isValid()) && 105 "ConstrainingReg has neither class nor type"); 106 assert((!RC || !getType(ConstrainingReg).isValid()) && 107 "ConstrainingReg has class and type both"); 108 if (OldRC && RC) 109 return ::constrainRegClass(*this, Reg, OldRC, RC, MinNumRegs); 110 // If one of the virtual registers is generic (used in generic machine 111 // instructions, has a low-level type, doesn't have a class), and the other is 112 // concrete (used in target specific instructions, doesn't have a low-level 113 // type, has a class), we can not unify them. 114 if (OldRC || RC) 115 return false; 116 // At this point, both registers are guaranteed to have a valid low-level 117 // type, and they must agree. 118 if (getType(Reg) != getType(ConstrainingReg)) 119 return false; 120 auto const *OldRB = getRegBankOrNull(Reg); 121 auto const *RB = getRegBankOrNull(ConstrainingReg); 122 if (OldRB) 123 return !RB || RB == OldRB; 124 if (RB) 125 setRegBank(Reg, *RB); 126 return true; 127 } 128 129 bool 130 MachineRegisterInfo::recomputeRegClass(unsigned Reg) { 131 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); 132 const TargetRegisterClass *OldRC = getRegClass(Reg); 133 const TargetRegisterClass *NewRC = 134 getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF); 135 136 // Stop early if there is no room to grow. 137 if (NewRC == OldRC) 138 return false; 139 140 // Accumulate constraints from all uses. 141 for (MachineOperand &MO : reg_nodbg_operands(Reg)) { 142 // Apply the effect of the given operand to NewRC. 143 MachineInstr *MI = MO.getParent(); 144 unsigned OpNo = &MO - &MI->getOperand(0); 145 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, 146 getTargetRegisterInfo()); 147 if (!NewRC || NewRC == OldRC) 148 return false; 149 } 150 setRegClass(Reg, NewRC); 151 return true; 152 } 153 154 unsigned MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) { 155 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 156 VRegInfo.grow(Reg); 157 RegAllocHints.grow(Reg); 158 insertVRegByName(Name, Reg); 159 return Reg; 160 } 161 162 /// createVirtualRegister - Create and return a new virtual register in the 163 /// function with the specified register class. 164 /// 165 unsigned 166 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, 167 StringRef Name) { 168 assert(RegClass && "Cannot create register without RegClass!"); 169 assert(RegClass->isAllocatable() && 170 "Virtual register RegClass must be allocatable."); 171 172 // New virtual register number. 173 unsigned Reg = createIncompleteVirtualRegister(Name); 174 VRegInfo[Reg].first = RegClass; 175 if (TheDelegate) 176 TheDelegate->MRI_NoteNewVirtualRegister(Reg); 177 return Reg; 178 } 179 180 void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) { 181 // Check that VReg doesn't have a class. 182 assert((getRegClassOrRegBank(VReg).isNull() || 183 !getRegClassOrRegBank(VReg).is<const TargetRegisterClass *>()) && 184 "Can't set the size of a non-generic virtual register"); 185 VRegToType.grow(VReg); 186 VRegToType[VReg] = Ty; 187 } 188 189 unsigned 190 MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) { 191 // New virtual register number. 192 unsigned Reg = createIncompleteVirtualRegister(Name); 193 // FIXME: Should we use a dummy register class? 194 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr); 195 setType(Reg, Ty); 196 if (TheDelegate) 197 TheDelegate->MRI_NoteNewVirtualRegister(Reg); 198 return Reg; 199 } 200 201 void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); } 202 203 /// clearVirtRegs - Remove all virtual registers (after physreg assignment). 204 void MachineRegisterInfo::clearVirtRegs() { 205 #ifndef NDEBUG 206 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { 207 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 208 if (!VRegInfo[Reg].second) 209 continue; 210 verifyUseList(Reg); 211 llvm_unreachable("Remaining virtual register operands"); 212 } 213 #endif 214 VRegInfo.clear(); 215 for (auto &I : LiveIns) 216 I.second = 0; 217 } 218 219 void MachineRegisterInfo::verifyUseList(unsigned Reg) const { 220 #ifndef NDEBUG 221 bool Valid = true; 222 for (MachineOperand &M : reg_operands(Reg)) { 223 MachineOperand *MO = &M; 224 MachineInstr *MI = MO->getParent(); 225 if (!MI) { 226 errs() << printReg(Reg, getTargetRegisterInfo()) 227 << " use list MachineOperand " << MO 228 << " has no parent instruction.\n"; 229 Valid = false; 230 continue; 231 } 232 MachineOperand *MO0 = &MI->getOperand(0); 233 unsigned NumOps = MI->getNumOperands(); 234 if (!(MO >= MO0 && MO < MO0+NumOps)) { 235 errs() << printReg(Reg, getTargetRegisterInfo()) 236 << " use list MachineOperand " << MO 237 << " doesn't belong to parent MI: " << *MI; 238 Valid = false; 239 } 240 if (!MO->isReg()) { 241 errs() << printReg(Reg, getTargetRegisterInfo()) 242 << " MachineOperand " << MO << ": " << *MO 243 << " is not a register\n"; 244 Valid = false; 245 } 246 if (MO->getReg() != Reg) { 247 errs() << printReg(Reg, getTargetRegisterInfo()) 248 << " use-list MachineOperand " << MO << ": " 249 << *MO << " is the wrong register\n"; 250 Valid = false; 251 } 252 } 253 assert(Valid && "Invalid use list"); 254 #endif 255 } 256 257 void MachineRegisterInfo::verifyUseLists() const { 258 #ifndef NDEBUG 259 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 260 verifyUseList(TargetRegisterInfo::index2VirtReg(i)); 261 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i) 262 verifyUseList(i); 263 #endif 264 } 265 266 /// Add MO to the linked list of operands for its register. 267 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) { 268 assert(!MO->isOnRegUseList() && "Already on list"); 269 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 270 MachineOperand *const Head = HeadRef; 271 272 // Head points to the first list element. 273 // Next is NULL on the last list element. 274 // Prev pointers are circular, so Head->Prev == Last. 275 276 // Head is NULL for an empty list. 277 if (!Head) { 278 MO->Contents.Reg.Prev = MO; 279 MO->Contents.Reg.Next = nullptr; 280 HeadRef = MO; 281 return; 282 } 283 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!"); 284 285 // Insert MO between Last and Head in the circular Prev chain. 286 MachineOperand *Last = Head->Contents.Reg.Prev; 287 assert(Last && "Inconsistent use list"); 288 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!"); 289 Head->Contents.Reg.Prev = MO; 290 MO->Contents.Reg.Prev = Last; 291 292 // Def operands always precede uses. This allows def_iterator to stop early. 293 // Insert def operands at the front, and use operands at the back. 294 if (MO->isDef()) { 295 // Insert def at the front. 296 MO->Contents.Reg.Next = Head; 297 HeadRef = MO; 298 } else { 299 // Insert use at the end. 300 MO->Contents.Reg.Next = nullptr; 301 Last->Contents.Reg.Next = MO; 302 } 303 } 304 305 /// Remove MO from its use-def list. 306 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) { 307 assert(MO->isOnRegUseList() && "Operand not on use list"); 308 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 309 MachineOperand *const Head = HeadRef; 310 assert(Head && "List already empty"); 311 312 // Unlink this from the doubly linked list of operands. 313 MachineOperand *Next = MO->Contents.Reg.Next; 314 MachineOperand *Prev = MO->Contents.Reg.Prev; 315 316 // Prev links are circular, next link is NULL instead of looping back to Head. 317 if (MO == Head) 318 HeadRef = Next; 319 else 320 Prev->Contents.Reg.Next = Next; 321 322 (Next ? Next : Head)->Contents.Reg.Prev = Prev; 323 324 MO->Contents.Reg.Prev = nullptr; 325 MO->Contents.Reg.Next = nullptr; 326 } 327 328 /// Move NumOps operands from Src to Dst, updating use-def lists as needed. 329 /// 330 /// The Dst range is assumed to be uninitialized memory. (Or it may contain 331 /// operands that won't be destroyed, which is OK because the MO destructor is 332 /// trivial anyway). 333 /// 334 /// The Src and Dst ranges may overlap. 335 void MachineRegisterInfo::moveOperands(MachineOperand *Dst, 336 MachineOperand *Src, 337 unsigned NumOps) { 338 assert(Src != Dst && NumOps && "Noop moveOperands"); 339 340 // Copy backwards if Dst is within the Src range. 341 int Stride = 1; 342 if (Dst >= Src && Dst < Src + NumOps) { 343 Stride = -1; 344 Dst += NumOps - 1; 345 Src += NumOps - 1; 346 } 347 348 // Copy one operand at a time. 349 do { 350 new (Dst) MachineOperand(*Src); 351 352 // Dst takes Src's place in the use-def chain. 353 if (Src->isReg()) { 354 MachineOperand *&Head = getRegUseDefListHead(Src->getReg()); 355 MachineOperand *Prev = Src->Contents.Reg.Prev; 356 MachineOperand *Next = Src->Contents.Reg.Next; 357 assert(Head && "List empty, but operand is chained"); 358 assert(Prev && "Operand was not on use-def list"); 359 360 // Prev links are circular, next link is NULL instead of looping back to 361 // Head. 362 if (Src == Head) 363 Head = Dst; 364 else 365 Prev->Contents.Reg.Next = Dst; 366 367 // Update Prev pointer. This also works when Src was pointing to itself 368 // in a 1-element list. In that case Head == Dst. 369 (Next ? Next : Head)->Contents.Reg.Prev = Dst; 370 } 371 372 Dst += Stride; 373 Src += Stride; 374 } while (--NumOps); 375 } 376 377 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 378 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 379 /// except that it also changes any definitions of the register as well. 380 /// If ToReg is a physical register we apply the sub register to obtain the 381 /// final/proper physical register. 382 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 383 assert(FromReg != ToReg && "Cannot replace a reg with itself"); 384 385 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 386 387 // TODO: This could be more efficient by bulk changing the operands. 388 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 389 MachineOperand &O = *I; 390 ++I; 391 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) { 392 O.substPhysReg(ToReg, *TRI); 393 } else { 394 O.setReg(ToReg); 395 } 396 } 397 } 398 399 /// getVRegDef - Return the machine instr that defines the specified virtual 400 /// register or null if none is found. This assumes that the code is in SSA 401 /// form, so there should only be one definition. 402 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 403 // Since we are in SSA form, we can use the first definition. 404 def_instr_iterator I = def_instr_begin(Reg); 405 assert((I.atEnd() || std::next(I) == def_instr_end()) && 406 "getVRegDef assumes a single definition or no definition"); 407 return !I.atEnd() ? &*I : nullptr; 408 } 409 410 /// getUniqueVRegDef - Return the unique machine instr that defines the 411 /// specified virtual register or null if none is found. If there are 412 /// multiple definitions or no definition, return null. 413 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { 414 if (def_empty(Reg)) return nullptr; 415 def_instr_iterator I = def_instr_begin(Reg); 416 if (std::next(I) != def_instr_end()) 417 return nullptr; 418 return &*I; 419 } 420 421 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 422 use_nodbg_iterator UI = use_nodbg_begin(RegNo); 423 if (UI == use_nodbg_end()) 424 return false; 425 return ++UI == use_nodbg_end(); 426 } 427 428 /// clearKillFlags - Iterate over all the uses of the given register and 429 /// clear the kill flag from the MachineOperand. This function is used by 430 /// optimization passes which extend register lifetimes and need only 431 /// preserve conservative kill flag information. 432 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 433 for (MachineOperand &MO : use_operands(Reg)) 434 MO.setIsKill(false); 435 } 436 437 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 438 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 439 if (I->first == Reg || I->second == Reg) 440 return true; 441 return false; 442 } 443 444 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 445 /// corresponding live-in physical register. 446 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 447 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 448 if (I->second == VReg) 449 return I->first; 450 return 0; 451 } 452 453 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 454 /// corresponding live-in physical register. 455 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 456 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 457 if (I->first == PReg) 458 return I->second; 459 return 0; 460 } 461 462 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 463 /// into the given entry block. 464 void 465 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 466 const TargetRegisterInfo &TRI, 467 const TargetInstrInfo &TII) { 468 // Emit the copies into the top of the block. 469 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 470 if (LiveIns[i].second) { 471 if (use_nodbg_empty(LiveIns[i].second)) { 472 // The livein has no non-dbg uses. Drop it. 473 // 474 // It would be preferable to have isel avoid creating live-in 475 // records for unused arguments in the first place, but it's 476 // complicated by the debug info code for arguments. 477 LiveIns.erase(LiveIns.begin() + i); 478 --i; --e; 479 } else { 480 // Emit a copy. 481 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 482 TII.get(TargetOpcode::COPY), LiveIns[i].second) 483 .addReg(LiveIns[i].first); 484 485 // Add the register to the entry block live-in set. 486 EntryMBB->addLiveIn(LiveIns[i].first); 487 } 488 } else { 489 // Add the register to the entry block live-in set. 490 EntryMBB->addLiveIn(LiveIns[i].first); 491 } 492 } 493 494 LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const { 495 // Lane masks are only defined for vregs. 496 assert(TargetRegisterInfo::isVirtualRegister(Reg)); 497 const TargetRegisterClass &TRC = *getRegClass(Reg); 498 return TRC.getLaneMask(); 499 } 500 501 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 502 LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(unsigned Reg) const { 503 for (MachineInstr &I : use_instructions(Reg)) 504 I.dump(); 505 } 506 #endif 507 508 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 509 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF); 510 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() && 511 "Invalid ReservedRegs vector from target"); 512 } 513 514 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const { 515 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 516 517 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 518 if (TRI->isConstantPhysReg(PhysReg)) 519 return true; 520 521 // Check if any overlapping register is modified, or allocatable so it may be 522 // used later. 523 for (MCRegAliasIterator AI(PhysReg, TRI, true); 524 AI.isValid(); ++AI) 525 if (!def_empty(*AI) || isAllocatable(*AI)) 526 return false; 527 return true; 528 } 529 530 bool 531 MachineRegisterInfo::isCallerPreservedOrConstPhysReg(unsigned PhysReg) const { 532 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 533 return isConstantPhysReg(PhysReg) || 534 TRI->isCallerPreservedPhysReg(PhysReg, *MF); 535 } 536 537 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the 538 /// specified register as undefined which causes the DBG_VALUE to be 539 /// deleted during LiveDebugVariables analysis. 540 void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const { 541 // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.) 542 MachineRegisterInfo::use_instr_iterator nextI; 543 for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end(); 544 I != E; I = nextI) { 545 nextI = std::next(I); // I is invalidated by the setReg 546 MachineInstr *UseMI = &*I; 547 if (UseMI->isDebugValue()) 548 UseMI->getOperand(0).setReg(0U); 549 } 550 } 551 552 static const Function *getCalledFunction(const MachineInstr &MI) { 553 for (const MachineOperand &MO : MI.operands()) { 554 if (!MO.isGlobal()) 555 continue; 556 const Function *Func = dyn_cast<Function>(MO.getGlobal()); 557 if (Func != nullptr) 558 return Func; 559 } 560 return nullptr; 561 } 562 563 static bool isNoReturnDef(const MachineOperand &MO) { 564 // Anything which is not a noreturn function is a real def. 565 const MachineInstr &MI = *MO.getParent(); 566 if (!MI.isCall()) 567 return false; 568 const MachineBasicBlock &MBB = *MI.getParent(); 569 if (!MBB.succ_empty()) 570 return false; 571 const MachineFunction &MF = *MBB.getParent(); 572 // We need to keep correct unwind information even if the function will 573 // not return, since the runtime may need it. 574 if (MF.getFunction().hasFnAttribute(Attribute::UWTable)) 575 return false; 576 const Function *Called = getCalledFunction(MI); 577 return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) || 578 !Called->hasFnAttribute(Attribute::NoUnwind)); 579 } 580 581 bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg, 582 bool SkipNoReturnDef) const { 583 if (UsedPhysRegMask.test(PhysReg)) 584 return true; 585 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 586 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) { 587 for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) { 588 if (!SkipNoReturnDef && isNoReturnDef(MO)) 589 continue; 590 return true; 591 } 592 } 593 return false; 594 } 595 596 bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const { 597 if (UsedPhysRegMask.test(PhysReg)) 598 return true; 599 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 600 for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid(); 601 ++AliasReg) { 602 if (!reg_nodbg_empty(*AliasReg)) 603 return true; 604 } 605 return false; 606 } 607 608 void MachineRegisterInfo::disableCalleeSavedRegister(unsigned Reg) { 609 610 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 611 assert(Reg && (Reg < TRI->getNumRegs()) && 612 "Trying to disable an invalid register"); 613 614 if (!IsUpdatedCSRsInitialized) { 615 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); 616 for (const MCPhysReg *I = CSR; *I; ++I) 617 UpdatedCSRs.push_back(*I); 618 619 // Zero value represents the end of the register list 620 // (no more registers should be pushed). 621 UpdatedCSRs.push_back(0); 622 623 IsUpdatedCSRsInitialized = true; 624 } 625 626 // Remove the register (and its aliases from the list). 627 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 628 UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI), 629 UpdatedCSRs.end()); 630 } 631 632 const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const { 633 if (IsUpdatedCSRsInitialized) 634 return UpdatedCSRs.data(); 635 636 return getTargetRegisterInfo()->getCalleeSavedRegs(MF); 637 } 638 639 void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) { 640 if (IsUpdatedCSRsInitialized) 641 UpdatedCSRs.clear(); 642 643 for (MCPhysReg Reg : CSRs) 644 UpdatedCSRs.push_back(Reg); 645 646 // Zero value represents the end of the register list 647 // (no more registers should be pushed). 648 UpdatedCSRs.push_back(0); 649 IsUpdatedCSRsInitialized = true; 650 } 651 652 bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const { 653 const TargetRegisterInfo *TRI = getTargetRegisterInfo(); 654 for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) { 655 bool IsRootReserved = true; 656 for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true); 657 Super.isValid(); ++Super) { 658 unsigned Reg = *Super; 659 if (!isReserved(Reg)) { 660 IsRootReserved = false; 661 break; 662 } 663 } 664 if (IsRootReserved) 665 return true; 666 } 667 return false; 668 } 669