1 /* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keithw (at) vmware.com> 30 */ 31 32 33 #ifndef BRWCONTEXT_INC 34 #define BRWCONTEXT_INC 35 36 #include <stdbool.h> 37 #include "main/macros.h" 38 #include "main/mtypes.h" 39 #include "brw_structs.h" 40 #include "brw_pipe_control.h" 41 #include "compiler/brw_compiler.h" 42 43 #include "isl/isl.h" 44 #include "blorp/blorp.h" 45 46 #include <brw_bufmgr.h> 47 48 #include "common/gen_debug.h" 49 #include "intel_screen.h" 50 #include "intel_tex_obj.h" 51 52 #ifdef __cplusplus 53 extern "C" { 54 #endif 55 /* Glossary: 56 * 57 * URB - uniform resource buffer. A mid-sized buffer which is 58 * partitioned between the fixed function units and used for passing 59 * values (vertices, primitives, constants) between them. 60 * 61 * CURBE - constant URB entry. An urb region (entry) used to hold 62 * constant values which the fixed function units can be instructed to 63 * preload into the GRF when spawning a thread. 64 * 65 * VUE - vertex URB entry. An urb entry holding a vertex and usually 66 * a vertex header. The header contains control information and 67 * things like primitive type, Begin/end flags and clip codes. 68 * 69 * PUE - primitive URB entry. An urb entry produced by the setup (SF) 70 * unit holding rasterization and interpolation parameters. 71 * 72 * GRF - general register file. One of several register files 73 * addressable by programmed threads. The inputs (r0, payload, curbe, 74 * urb) of the thread are preloaded to this area before the thread is 75 * spawned. The registers are individually 8 dwords wide and suitable 76 * for general usage. Registers holding thread input values are not 77 * special and may be overwritten. 78 * 79 * MRF - message register file. Threads communicate (and terminate) 80 * by sending messages. Message parameters are placed in contiguous 81 * MRF registers. All program output is via these messages. URB 82 * entries are populated by sending a message to the shared URB 83 * function containing the new data, together with a control word, 84 * often an unmodified copy of R0. 85 * 86 * R0 - GRF register 0. Typically holds control information used when 87 * sending messages to other threads. 88 * 89 * EU or GEN4 EU: The name of the programmable subsystem of the 90 * i965 hardware. Threads are executed by the EU, the registers 91 * described above are part of the EU architecture. 92 * 93 * Fixed function units: 94 * 95 * CS - Command streamer. Notional first unit, little software 96 * interaction. Holds the URB entries used for constant data, ie the 97 * CURBEs. 98 * 99 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of 100 * this unit is responsible for pulling vertices out of vertex buffers 101 * in vram and injecting them into the processing pipe as VUEs. If 102 * enabled, it first passes them to a VS thread which is a good place 103 * for the driver to implement any active vertex shader. 104 * 105 * HS - Hull Shader (Tessellation Control Shader) 106 * 107 * TE - Tessellation Engine (Tessellation Primitive Generation) 108 * 109 * DS - Domain Shader (Tessellation Evaluation Shader) 110 * 111 * GS - Geometry Shader. This corresponds to a new DX10 concept. If 112 * enabled, incoming strips etc are passed to GS threads in individual 113 * line/triangle/point units. The GS thread may perform arbitary 114 * computation and emit whatever primtives with whatever vertices it 115 * chooses. This makes GS an excellent place to implement GL's 116 * unfilled polygon modes, though of course it is capable of much 117 * more. Additionally, GS is used to translate away primitives not 118 * handled by latter units, including Quads and Lineloops. 119 * 120 * CS - Clipper. Mesa's clipping algorithms are imported to run on 121 * this unit. The fixed function part performs cliptesting against 122 * the 6 fixed clipplanes and makes descisions on whether or not the 123 * incoming primitive needs to be passed to a thread for clipping. 124 * User clip planes are handled via cooperation with the VS thread. 125 * 126 * SF - Strips Fans or Setup: Triangles are prepared for 127 * rasterization. Interpolation coefficients are calculated. 128 * Flatshading and two-side lighting usually performed here. 129 * 130 * WM - Windower. Interpolation of vertex attributes performed here. 131 * Fragment shader implemented here. SIMD aspects of EU taken full 132 * advantage of, as pixels are processed in blocks of 16. 133 * 134 * CC - Color Calculator. No EU threads associated with this unit. 135 * Handles blending and (presumably) depth and stencil testing. 136 */ 137 138 struct brw_context; 139 struct brw_inst; 140 struct brw_vs_prog_key; 141 struct brw_vue_prog_key; 142 struct brw_wm_prog_key; 143 struct brw_wm_prog_data; 144 struct brw_cs_prog_key; 145 struct brw_cs_prog_data; 146 147 enum brw_pipeline { 148 BRW_RENDER_PIPELINE, 149 BRW_COMPUTE_PIPELINE, 150 151 BRW_NUM_PIPELINES 152 }; 153 154 enum brw_cache_id { 155 BRW_CACHE_FS_PROG, 156 BRW_CACHE_BLORP_PROG, 157 BRW_CACHE_SF_PROG, 158 BRW_CACHE_VS_PROG, 159 BRW_CACHE_FF_GS_PROG, 160 BRW_CACHE_GS_PROG, 161 BRW_CACHE_TCS_PROG, 162 BRW_CACHE_TES_PROG, 163 BRW_CACHE_CLIP_PROG, 164 BRW_CACHE_CS_PROG, 165 166 BRW_MAX_CACHE 167 }; 168 169 enum brw_state_id { 170 /* brw_cache_ids must come first - see brw_program_cache.c */ 171 BRW_STATE_URB_FENCE = BRW_MAX_CACHE, 172 BRW_STATE_FRAGMENT_PROGRAM, 173 BRW_STATE_GEOMETRY_PROGRAM, 174 BRW_STATE_TESS_PROGRAMS, 175 BRW_STATE_VERTEX_PROGRAM, 176 BRW_STATE_REDUCED_PRIMITIVE, 177 BRW_STATE_PATCH_PRIMITIVE, 178 BRW_STATE_PRIMITIVE, 179 BRW_STATE_CONTEXT, 180 BRW_STATE_PSP, 181 BRW_STATE_SURFACES, 182 BRW_STATE_BINDING_TABLE_POINTERS, 183 BRW_STATE_INDICES, 184 BRW_STATE_VERTICES, 185 BRW_STATE_DEFAULT_TESS_LEVELS, 186 BRW_STATE_BATCH, 187 BRW_STATE_INDEX_BUFFER, 188 BRW_STATE_VS_CONSTBUF, 189 BRW_STATE_TCS_CONSTBUF, 190 BRW_STATE_TES_CONSTBUF, 191 BRW_STATE_GS_CONSTBUF, 192 BRW_STATE_PROGRAM_CACHE, 193 BRW_STATE_STATE_BASE_ADDRESS, 194 BRW_STATE_VUE_MAP_GEOM_OUT, 195 BRW_STATE_TRANSFORM_FEEDBACK, 196 BRW_STATE_RASTERIZER_DISCARD, 197 BRW_STATE_STATS_WM, 198 BRW_STATE_UNIFORM_BUFFER, 199 BRW_STATE_IMAGE_UNITS, 200 BRW_STATE_META_IN_PROGRESS, 201 BRW_STATE_PUSH_CONSTANT_ALLOCATION, 202 BRW_STATE_NUM_SAMPLES, 203 BRW_STATE_TEXTURE_BUFFER, 204 BRW_STATE_GEN4_UNIT_STATE, 205 BRW_STATE_CC_VP, 206 BRW_STATE_SF_VP, 207 BRW_STATE_CLIP_VP, 208 BRW_STATE_SAMPLER_STATE_TABLE, 209 BRW_STATE_VS_ATTRIB_WORKAROUNDS, 210 BRW_STATE_COMPUTE_PROGRAM, 211 BRW_STATE_CS_WORK_GROUPS, 212 BRW_STATE_URB_SIZE, 213 BRW_STATE_CC_STATE, 214 BRW_STATE_BLORP, 215 BRW_STATE_VIEWPORT_COUNT, 216 BRW_STATE_CONSERVATIVE_RASTERIZATION, 217 BRW_STATE_DRAW_CALL, 218 BRW_STATE_AUX, 219 BRW_NUM_STATE_BITS 220 }; 221 222 /** 223 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct. 224 * 225 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures. 226 * When the currently bound shader program differs from the previous draw 227 * call, these will be flagged. They cover brw->{stage}_program and 228 * ctx->{Stage}Program->_Current. 229 * 230 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a 231 * driver perspective. Even if the same shader is bound at the API level, 232 * we may need to switch between multiple versions of that shader to handle 233 * changes in non-orthagonal state. 234 * 235 * Additionally, multiple shader programs may have identical vertex shaders 236 * (for example), or compile down to the same code in the backend. We combine 237 * those into a single program cache entry. 238 * 239 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which 240 * covers the brw_*_prog_data structures, and brw->*.prog_offset. 241 */ 242 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG) 243 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't 244 * use the normal state upload paths), but the cache is still used. To avoid 245 * polluting the brw_program_cache code with special cases, we retain the 246 * dirty bit for now. It should eventually be removed. 247 */ 248 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG) 249 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG) 250 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG) 251 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG) 252 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG) 253 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG) 254 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG) 255 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG) 256 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG) 257 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE) 258 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM) 259 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM) 260 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS) 261 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM) 262 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE) 263 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE) 264 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE) 265 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT) 266 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP) 267 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES) 268 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS) 269 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES) 270 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES) 271 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS) 272 /** 273 * Used for any batch entry with a relocated pointer that will be used 274 * by any 3D rendering. 275 */ 276 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH) 277 /** \see brw.state.depth_region */ 278 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER) 279 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF) 280 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF) 281 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF) 282 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF) 283 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE) 284 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS) 285 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT) 286 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT) 287 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK) 288 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD) 289 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM) 290 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER) 291 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS) 292 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS) 293 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION) 294 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES) 295 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER) 296 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE) 297 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP) 298 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP) 299 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP) 300 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE) 301 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS) 302 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM) 303 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS) 304 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE) 305 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE) 306 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP) 307 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION) 308 #define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL) 309 #define BRW_NEW_AUX_STATE (1ull << BRW_STATE_AUX) 310 311 struct brw_state_flags { 312 /** State update flags signalled by mesa internals */ 313 GLuint mesa; 314 /** 315 * State update flags signalled as the result of brw_tracked_state updates 316 */ 317 uint64_t brw; 318 }; 319 320 321 /** Subclass of Mesa program */ 322 struct brw_program { 323 struct gl_program program; 324 GLuint id; 325 326 bool compiled_once; 327 }; 328 329 330 struct brw_ff_gs_prog_data { 331 GLuint urb_read_length; 332 GLuint total_grf; 333 334 /** 335 * Gen6 transform feedback: Amount by which the streaming vertex buffer 336 * indices should be incremented each time the GS is invoked. 337 */ 338 unsigned svbi_postincrement_value; 339 }; 340 341 /** Number of texture sampler units */ 342 #define BRW_MAX_TEX_UNIT 32 343 344 /** Max number of UBOs in a shader */ 345 #define BRW_MAX_UBO 14 346 347 /** Max number of SSBOs in a shader */ 348 #define BRW_MAX_SSBO 12 349 350 /** Max number of atomic counter buffer objects in a shader */ 351 #define BRW_MAX_ABO 16 352 353 /** Max number of image uniforms in a shader */ 354 #define BRW_MAX_IMAGES 32 355 356 /** Maximum number of actual buffers used for stream output */ 357 #define BRW_MAX_SOL_BUFFERS 4 358 359 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \ 360 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \ 361 BRW_MAX_UBO + \ 362 BRW_MAX_SSBO + \ 363 BRW_MAX_ABO + \ 364 BRW_MAX_IMAGES + \ 365 2 + /* shader time, pull constants */ \ 366 1 /* cs num work groups */) 367 368 struct brw_cache { 369 struct brw_context *brw; 370 371 struct brw_cache_item **items; 372 struct brw_bo *bo; 373 void *map; 374 GLuint size, n_items; 375 376 uint32_t next_offset; 377 }; 378 379 #define perf_debug(...) do { \ 380 static GLuint msg_id = 0; \ 381 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \ 382 dbg_printf(__VA_ARGS__); \ 383 if (brw->perf_debug) \ 384 _mesa_gl_debug(&brw->ctx, &msg_id, \ 385 MESA_DEBUG_SOURCE_API, \ 386 MESA_DEBUG_TYPE_PERFORMANCE, \ 387 MESA_DEBUG_SEVERITY_MEDIUM, \ 388 __VA_ARGS__); \ 389 } while(0) 390 391 #define WARN_ONCE(cond, fmt...) do { \ 392 if (unlikely(cond)) { \ 393 static bool _warned = false; \ 394 static GLuint msg_id = 0; \ 395 if (!_warned) { \ 396 fprintf(stderr, "WARNING: "); \ 397 fprintf(stderr, fmt); \ 398 _warned = true; \ 399 \ 400 _mesa_gl_debug(ctx, &msg_id, \ 401 MESA_DEBUG_SOURCE_API, \ 402 MESA_DEBUG_TYPE_OTHER, \ 403 MESA_DEBUG_SEVERITY_HIGH, fmt); \ 404 } \ 405 } \ 406 } while (0) 407 408 /* Considered adding a member to this struct to document which flags 409 * an update might raise so that ordering of the state atoms can be 410 * checked or derived at runtime. Dropped the idea in favor of having 411 * a debug mode where the state is monitored for flags which are 412 * raised that have already been tested against. 413 */ 414 struct brw_tracked_state { 415 struct brw_state_flags dirty; 416 void (*emit)( struct brw_context *brw ); 417 }; 418 419 enum shader_time_shader_type { 420 ST_NONE, 421 ST_VS, 422 ST_TCS, 423 ST_TES, 424 ST_GS, 425 ST_FS8, 426 ST_FS16, 427 ST_CS, 428 }; 429 430 struct brw_vertex_buffer { 431 /** Buffer object containing the uploaded vertex data */ 432 struct brw_bo *bo; 433 uint32_t offset; 434 uint32_t size; 435 /** Byte stride between elements in the uploaded array */ 436 GLuint stride; 437 GLuint step_rate; 438 }; 439 struct brw_vertex_element { 440 const struct gl_vertex_array *glarray; 441 442 int buffer; 443 bool is_dual_slot; 444 /** Offset of the first element within the buffer object */ 445 unsigned int offset; 446 }; 447 448 struct brw_query_object { 449 struct gl_query_object Base; 450 451 /** Last query BO associated with this query. */ 452 struct brw_bo *bo; 453 454 /** Last index in bo with query data for this object. */ 455 int last_index; 456 457 /** True if we know the batch has been flushed since we ended the query. */ 458 bool flushed; 459 }; 460 461 enum brw_gpu_ring { 462 UNKNOWN_RING, 463 RENDER_RING, 464 BLT_RING, 465 }; 466 467 struct brw_reloc_list { 468 struct drm_i915_gem_relocation_entry *relocs; 469 int reloc_count; 470 int reloc_array_size; 471 }; 472 473 struct brw_growing_bo { 474 struct brw_bo *bo; 475 uint32_t *map; 476 struct brw_bo *partial_bo; 477 uint32_t *partial_bo_map; 478 unsigned partial_bytes; 479 }; 480 481 struct intel_batchbuffer { 482 /** Current batchbuffer being queued up. */ 483 struct brw_growing_bo batch; 484 /** Current statebuffer being queued up. */ 485 struct brw_growing_bo state; 486 487 /** Last batchbuffer submitted to the hardware. Used for glFinish(). */ 488 struct brw_bo *last_bo; 489 490 #ifdef DEBUG 491 uint16_t emit, total; 492 #endif 493 uint32_t *map_next; 494 uint32_t state_used; 495 496 enum brw_gpu_ring ring; 497 bool use_shadow_copy; 498 bool use_batch_first; 499 bool needs_sol_reset; 500 bool state_base_address_emitted; 501 bool no_wrap; 502 503 struct brw_reloc_list batch_relocs; 504 struct brw_reloc_list state_relocs; 505 unsigned int valid_reloc_flags; 506 507 /** The validation list */ 508 struct drm_i915_gem_exec_object2 *validation_list; 509 struct brw_bo **exec_bos; 510 int exec_count; 511 int exec_array_size; 512 513 /** The amount of aperture space (in bytes) used by all exec_bos */ 514 int aperture_space; 515 516 struct { 517 uint32_t *map_next; 518 int batch_reloc_count; 519 int state_reloc_count; 520 int exec_count; 521 } saved; 522 523 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */ 524 struct hash_table *state_batch_sizes; 525 }; 526 527 #define BRW_MAX_XFB_STREAMS 4 528 529 struct brw_transform_feedback_counter { 530 /** 531 * Index of the first entry of this counter within the primitive count BO. 532 * An entry is considered to be an N-tuple of 64bit values, where N is the 533 * number of vertex streams supported by the platform. 534 */ 535 unsigned bo_start; 536 537 /** 538 * Index one past the last entry of this counter within the primitive 539 * count BO. 540 */ 541 unsigned bo_end; 542 543 /** 544 * Primitive count values accumulated while this counter was active, 545 * excluding any entries buffered between \c bo_start and \c bo_end, which 546 * haven't been accounted for yet. 547 */ 548 uint64_t accum[BRW_MAX_XFB_STREAMS]; 549 }; 550 551 static inline void 552 brw_reset_transform_feedback_counter( 553 struct brw_transform_feedback_counter *counter) 554 { 555 counter->bo_start = counter->bo_end; 556 memset(&counter->accum, 0, sizeof(counter->accum)); 557 } 558 559 struct brw_transform_feedback_object { 560 struct gl_transform_feedback_object base; 561 562 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */ 563 struct brw_bo *offset_bo; 564 565 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */ 566 bool zero_offsets; 567 568 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */ 569 GLenum primitive_mode; 570 571 /** 572 * The maximum number of vertices that we can write without overflowing 573 * any of the buffers currently being used for transform feedback. 574 */ 575 unsigned max_index; 576 577 struct brw_bo *prim_count_bo; 578 579 /** 580 * Count of primitives generated during this transform feedback operation. 581 */ 582 struct brw_transform_feedback_counter counter; 583 584 /** 585 * Count of primitives generated during the previous transform feedback 586 * operation. Used to implement DrawTransformFeedback(). 587 */ 588 struct brw_transform_feedback_counter previous_counter; 589 590 /** 591 * Number of vertices written between last Begin/EndTransformFeedback(). 592 * 593 * Used to implement DrawTransformFeedback(). 594 */ 595 uint64_t vertices_written[BRW_MAX_XFB_STREAMS]; 596 bool vertices_written_valid; 597 }; 598 599 /** 600 * Data shared between each programmable stage in the pipeline (vs, gs, and 601 * wm). 602 */ 603 struct brw_stage_state 604 { 605 gl_shader_stage stage; 606 struct brw_stage_prog_data *prog_data; 607 608 /** 609 * Optional scratch buffer used to store spilled register values and 610 * variably-indexed GRF arrays. 611 * 612 * The contents of this buffer are short-lived so the same memory can be 613 * re-used at will for multiple shader programs (executed by the same fixed 614 * function). However reusing a scratch BO for which shader invocations 615 * are still in flight with a per-thread scratch slot size other than the 616 * original can cause threads with different scratch slot size and FFTID 617 * (which may be executed in parallel depending on the shader stage and 618 * hardware generation) to map to an overlapping region of the scratch 619 * space, which can potentially lead to mutual scratch space corruption. 620 * For that reason if you borrow this scratch buffer you should only be 621 * using the slot size given by the \c per_thread_scratch member below, 622 * unless you're taking additional measures to synchronize thread execution 623 * across slot size changes. 624 */ 625 struct brw_bo *scratch_bo; 626 627 /** 628 * Scratch slot size allocated for each thread in the buffer object given 629 * by \c scratch_bo. 630 */ 631 uint32_t per_thread_scratch; 632 633 /** Offset in the program cache to the program */ 634 uint32_t prog_offset; 635 636 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */ 637 uint32_t state_offset; 638 639 struct brw_bo *push_const_bo; /* NULL if using the batchbuffer */ 640 uint32_t push_const_offset; /* Offset in the push constant BO or batch */ 641 int push_const_size; /* in 256-bit register increments */ 642 643 /* Binding table: pointers to SURFACE_STATE entries. */ 644 uint32_t bind_bo_offset; 645 uint32_t surf_offset[BRW_MAX_SURFACES]; 646 647 /** SAMPLER_STATE count and table offset */ 648 uint32_t sampler_count; 649 uint32_t sampler_offset; 650 651 struct brw_image_param image_param[BRW_MAX_IMAGES]; 652 653 /** Need to re-emit 3DSTATE_CONSTANT_XS? */ 654 bool push_constants_dirty; 655 }; 656 657 enum brw_predicate_state { 658 /* The first two states are used if we can determine whether to draw 659 * without having to look at the values in the query object buffer. This 660 * will happen if there is no conditional render in progress, if the query 661 * object is already completed or if something else has already added 662 * samples to the preliminary result such as via a BLT command. 663 */ 664 BRW_PREDICATE_STATE_RENDER, 665 BRW_PREDICATE_STATE_DONT_RENDER, 666 /* In this case whether to draw or not depends on the result of an 667 * MI_PREDICATE command so the predicate enable bit needs to be checked. 668 */ 669 BRW_PREDICATE_STATE_USE_BIT, 670 /* In this case, either MI_PREDICATE doesn't exist or we lack the 671 * necessary kernel features to use it. Stall for the query result. 672 */ 673 BRW_PREDICATE_STATE_STALL_FOR_QUERY, 674 }; 675 676 struct shader_times; 677 678 struct gen_l3_config; 679 680 enum brw_query_kind { 681 OA_COUNTERS, 682 PIPELINE_STATS 683 }; 684 685 struct brw_perf_query_register_prog { 686 uint32_t reg; 687 uint32_t val; 688 }; 689 690 struct brw_perf_query_info 691 { 692 enum brw_query_kind kind; 693 const char *name; 694 const char *guid; 695 struct brw_perf_query_counter *counters; 696 int n_counters; 697 size_t data_size; 698 699 /* OA specific */ 700 uint64_t oa_metrics_set_id; 701 int oa_format; 702 703 /* For indexing into the accumulator[] ... */ 704 int gpu_time_offset; 705 int gpu_clock_offset; 706 int a_offset; 707 int b_offset; 708 int c_offset; 709 710 /* Register programming for a given query */ 711 struct brw_perf_query_register_prog *flex_regs; 712 uint32_t n_flex_regs; 713 714 struct brw_perf_query_register_prog *mux_regs; 715 uint32_t n_mux_regs; 716 717 struct brw_perf_query_register_prog *b_counter_regs; 718 uint32_t n_b_counter_regs; 719 }; 720 721 /** 722 * brw_context is derived from gl_context. 723 */ 724 struct brw_context 725 { 726 struct gl_context ctx; /**< base class, must be first field */ 727 728 struct 729 { 730 /** 731 * Send the appropriate state packets to configure depth, stencil, and 732 * HiZ buffers (i965+ only) 733 */ 734 void (*emit_depth_stencil_hiz)(struct brw_context *brw, 735 struct intel_mipmap_tree *depth_mt, 736 uint32_t depth_offset, 737 uint32_t depthbuffer_format, 738 uint32_t depth_surface_type, 739 struct intel_mipmap_tree *stencil_mt, 740 bool hiz, bool separate_stencil, 741 uint32_t width, uint32_t height, 742 uint32_t tile_x, uint32_t tile_y); 743 744 /** 745 * Emit an MI_REPORT_PERF_COUNT command packet. 746 * 747 * This asks the GPU to write a report of the current OA counter values 748 * into @bo at the given offset and containing the given @report_id 749 * which we can cross-reference when parsing the report (gen7+ only). 750 */ 751 void (*emit_mi_report_perf_count)(struct brw_context *brw, 752 struct brw_bo *bo, 753 uint32_t offset_in_bytes, 754 uint32_t report_id); 755 } vtbl; 756 757 struct brw_bufmgr *bufmgr; 758 759 uint32_t hw_ctx; 760 761 /** BO for post-sync nonzero writes for gen6 workaround. */ 762 struct brw_bo *workaround_bo; 763 uint8_t pipe_controls_since_last_cs_stall; 764 765 /** 766 * Set of struct brw_bo * that have been rendered to within this batchbuffer 767 * and would need flushing before being used from another cache domain that 768 * isn't coherent with it (i.e. the sampler). 769 */ 770 struct hash_table *render_cache; 771 772 /** 773 * Set of struct brw_bo * that have been used as a depth buffer within this 774 * batchbuffer and would need flushing before being used from another cache 775 * domain that isn't coherent with it (i.e. the sampler). 776 */ 777 struct set *depth_cache; 778 779 /** 780 * Number of resets observed in the system at context creation. 781 * 782 * This is tracked in the context so that we can determine that another 783 * reset has occurred. 784 */ 785 uint32_t reset_count; 786 787 struct intel_batchbuffer batch; 788 789 struct { 790 struct brw_bo *bo; 791 void *map; 792 uint32_t next_offset; 793 } upload; 794 795 /** 796 * Set if rendering has occurred to the drawable's front buffer. 797 * 798 * This is used in the DRI2 case to detect that glFlush should also copy 799 * the contents of the fake front buffer to the real front buffer. 800 */ 801 bool front_buffer_dirty; 802 803 /** Framerate throttling: @{ */ 804 struct brw_bo *throttle_batch[2]; 805 806 /* Limit the number of outstanding SwapBuffers by waiting for an earlier 807 * frame of rendering to complete. This gives a very precise cap to the 808 * latency between input and output such that rendering never gets more 809 * than a frame behind the user. (With the caveat that we technically are 810 * not using the SwapBuffers itself as a barrier but the first batch 811 * submitted afterwards, which may be immediately prior to the next 812 * SwapBuffers.) 813 */ 814 bool need_swap_throttle; 815 816 /** General throttling, not caught by throttling between SwapBuffers */ 817 bool need_flush_throttle; 818 /** @} */ 819 820 GLuint stats_wm; 821 822 /** 823 * drirc options: 824 * @{ 825 */ 826 bool no_rast; 827 bool always_flush_batch; 828 bool always_flush_cache; 829 bool disable_throttling; 830 bool precompile; 831 bool dual_color_blend_by_location; 832 833 driOptionCache optionCache; 834 /** @} */ 835 836 GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */ 837 838 GLenum reduced_primitive; 839 840 /** 841 * Set if we're either a debug context or the INTEL_DEBUG=perf environment 842 * variable is set, this is the flag indicating to do expensive work that 843 * might lead to a perf_debug() call. 844 */ 845 bool perf_debug; 846 847 uint64_t max_gtt_map_object_size; 848 849 bool has_hiz; 850 bool has_separate_stencil; 851 bool has_swizzling; 852 853 /** Derived stencil states. */ 854 bool stencil_enabled; 855 bool stencil_two_sided; 856 bool stencil_write_enabled; 857 /** Derived polygon state. */ 858 bool polygon_front_bit; /**< 0=GL_CCW, 1=GL_CW */ 859 860 struct isl_device isl_dev; 861 862 struct blorp_context blorp; 863 864 GLuint NewGLState; 865 struct { 866 struct brw_state_flags pipelines[BRW_NUM_PIPELINES]; 867 } state; 868 869 enum brw_pipeline last_pipeline; 870 871 struct brw_cache cache; 872 873 /* Whether a meta-operation is in progress. */ 874 bool meta_in_progress; 875 876 /* Whether the last depth/stencil packets were both NULL. */ 877 bool no_depth_or_stencil; 878 879 /* The last PMA stall bits programmed. */ 880 uint32_t pma_stall_bits; 881 882 struct { 883 struct { 884 /** The value of gl_BaseVertex for the current _mesa_prim. */ 885 int gl_basevertex; 886 887 /** The value of gl_BaseInstance for the current _mesa_prim. */ 888 int gl_baseinstance; 889 } params; 890 891 /** 892 * Buffer and offset used for GL_ARB_shader_draw_parameters 893 * (for now, only gl_BaseVertex). 894 */ 895 struct brw_bo *draw_params_bo; 896 uint32_t draw_params_offset; 897 898 /** 899 * The value of gl_DrawID for the current _mesa_prim. This always comes 900 * in from it's own vertex buffer since it's not part of the indirect 901 * draw parameters. 902 */ 903 int gl_drawid; 904 struct brw_bo *draw_id_bo; 905 uint32_t draw_id_offset; 906 907 /** 908 * Pointer to the the buffer storing the indirect draw parameters. It 909 * currently only stores the number of requested draw calls but more 910 * parameters could potentially be added. 911 */ 912 struct brw_bo *draw_params_count_bo; 913 uint32_t draw_params_count_offset; 914 } draw; 915 916 struct { 917 /** 918 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is 919 * an indirect call, and num_work_groups_offset is valid. Otherwise, 920 * num_work_groups is set based on glDispatchCompute. 921 */ 922 struct brw_bo *num_work_groups_bo; 923 GLintptr num_work_groups_offset; 924 const GLuint *num_work_groups; 925 } compute; 926 927 struct { 928 struct brw_vertex_element inputs[VERT_ATTRIB_MAX]; 929 struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX]; 930 931 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX]; 932 GLuint nr_enabled; 933 GLuint nr_buffers; 934 935 /* Summary of size and varying of active arrays, so we can check 936 * for changes to this state: 937 */ 938 bool index_bounds_valid; 939 unsigned int min_index, max_index; 940 941 /* Offset from start of vertex buffer so we can avoid redefining 942 * the same VB packed over and over again. 943 */ 944 unsigned int start_vertex_bias; 945 946 /** 947 * Certain vertex attribute formats aren't natively handled by the 948 * hardware and require special VS code to fix up their values. 949 * 950 * These bitfields indicate which workarounds are needed. 951 */ 952 uint8_t attrib_wa_flags[VERT_ATTRIB_MAX]; 953 } vb; 954 955 struct { 956 /** 957 * Index buffer for this draw_prims call. 958 * 959 * Updates are signaled by BRW_NEW_INDICES. 960 */ 961 const struct _mesa_index_buffer *ib; 962 963 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */ 964 struct brw_bo *bo; 965 uint32_t size; 966 unsigned index_size; 967 968 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can 969 * avoid re-uploading the IB packet over and over if we're actually 970 * referencing the same index buffer. 971 */ 972 unsigned int start_vertex_offset; 973 } ib; 974 975 /* Active vertex program: 976 */ 977 struct gl_program *programs[MESA_SHADER_STAGES]; 978 979 /** 980 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so 981 * that we don't have to reemit that state every time we change FBOs. 982 */ 983 unsigned int num_samples; 984 985 /* BRW_NEW_URB_ALLOCATIONS: 986 */ 987 struct { 988 GLuint vsize; /* vertex size plus header in urb registers */ 989 GLuint gsize; /* GS output size in urb registers */ 990 GLuint hsize; /* Tessellation control output size in urb registers */ 991 GLuint dsize; /* Tessellation evaluation output size in urb registers */ 992 GLuint csize; /* constant buffer size in urb registers */ 993 GLuint sfsize; /* setup data size in urb registers */ 994 995 bool constrained; 996 997 GLuint nr_vs_entries; 998 GLuint nr_hs_entries; 999 GLuint nr_ds_entries; 1000 GLuint nr_gs_entries; 1001 GLuint nr_clip_entries; 1002 GLuint nr_sf_entries; 1003 GLuint nr_cs_entries; 1004 1005 GLuint vs_start; 1006 GLuint hs_start; 1007 GLuint ds_start; 1008 GLuint gs_start; 1009 GLuint clip_start; 1010 GLuint sf_start; 1011 GLuint cs_start; 1012 /** 1013 * URB size in the current configuration. The units this is expressed 1014 * in are somewhat inconsistent, see gen_device_info::urb::size. 1015 * 1016 * FINISHME: Represent the URB size consistently in KB on all platforms. 1017 */ 1018 GLuint size; 1019 1020 /* True if the most recently sent _3DSTATE_URB message allocated 1021 * URB space for the GS. 1022 */ 1023 bool gs_present; 1024 1025 /* True if the most recently sent _3DSTATE_URB message allocated 1026 * URB space for the HS and DS. 1027 */ 1028 bool tess_present; 1029 } urb; 1030 1031 1032 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */ 1033 struct { 1034 GLuint wm_start; /**< pos of first wm const in CURBE buffer */ 1035 GLuint wm_size; /**< number of float[4] consts, multiple of 16 */ 1036 GLuint clip_start; 1037 GLuint clip_size; 1038 GLuint vs_start; 1039 GLuint vs_size; 1040 GLuint total_size; 1041 1042 /** 1043 * Pointer to the (intel_upload.c-generated) BO containing the uniforms 1044 * for upload to the CURBE. 1045 */ 1046 struct brw_bo *curbe_bo; 1047 /** Offset within curbe_bo of space for current curbe entry */ 1048 GLuint curbe_offset; 1049 } curbe; 1050 1051 /** 1052 * Layout of vertex data exiting the geometry portion of the pipleine. 1053 * This comes from the last enabled shader stage (GS, DS, or VS). 1054 * 1055 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes. 1056 */ 1057 struct brw_vue_map vue_map_geom_out; 1058 1059 struct { 1060 struct brw_stage_state base; 1061 } vs; 1062 1063 struct { 1064 struct brw_stage_state base; 1065 } tcs; 1066 1067 struct { 1068 struct brw_stage_state base; 1069 } tes; 1070 1071 struct { 1072 struct brw_stage_state base; 1073 1074 /** 1075 * True if the 3DSTATE_GS command most recently emitted to the 3D 1076 * pipeline enabled the GS; false otherwise. 1077 */ 1078 bool enabled; 1079 } gs; 1080 1081 struct { 1082 struct brw_ff_gs_prog_data *prog_data; 1083 1084 bool prog_active; 1085 /** Offset in the program cache to the CLIP program pre-gen6 */ 1086 uint32_t prog_offset; 1087 uint32_t state_offset; 1088 1089 uint32_t bind_bo_offset; 1090 /** 1091 * Surface offsets for the binding table. We only need surfaces to 1092 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we 1093 * need in this case. 1094 */ 1095 uint32_t surf_offset[BRW_MAX_SOL_BINDINGS]; 1096 } ff_gs; 1097 1098 struct { 1099 struct brw_clip_prog_data *prog_data; 1100 1101 /** Offset in the program cache to the CLIP program pre-gen6 */ 1102 uint32_t prog_offset; 1103 1104 /* Offset in the batch to the CLIP state on pre-gen6. */ 1105 uint32_t state_offset; 1106 1107 /* As of gen6, this is the offset in the batch to the CLIP VP, 1108 * instead of vp_bo. 1109 */ 1110 uint32_t vp_offset; 1111 1112 /** 1113 * The number of viewports to use. If gl_ViewportIndex is written, 1114 * we can have up to ctx->Const.MaxViewports viewports. If not, 1115 * the viewport index is always 0, so we can only emit one. 1116 */ 1117 uint8_t viewport_count; 1118 } clip; 1119 1120 1121 struct { 1122 struct brw_sf_prog_data *prog_data; 1123 1124 /** Offset in the program cache to the CLIP program pre-gen6 */ 1125 uint32_t prog_offset; 1126 uint32_t state_offset; 1127 uint32_t vp_offset; 1128 } sf; 1129 1130 struct { 1131 struct brw_stage_state base; 1132 1133 /** 1134 * Buffer object used in place of multisampled null render targets on 1135 * Gen6. See brw_emit_null_surface_state(). 1136 */ 1137 struct brw_bo *multisampled_null_render_target_bo; 1138 1139 float offset_clamp; 1140 } wm; 1141 1142 struct { 1143 struct brw_stage_state base; 1144 } cs; 1145 1146 struct { 1147 uint32_t state_offset; 1148 uint32_t blend_state_offset; 1149 uint32_t depth_stencil_state_offset; 1150 uint32_t vp_offset; 1151 } cc; 1152 1153 struct { 1154 struct brw_query_object *obj; 1155 bool begin_emitted; 1156 } query; 1157 1158 struct { 1159 enum brw_predicate_state state; 1160 bool supported; 1161 } predicate; 1162 1163 struct { 1164 /* Variables referenced in the XML meta data for OA performance 1165 * counters, e.g in the normalization equations. 1166 * 1167 * All uint64_t for consistent operand types in generated code 1168 */ 1169 struct { 1170 uint64_t timestamp_frequency; /** $GpuTimestampFrequency */ 1171 uint64_t n_eus; /** $EuCoresTotalCount */ 1172 uint64_t n_eu_slices; /** $EuSlicesTotalCount */ 1173 uint64_t n_eu_sub_slices; /** $EuSubslicesTotalCount */ 1174 uint64_t eu_threads_count; /** $EuThreadsCount */ 1175 uint64_t slice_mask; /** $SliceMask */ 1176 uint64_t subslice_mask; /** $SubsliceMask */ 1177 uint64_t gt_min_freq; /** $GpuMinFrequency */ 1178 uint64_t gt_max_freq; /** $GpuMaxFrequency */ 1179 uint64_t revision; /** $SkuRevisionId */ 1180 } sys_vars; 1181 1182 /* OA metric sets, indexed by GUID, as know by Mesa at build time, 1183 * to cross-reference with the GUIDs of configs advertised by the 1184 * kernel at runtime 1185 */ 1186 struct hash_table *oa_metrics_table; 1187 1188 struct brw_perf_query_info *queries; 1189 int n_queries; 1190 1191 /* The i915 perf stream we open to setup + enable the OA counters */ 1192 int oa_stream_fd; 1193 1194 /* An i915 perf stream fd gives exclusive access to the OA unit that will 1195 * report counter snapshots for a specific counter set/profile in a 1196 * specific layout/format so we can only start OA queries that are 1197 * compatible with the currently open fd... 1198 */ 1199 int current_oa_metrics_set_id; 1200 int current_oa_format; 1201 1202 /* List of buffers containing OA reports */ 1203 struct exec_list sample_buffers; 1204 1205 /* Cached list of empty sample buffers */ 1206 struct exec_list free_sample_buffers; 1207 1208 int n_active_oa_queries; 1209 int n_active_pipeline_stats_queries; 1210 1211 /* The number of queries depending on running OA counters which 1212 * extends beyond brw_end_perf_query() since we need to wait until 1213 * the last MI_RPC command has parsed by the GPU. 1214 * 1215 * Accurate accounting is important here as emitting an 1216 * MI_REPORT_PERF_COUNT command while the OA unit is disabled will 1217 * effectively hang the gpu. 1218 */ 1219 int n_oa_users; 1220 1221 /* To help catch an spurious problem with the hardware or perf 1222 * forwarding samples, we emit each MI_REPORT_PERF_COUNT command 1223 * with a unique ID that we can explicitly check for... 1224 */ 1225 int next_query_start_report_id; 1226 1227 /** 1228 * An array of queries whose results haven't yet been assembled 1229 * based on the data in buffer objects. 1230 * 1231 * These may be active, or have already ended. However, the 1232 * results have not been requested. 1233 */ 1234 struct brw_perf_query_object **unaccumulated; 1235 int unaccumulated_elements; 1236 int unaccumulated_array_size; 1237 1238 /* The total number of query objects so we can relinquish 1239 * our exclusive access to perf if the application deletes 1240 * all of its objects. (NB: We only disable perf while 1241 * there are no active queries) 1242 */ 1243 int n_query_instances; 1244 } perfquery; 1245 1246 int num_atoms[BRW_NUM_PIPELINES]; 1247 const struct brw_tracked_state render_atoms[76]; 1248 const struct brw_tracked_state compute_atoms[11]; 1249 1250 const enum isl_format *mesa_to_isl_render_format; 1251 const bool *mesa_format_supports_render; 1252 1253 /* PrimitiveRestart */ 1254 struct { 1255 bool in_progress; 1256 bool enable_cut_index; 1257 } prim_restart; 1258 1259 /** Computed depth/stencil/hiz state from the current attached 1260 * renderbuffers, valid only during the drawing state upload loop after 1261 * brw_workaround_depthstencil_alignment(). 1262 */ 1263 struct { 1264 /* Inter-tile (page-aligned) byte offsets. */ 1265 uint32_t depth_offset; 1266 /* Intra-tile x,y offsets for drawing to combined depth-stencil. Only 1267 * used for Gen < 6. 1268 */ 1269 uint32_t tile_x, tile_y; 1270 } depthstencil; 1271 1272 uint32_t num_instances; 1273 int basevertex; 1274 int baseinstance; 1275 1276 struct { 1277 const struct gen_l3_config *config; 1278 } l3; 1279 1280 struct { 1281 struct brw_bo *bo; 1282 const char **names; 1283 int *ids; 1284 enum shader_time_shader_type *types; 1285 struct shader_times *cumulative; 1286 int num_entries; 1287 int max_entries; 1288 double report_time; 1289 } shader_time; 1290 1291 struct brw_fast_clear_state *fast_clear_state; 1292 1293 /* Array of aux usages to use for drawing. Aux usage for render targets is 1294 * a bit more complex than simply calling a single function so we need some 1295 * way of passing it form brw_draw.c to surface state setup. 1296 */ 1297 enum isl_aux_usage draw_aux_usage[MAX_DRAW_BUFFERS]; 1298 1299 __DRIcontext *driContext; 1300 struct intel_screen *screen; 1301 }; 1302 1303 /* brw_clear.c */ 1304 extern void intelInitClearFuncs(struct dd_function_table *functions); 1305 1306 /*====================================================================== 1307 * brw_context.c 1308 */ 1309 extern const char *const brw_vendor_string; 1310 1311 extern const char * 1312 brw_get_renderer_string(const struct intel_screen *screen); 1313 1314 enum { 1315 DRI_CONF_BO_REUSE_DISABLED, 1316 DRI_CONF_BO_REUSE_ALL 1317 }; 1318 1319 void intel_update_renderbuffers(__DRIcontext *context, 1320 __DRIdrawable *drawable); 1321 void intel_prepare_render(struct brw_context *brw); 1322 1323 void brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering, 1324 bool *draw_aux_buffer_disabled); 1325 1326 void intel_resolve_for_dri2_flush(struct brw_context *brw, 1327 __DRIdrawable *drawable); 1328 1329 GLboolean brwCreateContext(gl_api api, 1330 const struct gl_config *mesaVis, 1331 __DRIcontext *driContextPriv, 1332 const struct __DriverContextConfig *ctx_config, 1333 unsigned *error, 1334 void *sharedContextPrivate); 1335 1336 /*====================================================================== 1337 * brw_misc_state.c 1338 */ 1339 void 1340 brw_meta_resolve_color(struct brw_context *brw, 1341 struct intel_mipmap_tree *mt); 1342 1343 /*====================================================================== 1344 * brw_misc_state.c 1345 */ 1346 void brw_workaround_depthstencil_alignment(struct brw_context *brw, 1347 GLbitfield clear_mask); 1348 1349 /* brw_object_purgeable.c */ 1350 void brw_init_object_purgeable_functions(struct dd_function_table *functions); 1351 1352 /*====================================================================== 1353 * brw_queryobj.c 1354 */ 1355 void brw_init_common_queryobj_functions(struct dd_function_table *functions); 1356 void gen4_init_queryobj_functions(struct dd_function_table *functions); 1357 void brw_emit_query_begin(struct brw_context *brw); 1358 void brw_emit_query_end(struct brw_context *brw); 1359 void brw_query_counter(struct gl_context *ctx, struct gl_query_object *q); 1360 bool brw_is_query_pipelined(struct brw_query_object *query); 1361 uint64_t brw_timebase_scale(struct brw_context *brw, uint64_t gpu_timestamp); 1362 uint64_t brw_raw_timestamp_delta(struct brw_context *brw, 1363 uint64_t time0, uint64_t time1); 1364 1365 /** gen6_queryobj.c */ 1366 void gen6_init_queryobj_functions(struct dd_function_table *functions); 1367 void brw_write_timestamp(struct brw_context *brw, struct brw_bo *bo, int idx); 1368 void brw_write_depth_count(struct brw_context *brw, struct brw_bo *bo, int idx); 1369 1370 /** hsw_queryobj.c */ 1371 void hsw_overflow_result_to_gpr0(struct brw_context *brw, 1372 struct brw_query_object *query, 1373 int count); 1374 void hsw_init_queryobj_functions(struct dd_function_table *functions); 1375 1376 /** brw_conditional_render.c */ 1377 void brw_init_conditional_render_functions(struct dd_function_table *functions); 1378 bool brw_check_conditional_render(struct brw_context *brw); 1379 1380 /** intel_batchbuffer.c */ 1381 void brw_load_register_mem(struct brw_context *brw, 1382 uint32_t reg, 1383 struct brw_bo *bo, 1384 uint32_t offset); 1385 void brw_load_register_mem64(struct brw_context *brw, 1386 uint32_t reg, 1387 struct brw_bo *bo, 1388 uint32_t offset); 1389 void brw_store_register_mem32(struct brw_context *brw, 1390 struct brw_bo *bo, uint32_t reg, uint32_t offset); 1391 void brw_store_register_mem64(struct brw_context *brw, 1392 struct brw_bo *bo, uint32_t reg, uint32_t offset); 1393 void brw_load_register_imm32(struct brw_context *brw, 1394 uint32_t reg, uint32_t imm); 1395 void brw_load_register_imm64(struct brw_context *brw, 1396 uint32_t reg, uint64_t imm); 1397 void brw_load_register_reg(struct brw_context *brw, uint32_t src, 1398 uint32_t dest); 1399 void brw_load_register_reg64(struct brw_context *brw, uint32_t src, 1400 uint32_t dest); 1401 void brw_store_data_imm32(struct brw_context *brw, struct brw_bo *bo, 1402 uint32_t offset, uint32_t imm); 1403 void brw_store_data_imm64(struct brw_context *brw, struct brw_bo *bo, 1404 uint32_t offset, uint64_t imm); 1405 1406 /*====================================================================== 1407 * intel_tex_validate.c 1408 */ 1409 void brw_validate_textures( struct brw_context *brw ); 1410 1411 1412 /*====================================================================== 1413 * brw_program.c 1414 */ 1415 static inline bool 1416 key_debug(struct brw_context *brw, const char *name, int a, int b) 1417 { 1418 if (a != b) { 1419 perf_debug(" %s %d->%d\n", name, a, b); 1420 return true; 1421 } 1422 return false; 1423 } 1424 1425 void brwInitFragProgFuncs( struct dd_function_table *functions ); 1426 1427 void brw_get_scratch_bo(struct brw_context *brw, 1428 struct brw_bo **scratch_bo, int size); 1429 void brw_alloc_stage_scratch(struct brw_context *brw, 1430 struct brw_stage_state *stage_state, 1431 unsigned per_thread_size); 1432 void brw_init_shader_time(struct brw_context *brw); 1433 int brw_get_shader_time_index(struct brw_context *brw, 1434 struct gl_program *prog, 1435 enum shader_time_shader_type type, 1436 bool is_glsl_sh); 1437 void brw_collect_and_report_shader_time(struct brw_context *brw); 1438 void brw_destroy_shader_time(struct brw_context *brw); 1439 1440 /* brw_urb.c 1441 */ 1442 void brw_calculate_urb_fence(struct brw_context *brw, unsigned csize, 1443 unsigned vsize, unsigned sfsize); 1444 void brw_upload_urb_fence(struct brw_context *brw); 1445 1446 /* brw_curbe.c 1447 */ 1448 void brw_upload_cs_urb_state(struct brw_context *brw); 1449 1450 /* brw_vs.c */ 1451 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx); 1452 1453 /* brw_draw_upload.c */ 1454 unsigned brw_get_vertex_surface_type(struct brw_context *brw, 1455 const struct gl_vertex_array *glarray); 1456 1457 static inline unsigned 1458 brw_get_index_type(unsigned index_size) 1459 { 1460 /* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint, 1461 * respectively. 1462 */ 1463 return index_size >> 1; 1464 } 1465 1466 void brw_prepare_vertices(struct brw_context *brw); 1467 1468 /* brw_wm_surface_state.c */ 1469 void brw_update_buffer_texture_surface(struct gl_context *ctx, 1470 unsigned unit, 1471 uint32_t *surf_offset); 1472 void 1473 brw_update_sol_surface(struct brw_context *brw, 1474 struct gl_buffer_object *buffer_obj, 1475 uint32_t *out_offset, unsigned num_vector_components, 1476 unsigned stride_dwords, unsigned offset_dwords); 1477 void brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_program *prog, 1478 struct brw_stage_state *stage_state, 1479 struct brw_stage_prog_data *prog_data); 1480 void brw_upload_image_surfaces(struct brw_context *brw, 1481 const struct gl_program *prog, 1482 struct brw_stage_state *stage_state, 1483 struct brw_stage_prog_data *prog_data); 1484 1485 /* brw_surface_formats.c */ 1486 void intel_screen_init_surface_formats(struct intel_screen *screen); 1487 void brw_init_surface_formats(struct brw_context *brw); 1488 bool brw_render_target_supported(struct brw_context *brw, 1489 struct gl_renderbuffer *rb); 1490 uint32_t brw_depth_format(struct brw_context *brw, mesa_format format); 1491 1492 /* brw_performance_query.c */ 1493 void brw_init_performance_queries(struct brw_context *brw); 1494 1495 /* intel_extensions.c */ 1496 extern void intelInitExtensions(struct gl_context *ctx); 1497 1498 /* intel_state.c */ 1499 extern int intel_translate_shadow_compare_func(GLenum func); 1500 extern int intel_translate_compare_func(GLenum func); 1501 extern int intel_translate_stencil_op(GLenum op); 1502 extern int intel_translate_logic_op(GLenum opcode); 1503 1504 /* brw_sync.c */ 1505 void brw_init_syncobj_functions(struct dd_function_table *functions); 1506 1507 /* gen6_sol.c */ 1508 struct gl_transform_feedback_object * 1509 brw_new_transform_feedback(struct gl_context *ctx, GLuint name); 1510 void 1511 brw_delete_transform_feedback(struct gl_context *ctx, 1512 struct gl_transform_feedback_object *obj); 1513 void 1514 brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode, 1515 struct gl_transform_feedback_object *obj); 1516 void 1517 brw_end_transform_feedback(struct gl_context *ctx, 1518 struct gl_transform_feedback_object *obj); 1519 void 1520 brw_pause_transform_feedback(struct gl_context *ctx, 1521 struct gl_transform_feedback_object *obj); 1522 void 1523 brw_resume_transform_feedback(struct gl_context *ctx, 1524 struct gl_transform_feedback_object *obj); 1525 void 1526 brw_save_primitives_written_counters(struct brw_context *brw, 1527 struct brw_transform_feedback_object *obj); 1528 GLsizei 1529 brw_get_transform_feedback_vertex_count(struct gl_context *ctx, 1530 struct gl_transform_feedback_object *obj, 1531 GLuint stream); 1532 1533 /* gen7_sol_state.c */ 1534 void 1535 gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode, 1536 struct gl_transform_feedback_object *obj); 1537 void 1538 gen7_end_transform_feedback(struct gl_context *ctx, 1539 struct gl_transform_feedback_object *obj); 1540 void 1541 gen7_pause_transform_feedback(struct gl_context *ctx, 1542 struct gl_transform_feedback_object *obj); 1543 void 1544 gen7_resume_transform_feedback(struct gl_context *ctx, 1545 struct gl_transform_feedback_object *obj); 1546 1547 /* hsw_sol.c */ 1548 void 1549 hsw_begin_transform_feedback(struct gl_context *ctx, GLenum mode, 1550 struct gl_transform_feedback_object *obj); 1551 void 1552 hsw_end_transform_feedback(struct gl_context *ctx, 1553 struct gl_transform_feedback_object *obj); 1554 void 1555 hsw_pause_transform_feedback(struct gl_context *ctx, 1556 struct gl_transform_feedback_object *obj); 1557 void 1558 hsw_resume_transform_feedback(struct gl_context *ctx, 1559 struct gl_transform_feedback_object *obj); 1560 1561 /* brw_blorp_blit.cpp */ 1562 GLbitfield 1563 brw_blorp_framebuffer(struct brw_context *brw, 1564 struct gl_framebuffer *readFb, 1565 struct gl_framebuffer *drawFb, 1566 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, 1567 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, 1568 GLbitfield mask, GLenum filter); 1569 1570 bool 1571 brw_blorp_copytexsubimage(struct brw_context *brw, 1572 struct gl_renderbuffer *src_rb, 1573 struct gl_texture_image *dst_image, 1574 int slice, 1575 int srcX0, int srcY0, 1576 int dstX0, int dstY0, 1577 int width, int height); 1578 1579 void 1580 gen6_get_sample_position(struct gl_context *ctx, 1581 struct gl_framebuffer *fb, 1582 GLuint index, 1583 GLfloat *result); 1584 void 1585 gen6_set_sample_maps(struct gl_context *ctx); 1586 1587 /* gen8_multisample_state.c */ 1588 void gen8_emit_3dstate_sample_pattern(struct brw_context *brw); 1589 1590 /* gen7_urb.c */ 1591 void 1592 gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size, 1593 unsigned hs_size, unsigned ds_size, 1594 unsigned gs_size, unsigned fs_size); 1595 1596 void 1597 gen6_upload_urb(struct brw_context *brw, unsigned vs_size, 1598 bool gs_present, unsigned gs_size); 1599 void 1600 gen7_upload_urb(struct brw_context *brw, unsigned vs_size, 1601 bool gs_present, bool tess_present); 1602 1603 /* brw_reset.c */ 1604 extern GLenum 1605 brw_get_graphics_reset_status(struct gl_context *ctx); 1606 void 1607 brw_check_for_reset(struct brw_context *brw); 1608 1609 /* brw_compute.c */ 1610 extern void 1611 brw_init_compute_functions(struct dd_function_table *functions); 1612 1613 /* brw_program_binary.c */ 1614 extern void 1615 brw_program_binary_init(unsigned device_id); 1616 extern void 1617 brw_get_program_binary_driver_sha1(struct gl_context *ctx, uint8_t *sha1); 1618 extern void 1619 brw_deserialize_program_binary(struct gl_context *ctx, 1620 struct gl_shader_program *shProg, 1621 struct gl_program *prog); 1622 void 1623 brw_program_serialize_nir(struct gl_context *ctx, struct gl_program *prog); 1624 void 1625 brw_program_deserialize_nir(struct gl_context *ctx, struct gl_program *prog, 1626 gl_shader_stage stage); 1627 1628 /*====================================================================== 1629 * Inline conversion functions. These are better-typed than the 1630 * macros used previously: 1631 */ 1632 static inline struct brw_context * 1633 brw_context( struct gl_context *ctx ) 1634 { 1635 return (struct brw_context *)ctx; 1636 } 1637 1638 static inline struct brw_program * 1639 brw_program(struct gl_program *p) 1640 { 1641 return (struct brw_program *) p; 1642 } 1643 1644 static inline const struct brw_program * 1645 brw_program_const(const struct gl_program *p) 1646 { 1647 return (const struct brw_program *) p; 1648 } 1649 1650 static inline bool 1651 brw_depth_writes_enabled(const struct brw_context *brw) 1652 { 1653 const struct gl_context *ctx = &brw->ctx; 1654 1655 /* We consider depth writes disabled if the depth function is GL_EQUAL, 1656 * because it would just overwrite the existing depth value with itself. 1657 * 1658 * These bonus depth writes not only use bandwidth, but they also can 1659 * prevent early depth processing. For example, if the pixel shader 1660 * discards, the hardware must invoke the to determine whether or not 1661 * to do the depth write. If writes are disabled, we may still be able 1662 * to do the depth test before the shader, and skip the shader execution. 1663 * 1664 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains 1665 * a programming note saying to disable depth writes for EQUAL. 1666 */ 1667 return ctx->Depth.Test && ctx->Depth.Mask && ctx->Depth.Func != GL_EQUAL; 1668 } 1669 1670 void 1671 brw_emit_depthbuffer(struct brw_context *brw); 1672 1673 void 1674 brw_emit_depth_stencil_hiz(struct brw_context *brw, 1675 struct intel_mipmap_tree *depth_mt, 1676 uint32_t depth_offset, uint32_t depthbuffer_format, 1677 uint32_t depth_surface_type, 1678 struct intel_mipmap_tree *stencil_mt, 1679 bool hiz, bool separate_stencil, 1680 uint32_t width, uint32_t height, 1681 uint32_t tile_x, uint32_t tile_y); 1682 1683 void 1684 gen6_emit_depth_stencil_hiz(struct brw_context *brw, 1685 struct intel_mipmap_tree *depth_mt, 1686 uint32_t depth_offset, uint32_t depthbuffer_format, 1687 uint32_t depth_surface_type, 1688 struct intel_mipmap_tree *stencil_mt, 1689 bool hiz, bool separate_stencil, 1690 uint32_t width, uint32_t height, 1691 uint32_t tile_x, uint32_t tile_y); 1692 1693 void 1694 gen7_emit_depth_stencil_hiz(struct brw_context *brw, 1695 struct intel_mipmap_tree *depth_mt, 1696 uint32_t depth_offset, uint32_t depthbuffer_format, 1697 uint32_t depth_surface_type, 1698 struct intel_mipmap_tree *stencil_mt, 1699 bool hiz, bool separate_stencil, 1700 uint32_t width, uint32_t height, 1701 uint32_t tile_x, uint32_t tile_y); 1702 void 1703 gen8_emit_depth_stencil_hiz(struct brw_context *brw, 1704 struct intel_mipmap_tree *depth_mt, 1705 uint32_t depth_offset, uint32_t depthbuffer_format, 1706 uint32_t depth_surface_type, 1707 struct intel_mipmap_tree *stencil_mt, 1708 bool hiz, bool separate_stencil, 1709 uint32_t width, uint32_t height, 1710 uint32_t tile_x, uint32_t tile_y); 1711 1712 uint32_t get_hw_prim_for_gl_prim(int mode); 1713 1714 void 1715 gen6_upload_push_constants(struct brw_context *brw, 1716 const struct gl_program *prog, 1717 const struct brw_stage_prog_data *prog_data, 1718 struct brw_stage_state *stage_state); 1719 1720 bool 1721 gen9_use_linear_1d_layout(const struct brw_context *brw, 1722 const struct intel_mipmap_tree *mt); 1723 1724 /* brw_queryformat.c */ 1725 void brw_query_internal_format(struct gl_context *ctx, GLenum target, 1726 GLenum internalFormat, GLenum pname, 1727 GLint *params); 1728 1729 #ifdef __cplusplus 1730 } 1731 #endif 1732 1733 #endif 1734
