| /external/u-boot/drivers/ddr/marvell/a38x/ |
| ddr3_training_ip_centralization.h | 9 int ddr3_tip_centralization_tx(u32 dev_num);
10 int ddr3_tip_centralization_rx(u32 dev_num);
11 int ddr3_tip_print_centralization_result(u32 dev_num);
12 int ddr3_tip_special_rx(u32 dev_num);
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| ddr3_training_hw_algo.h | 9 int ddr3_tip_vref(u32 dev_num);
10 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id);
11 int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap);
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| ddr3_training_leveling.h | 11 int ddr3_tip_print_wl_supp_result(u32 dev_num);
12 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
14 u32 ddr3_tip_max_cs_get(u32 dev_num);
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| ddr3_training_ip_prv_if.h | 23 typedef int (*HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR)(u8 dev_num, int enable);
25 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
28 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
31 u8 dev_num, enum hws_ddr_freq freq,
34 u8 dev_num, struct ddr3_device_info *info_ptr);
36 u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info);
38 u8 dev_num, u32 if_id, enum hws_ddr_freq freq);
39 typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum hws_ddr_freq *freq);
41 u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
44 u32 dev_num, enum hws_access_type access_type, u32 dunit_id
[all...] |
| ddr3_training_ip_pbs.h | 36 int ddr3_tip_pbs_rx(u32 dev_num);
37 int ddr3_tip_print_all_pbs_result(u32 dev_num);
38 int ddr3_tip_pbs_tx(u32 dev_num);
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| ddr3_training_ip_flow.h | 126 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
129 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id,
132 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
134 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
137 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
139 int ddr3_tip_bus_read_modify_write(u32 dev_num,
144 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access,
147 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access,
151 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id,
153 int ddr3_tip_adjust_dqs(u32 dev_num);
[all...] |
| ddr3_training_ip_bist.h | 35 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
37 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
44 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
46 int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
48 int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num,
50 int ddr3_tip_print_regs(u32 dev_num);
51 int ddr3_tip_reg_dump(u32 dev_num);
52 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
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| ddr3_training.c | 90 static int ddr3_tip_ddr3_training_main_flow(u32 dev_num);
91 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
93 static int ddr3_tip_ddr3_auto_tune(u32 dev_num);
96 static int odt_test(u32 dev_num, enum hws_algo_type algo_type);
99 int adll_calibration(u32 dev_num, enum hws_access_type access_type,
101 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
207 static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id);
208 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
213 int ddr3_tip_tune_training_params(u32 dev_num,
258 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable
[all...] |
| ddr3_training_leveling.c | 19 static int ddr3_tip_dynamic_write_leveling_seq(u32 dev_num);
20 static int ddr3_tip_dynamic_read_leveling_seq(u32 dev_num);
21 static int ddr3_tip_dynamic_per_bit_read_leveling_seq(u32 dev_num);
22 static int ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id,
24 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id,
27 u32 ddr3_tip_max_cs_get(u32 dev_num)
32 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
35 CHECK_STATUS(ddr3_tip_get_first_active_if((u8)dev_num,
61 int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 freq)
64 u32 max_cs = ddr3_tip_max_cs_get(dev_num);
[all...] |
| ddr_training_ip_db.h | 13 u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index);
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| ddr3_debug.c | 109 int ddr3_tip_reg_dump(u32 dev_num)
113 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
122 (dev_num, ACCESS_TYPE_UNICAST,
140 (dev_num, if_id,
151 (dev_num, if_id,
167 int ddr3_tip_init_config_func(u32 dev_num,
173 memcpy(&config_func_info[dev_num], config_func,
183 u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM])
207 int ddr3_tip_get_device_info(u32 dev_num, struct ddr3_device_info *info_ptr)
209 if (config_func_info[dev_num].tip_get_device_info_func != NULL)
851 u32 bus_cnt = 0, if_id, data_p1, data_p2, ui_data3, dev_num = 0; local
1651 u32 dev_num = 0; local
[all...] |
| ddr3_training_hw_algo.c | 42 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
51 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
53 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
56 CHECK_STATUS(ddr3_tip_if_read(dev_num, access_type, if_id,
75 (dev_num, if_id,
99 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
103 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
111 int get_valid_win_rx(u32 dev_num, u32 if_id, u8 res[4])
124 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id,
145 int ddr3_tip_vref(u32 dev_num)
[all...] |
| ddr3_training_ip_engine.h | 32 int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type,
39 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern);
40 int ddr3_tip_load_all_pattern_to_mem(u32 dev_num);
41 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
51 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
62 int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
|
| ddr3_init.h | 150 int ddr3_tip_enable_init_sequence(u32 dev_num);
164 int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
165 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
168 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
169 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
170 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
172 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
174 int ddr3_tip_restore_dunit_regs(u32 dev_num);
182 int ddr3_tip_tune_training_params(u32 dev_num,
188 int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num)
[all...] |
| ddr3_training_ip_db.h | 90 void ddr3_tip_dev_attr_init(u32 dev_num);
91 u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id);
92 void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value);
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| ddr3_training_centralization.c | 26 static int ddr3_tip_centralization(u32 dev_num, u32 mode);
31 int ddr3_tip_centralization_rx(u32 dev_num)
33 CHECK_STATUS(ddr3_tip_special_rx(dev_num));
34 CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_RX));
42 int ddr3_tip_centralization_tx(u32 dev_num)
44 CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_TX));
52 static int ddr3_tip_centralization(u32 dev_num, u32 mode)
63 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
83 (dev_num, ACCESS_TYPE_UNICAST, if_id,
87 (dev_num, ACCESS_TYPE_UNICAST, if_id
[all...] |
| ddr3_training_pbs.c | 33 int ddr3_tip_pbs(u32 dev_num, enum pbs_dir pbs_mode)
51 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
60 (dev_num, ACCESS_TYPE_UNICAST, if_id,
65 (dev_num, ACCESS_TYPE_UNICAST, if_id,
72 ddr3_tip_read_adll_value(dev_num, nominal_adll, reg_addr, MASK_ALL_BITS);
75 ddr3_tip_ip_training(dev_num, ACCESS_TYPE_MULTICAST,
100 (dev_num, ACCESS_TYPE_MULTICAST,
187 (dev_num, ACCESS_TYPE_UNICAST, if_id,
194 (dev_num, ACCESS_TYPE_UNICAST, if_id,
203 ddr3_tip_ip_training(dev_num, ACCESS_TYPE_MULTICAST
[all...] |
| ddr3_training_ip_engine.c | 312 u32 *ddr3_tip_get_buf_ptr(u32 dev_num, enum hws_search_dir search,
334 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
355 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
377 (dev_num, access_type, interface_num,
381 (dev_num, access_type, interface_num,
386 (dev_num, access_type, interface_num,
390 (dev_num, access_type, interface_num,
396 ddr3_tip_load_pattern_to_odpg(dev_num, access_type, interface_num,
404 (dev_num, access_type, interface_num, direction,
412 (dev_num, access_type, interface_num
1458 u32 bus_cnt = 0, if_id, dev_num = 0; local
[all...] |
| ddr3_training_ip.h | 169 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table);
170 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
171 int hws_ddr3_tip_init_controller(u32 dev_num,
173 int hws_ddr3_tip_load_topology_map(u32 dev_num,
175 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
176 int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
177 int hws_ddr3_tip_read_training_result(u32 dev_num,
|
| /external/ltp/testcases/kernel/syscalls/ustat/ |
| ustat01.c | 17 static dev_t dev_num; variable
23 TEST(tst_syscall(__NR_ustat, dev_num, &ubuf));
38 dev_num = buf.st_dev;
|
| /external/u-boot/cmd/ |
| android_cmds.c | 31 int dev_num; local
37 dev_num = simple_strtoul(dev_part_str, &ep, 16);
44 *dev_desc = blk_get_dev(dev_iface, dev_num);
46 printf("Could not find %s %d\n", dev_iface, dev_num);
60 /* Split the part_name if passed as "$dev_num;part_name". */
|
| /external/ltp/testcases/kernel/device-drivers/zram/ |
| zram02.sh | 29 dev_num=1
31 # Number of items must be equal to 'dev_num' parameter.
|
| /external/linux-kselftest/tools/testing/selftests/zram/ |
| zram02.sh | 25 dev_num=1
27 # Number of items must be equal to 'dev_num' parameter.
|
| zram_lib.sh | 49 for i in $(seq 0 $(($dev_num - 1))); do
70 echo "create '$dev_num' zram device(s)"
71 modprobe zram num_devices=$dev_num
79 if [ "$dev_num_created" -ne "$dev_num" ]; then
110 echo "$sys_path = '$max_streams' ($i/$dev_num)"
128 echo "$sys_path = '$alg' ($i/$dev_num)"
144 echo "$sys_path = '$ds' ($i/$dev_num)"
161 echo "$sys_path = '$ds' ($i/$dev_num)"
171 for i in $(seq 0 $(($dev_num - 1))); do
227 for i in $(seq 0 $(($dev_num - 1))); d
[all...] |
| /external/u-boot/include/ |
| netdev.h | 30 int bcm_sf2_eth_register(bd_t *bis, u8 dev_num);
33 int cs8900_initialize(u8 dev_num, int base_addr);
41 int ep93xx_eth_initialize(u8 dev_num, int base_addr);
43 int ethoc_initialize(u8 dev_num, int base_addr);
51 int ks8851_mll_initialize(u8 dev_num, int base_addr);
52 int lan91c96_initialize(u8 dev_num, int base_addr);
70 int smc91111_initialize(u8 dev_num, int base_addr);
71 int smc911x_initialize(u8 dev_num, int base_addr);
|
