| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/ |
| suspend.c | 21 mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01);
|
| dram.c | 31 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ,
77 mmio_clrbits_32(PHY_REG(0, 927), (1 << 22));
78 mmio_clrbits_32(PHY_REG(1, 927), (1 << 22));
|
| stopwatch.c | 72 mmio_clrbits_32(SYST_CST, ENABLE);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt6795/ |
| scu.c | 24 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg,
27 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp0_axi_config,
|
| bl31_plat_setup.c | 136 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_rst_ctl,
|
| plat_pm.c | 438 mmio_clrbits_32(MTK_WDT_BASE,
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/ |
| scu.c | 24 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg,
27 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config,
|
| bl31_plat_setup.c | 56 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl,
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/include/ |
| rk3399_mcu.h | 18 #define mmio_clrbits_32(addr, clear) \ macro
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/ |
| mtcmos.c | 137 mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B);
143 mmio_clrbits_32(reg_pwr_con, PWR_RST_B);
145 mmio_clrbits_32(reg_pwr_con, PWR_ON);
146 mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND);
269 mmio_clrbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN);
|
| /device/linaro/bootloader/arm-trusted-firmware/include/lib/ |
| mmio.h | 52 static inline void mmio_clrbits_32(uintptr_t addr, uint32_t clear) function
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/socionext/uniphier/ |
| uniphier_psci.c | 73 mmio_clrbits_32(UNIPHIER_SLFRSTSEL, UNIPHIER_SLFRSTSEL_MASK);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/ |
| suspend.c | 253 mmio_clrbits_32(PI_REG(ch, 100), 0x3 << 8);
299 mmio_clrbits_32(PI_REG(ch, 60), 0x3 << 8);
347 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 24);
380 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 16);
394 mmio_clrbits_32(PI_REG(ch, 181), 0x1 << 8);
415 mmio_clrbits_32(PI_REG(ch, 124), 0x3 << 16);
419 mmio_clrbits_32(PHY_REG(ch, 927), (1 << 22));
611 mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT);
630 mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT);
|
| dfs.c | 641 mmio_clrbits_32(CTL_REG(i, 213), 1 << 16);
890 mmio_clrbits_32(CTL_REG(i, 213), (1 << 24));
1005 mmio_clrbits_32(CTL_REG(i, 305), 1 << 16);
1006 mmio_clrbits_32(CTL_REG(i, 71), 1);
1007 mmio_clrbits_32(CTL_REG(i, 70), 1 << 8);
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/ |
| hikey960_bl1_setup.c | 161 mmio_clrbits_32(PMU_SSI0_CLK_TOP_CTRL7_REG, NP_XO_ABB_DIG);
529 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN);
534 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1);
535 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN);
561 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL);
567 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL);
568 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL);
569 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/ |
| spm.c | 288 mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
364 mmio_clrbits_32(AP_PLL_CON3, 0xFFFFF);
365 mmio_clrbits_32(AP_PLL_CON4, 0xF);
|
| spm_suspend.c | 283 mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN);
289 mmio_clrbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN);
291 mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON);
|
| spm_hotplug.c | 244 mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK);
265 mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK);
|
| spm_mcdi.c | 260 mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
440 mmio_clrbits_32(SPM_PCM_RESERVE,
443 mmio_clrbits_32(SPM_PCM_RESERVE,
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/ |
| pmu.c | 412 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B));
441 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG));
887 mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle);
943 mmio_clrbits_32(GPIO3_BASE + 0x04, 0x00ffffff);
960 mmio_clrbits_32(GPIO2_BASE + 0x04, 0x00001fff);
977 mmio_clrbits_32(GPIO2_BASE + 0x04, 0x1fff0000);
994 mmio_clrbits_32(GPIO4_BASE + 0x04, 0x7fff0000);
1010 mmio_clrbits_32(GPIO3_BASE + 0x04, 0xff000000);
1011 mmio_clrbits_32(GPIO4_BASE + 0x04, 0x000000ff);
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/drivers/pwrc/ |
| hisi_pwrc.c | 145 mmio_clrbits_32(CPUIDLE_FLAG_REG(cluster), BIT(core));
218 mmio_clrbits_32(REG_SCBAKDATA3_OFFSET, flag);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/ |
| pmu.c | 494 mmio_clrbits_32(DDR_UPCTL_BASE + DDR_PCTL2_PWRCTL, SELFREF_EN);
541 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(2));
543 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(0));
|
| /device/linaro/bootloader/arm-trusted-firmware/drivers/synopsys/ufs/ |
| dw_ufs.c | 80 mmio_clrbits_32(base + AHIT, 0x3FF);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/ |
| soc.c | 297 mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON,
|
