| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 189 SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
190 switch (Op.getOpcode()) {
192 return LowerBR_CC(Op, DAG);
194 return LowerGlobalAddress(Op, DAG);
196 return LowerSELECT_CC(Op, DAG);
498 SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
499 SDValue Chain = Op.getOperand(0);
500 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
501 SDValue LHS = Op.getOperand(2);
502 SDValue RHS = Op.getOperand(3)
[all...] |
| /external/swiftshader/third_party/subzero/pnacl-llvm/include/llvm/Bitcode/NaCl/ |
| NaClBitCodes.h | 192 /// \brief Compares this to Op. Returns <0 if this is less than Op,
193 /// Returns 0 if they are equal, and >0 if this is greater than Op.
194 int Compare(const NaClBitCodeAbbrevOp &Op) const {
196 int EncodingDiff = static_cast<int>(Enc) - static_cast<int>(Op.Enc);
201 return ValCompare(Op);
208 int ValCompare(const NaClBitCodeAbbrevOp &Op) const {
209 if (Val < Op.Val)
211 else if (Val > Op.Val)
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Scalarizer.cpp | 292 // Replace Op with the gathered form of the components in CV. Defer the
293 // deletion of Op and creation of the gathered form to the end of the pass,
294 // so that we can avoid creating the gathered form if all uses of Op are
296 void Scalarizer::gather(Instruction *Op, const ValueVector &CV) {
297 // Since we're not deleting Op yet, stub out its operands, so that it
299 for (unsigned I = 0, E = Op->getNumOperands(); I != E; ++I)
300 Op->setOperand(I, UndefValue::get(Op->getOperand(I)->getType()));
302 transferMetadata(Op, CV);
304 // If we already have a scattered form of Op (created from ExtractElement
[all...] |
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 196 TreePatternNode *Op = InstPatNode->getChild(i);
199 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
201 if (!Op->getPredicateFns().empty()) {
202 TreePredicateFn PredFn = Op->getPredicateFns()[0];
206 if (Op->getPredicateFns().size() > 1 ||
221 //if (Op->getType(0) != VT)
231 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
234 if (!Op->isLeaf())
[all...] |
| CodeGenInstruction.cpp | 160 CGIOperandList::ParseOperandName(const std::string &Op, bool AllowWholeOp) {
161 if (Op.empty() || Op[0] != '$')
162 PrintFatalError(TheDef->getName() + ": Illegal operand name: '" + Op + "'");
164 std::string OpName = Op.substr(1);
172 PrintFatalError(TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'");
183 " whole operand part of complex operand '" + Op + "'");
192 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'");
200 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'");
215 std::pair<unsigned,unsigned> Op = Ops.ParseOperandName(Name, false)
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| FastISelEmitter.cpp | 189 TreePatternNode *Op = InstPatNode->getChild(i);
192 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
194 if (!Op->getPredicateFns().empty()) {
195 TreePredicateFn PredFn = Op->getPredicateFns()[0];
199 if (Op->getPredicateFns().size() > 1 ||
214 //if (Op->getType(0) != VT)
224 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
227 if (!Op->isLeaf())
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 207 TreePatternNode *Op = InstPatNode->getChild(i);
210 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
212 if (!Op->getPredicateFns().empty()) {
213 TreePredicateFn PredFn = Op->getPredicateFns()[0];
217 if (Op->getPredicateFns().size() > 1 ||
238 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
241 if (!Op->isLeaf()) {
242 if (Op->getOperator()->getName() == "fpimm")
[all...] |
| CodeGenInstruction.cpp | 161 CGIOperandList::ParseOperandName(const std::string &Op, bool AllowWholeOp) {
162 if (Op.empty() || Op[0] != '$')
163 PrintFatalError(TheDef->getName() + ": Illegal operand name: '" + Op + "'");
165 std::string OpName = Op.substr(1);
173 PrintFatalError(TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'");
184 " whole operand part of complex operand '" + Op + "'");
193 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'");
201 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'");
216 std::pair<unsigned,unsigned> Op = Ops.ParseOperandName(Name, false)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 195 SDValue MBlazeTargetLowering::LowerOperation(SDValue Op,
197 switch (Op.getOpcode())
199 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
200 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
201 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
202 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
203 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
204 case ISD::VASTART: return LowerVASTART(Op, DAG);
568 SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op,
570 SDValue LHS = Op.getOperand(0)
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 41 static inline const char *getAddrOpcStr(AddrOpc Op) {
42 return Op == sub ? "-" : "";
45 static inline const char *getShiftOpcStr(ShiftOpc Op) {
46 switch (Op) {
56 static inline unsigned getShiftOpcEncoding(ShiftOpc Op) {
57 switch (Op) {
115 static inline unsigned getSORegOffset(unsigned Op) {
116 return Op >> 3;
118 static inline ShiftOpc getSORegShOp(unsigned Op) {
119 return (ShiftOpc)(Op & 7)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitDouble.cpp | 187 for (auto &Op : MI->operands()) {
188 if (!Op.isReg())
190 unsigned R = Op.getReg();
230 MachineOperand &Op = *U;
231 MachineInstr *UseI = Op.getParent();
237 if (&MO == &Op || !MO.isReg() || MO.getSubReg())
305 for (const auto &Op : MI->operands())
306 if (!Op.getSubReg())
396 for (auto &Op : UseI->operands()) {
397 if (Op.isReg() && Part.count(Op.getReg())
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 41 inline const char *getAddrOpcStr(AddrOpc Op) { return Op == sub ? "-" : ""; }
43 inline const char *getShiftOpcStr(ShiftOpc Op) {
44 switch (Op) {
54 inline unsigned getShiftOpcEncoding(ShiftOpc Op) {
55 switch (Op) {
113 inline unsigned getSORegOffset(unsigned Op) { return Op >> 3; }
114 inline ShiftOpc getSORegShOp(unsigned Op) { return (ShiftOpc)(Op & 7);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonSplitDouble.cpp | 211 for (auto &Op : MI->operands()) {
212 if (!Op.isReg())
214 unsigned R = Op.getReg();
253 MachineOperand &Op = *U;
254 MachineInstr *UseI = Op.getParent();
260 if (&MO == &Op || !MO.isReg() || MO.getSubReg())
321 for (const auto &Op : MI->operands())
322 if (!Op.getSubReg())
443 for (auto &Op : UseI->operands()) {
444 if (Op.isReg() && Part.count(Op.getReg())
[all...] |
| HexagonConstExtenders.cpp | 232 Register(const MachineOperand &Op)
233 : Reg(Op.getReg()), Sub(Op.getSubReg()) {}
234 Register &operator=(const MachineOperand &Op) {
235 if (Op.isReg()) {
236 Reg = Op.getReg();
237 Sub = Op.getSubReg();
238 } else if (Op.isFI()) {
239 Reg = TargetRegisterInfo::index2StackSlot(Op.getIndex());
350 ExtRoot(const MachineOperand &Op);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86ExpandPseudo.cpp | 216 unsigned Op;
219 Op = X86::TAILJMPd;
222 Op = X86::TAILJMPd_CC;
228 Op = X86::TAILJMPd64_CC;
233 Op = X86::TAILJMPd64;
236 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
245 if (Op == X86::TAILJMPd_CC || Op == X86::TAILJMPd64_CC) {
250 unsigned Op = (Opcode == X86::TCRETURNmi)
253 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
[all...] |
| /external/clang/lib/Sema/ |
| SemaCast.cpp | 247 CastOperation Op(*this, DestType, E);
248 Op.OpRange = SourceRange(OpLoc, Parens.getEnd());
249 Op.DestRange = AngleBrackets;
256 Op.CheckConstCast();
257 if (Op.SrcExpr.isInvalid())
260 return Op.complete(CXXConstCastExpr::Create(Context, Op.ResultType,
261 Op.ValueKind, Op.SrcExpr.get(), DestTInfo,
267 Op.CheckDynamicCast()
[all...] |
| /external/deqp-deps/glslang/SPIRV/ |
| SpvBuilder.h | 165 Op getOpCode(Id id) const { return module.getInstruction(id)->getOpCode(); }
166 Op getTypeClass(Id typeId) const { return getOpCode(typeId); }
167 Op getMostBasicTypeClass(Id typeId) const;
198 bool containsType(Id typeId, Op typeOp, unsigned int width) const;
201 bool isConstantOpCode(Op opcode) const;
202 bool isSpecConstantOpCode(Op opcode) const;
326 void createNoResultOp(Op);
327 void createNoResultOp(Op, Id operand);
328 void createNoResultOp(Op, const std::vector<Id>& operands);
329 void createNoResultOp(Op, const std::vector<IdImmediate>& operands)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 145 SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
147 DebugLoc DL = Op.getDebugLoc();
148 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
150 Op = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
151 return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
154 SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op,
156 DebugLoc DL = Op.getDebugLoc();
157 int JTI = cast<JumpTableSDNode>(Op)->getIndex();
159 Op = DAG.getTargetJumpTable(JTI, MVT::i32);
160 return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
[all...] |
| /external/skia/bench/ |
| VertexColorSpaceBench.cpp | 121 class Op : public GrMeshDrawOp {
127 Op(GrColor color)
134 Op(const SkColor4f& color4f, Mode mode)
142 Op(GrColor color, sk_sp<GrColorSpaceXform> colorSpaceXform)
282 std::unique_ptr<GrDrawOp> op = nullptr; variable
286 op = pool->allocate<Op>(SkColorToPremulGrColor(c));
289 op = pool->allocate<Op>(SkColorToUnpremulGrColor(c), xform);
295 op = pool->allocate<Op>(c4f, fMode)
[all...] |
| /external/skqp/bench/ |
| VertexColorSpaceBench.cpp | 121 class Op : public GrMeshDrawOp {
127 Op(GrColor color)
134 Op(const SkColor4f& color4f, Mode mode)
142 Op(GrColor color, sk_sp<GrColorSpaceXform> colorSpaceXform)
278 std::unique_ptr<GrDrawOp> op = nullptr; variable
282 op = pool->allocate<Op>(SkColorToPremulGrColor(c));
285 op = pool->allocate<Op>(SkColorToUnpremulGrColor(c), xform);
291 op = pool->allocate<Op>(c4f, fMode)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 93 assert(Modifier && "Must specify 'cc' or 'reg' as predicate op modifier!");
111 "Need to specify 'cc' or 'reg' as predicate op modifier!");
248 const MCOperand &Op = MI->getOperand(OpNo);
249 if (Op.isReg()) {
250 const char *RegName = getRegisterName(Op.getReg());
259 if (Op.isImm()) {
260 O << Op.getImm();
264 assert(Op.isExpr() && "unknown operand kind in printOperand");
265 O << *Op.getExpr();
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 280 // Check for additional literals in SRC0/1/2 (Op 1/2/3)
288 const MCOperand &Op = MI.getOperand(i);
289 if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255)
295 if (Op.isImm())
296 Imm = Op.getImm();
297 else if (Op.isExpr()) {
298 if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
301 } else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 219 // parameter starting at index Idx using a single vectorized op of
221 // covered by the vector op. Otherwise, it returns 1.
359 auto setFP16OperationAction = [&](unsigned Op, MVT VT, LegalizeAction Action,
361 setOperationAction(Op, VT, STI.allowFP16Math() ? Action : NoF16Action);
525 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
526 setFP16OperationAction(Op, MVT::f16, Legal, Promote);
527 setFP16OperationAction(Op, MVT::v2f16, Legal, Expand);
537 for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT,
539 setOperationAction(Op, MVT::f16, Legal);
540 setOperationAction(Op, MVT::f32, Legal)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsISelLowering.cpp | 492 // Returns Op if setcc is not a floating point comparison.
493 static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
495 if (Op.getOpcode() != ISD::SETCC)
496 return Op;
498 SDValue LHS = Op.getOperand(0);
501 return Op;
503 SDValue RHS = Op.getOperand(1);
504 DebugLoc dl = Op.getDebugLoc();
508 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
553 // Op's first operand must be a shift right
[all...] |
