| Up to higher level directory | |||
| Name | Date | Size | |
|---|---|---|---|
| README.core_prefetch | 22-Oct-2020 | 745 | |
| README.falcon | 22-Oct-2020 | 6K | |
| README.lsch2 | 22-Oct-2020 | 233 | |
| README.lsch3 | 22-Oct-2020 | 16.5K | |
| README.qspi | 22-Oct-2020 | 1.4K | |
| README.soc | 22-Oct-2020 | 11K | |
README.core_prefetch
1 Core instruction prefetch disable 2 --------------------------------- 3 To disable instruction prefetch of core; hwconfig needs to be updated. 4 for e.g. 5 setenv hwconfig 'fsl_ddr:bank_intlv=auto;core_prefetch:disable=0x02' 6 7 Here 0x02 can be replaced with any valid value except Mask[0] bit. It 8 represents 64 bit mask. The 64-bit Mask has one bit for each core. 9 Mask[0] = core0 10 Mask[1] = core1 11 Mask[2] = core2 12 etc 13 If the bit is set ('b1) in the mask, then prefetch is disabled for 14 that core when it is released from reset. 15 16 core0 prefetch should not be disabled i.e. Mask[0] should never be set. 17 Setting Mask[0] may lead to undefined behavior. 18 19 Once disabled, prefetch remains disabled until the next reset. 20 There is no function to re-enable prefetch. 21
README.falcon
1 Falcon boot option 2 ------------------ 3 Falcon boot is a short cut boot method for SD/eMMC targets. It skips loading the 4 RAM version U-Boot. Instead, it loads FIT image and boot directly to Linux. 5 CONFIG_SPL_OS_BOOT enables falcon boot. CONFIG_SPL_LOAD_FIT enables the FIT 6 image support (also need CONFIG_SPL_OF_LIBFDT, CONFIG_SPL_FIT and optionally 7 CONFIG_SPL_GZIP). 8 9 To enable falcon boot, a hook function spl_start_uboot() returns 0 to indicate 10 booting U-Boot is not the first choice. The kernel FIT image needs to be put 11 at CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR. SPL mmc driver reads the header to 12 determine if this is a FIT image. If true, FIT image components are parsed and 13 copied or decompressed (if applicable) to their destinations. If FIT image is 14 not found, normal U-Boot flow will follow. 15 16 An important part of falcon boot is to prepare the device tree. A normal U-Boot 17 does FDT fixups when booting Linux. For falcon boot, Linux boots directly from 18 SPL, skipping the normal U-Boot. The device tree has to be prepared in advance. 19 A command "spl export" should be called under the normal RAM version U-Boot. 20 It is equivalent to go through "bootm" step-by-step until device tree fixup is 21 done. The device tree in memory is the one needed for falcon boot. Falcon boot 22 flow suggests to save this image to SD/eMMC at the location pointed by macro 23 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR, with maximum size specified by macro 24 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS. However, when FIT image is used for 25 Linux, the device tree stored in FIT image overwrites the memory loaded by spl 26 driver from these sectors. We could change this loading order to favor the 27 stored sectors. But when secure boot is enabled, these sectors are used for 28 signature header and needs to be loaded before the FIT image. So it is important 29 to understand the device tree in FIT image should be the one actually used, or 30 leave it absent to favor the stored sectors. It is easier to deploy the FIT 31 image with embedded static device tree to multiple boards. 32 33 Macro CONFIG_SYS_SPL_ARGS_ADDR serves two purposes. One is the pointer to load 34 the stored sectors to. Normally this is the static device tree. The second 35 purpose is the memory location of signature header for secure boot. After the 36 FIT image is loaded into memory, it is validated against the signature header 37 before individual components are extracted (and optionally decompressed) into 38 their final memory locations, respectively. After the validation, the header 39 is no longer used. The static device tree is copied into this location. So 40 this macro is passed as the location of device tree when booting Linux. 41 42 Steps to prepare static device tree 43 ----------------------------------- 44 To prepare the static device tree for Layerscape boards, it is important to 45 understand the fixups in U-Boot. Memory size and location, as well as reserved 46 memory blocks are added/updated. Ethernet MAC addressed are updated. FMan 47 microcode (if used) is embedded in the device tree. Kernel command line and 48 initrd information are embedded. Others including CPU status, boot method, 49 Ethernet port status, etc. are also updated. 50 51 Following normal booting process, all variables are set, all images are loaded 52 before "bootm" command would be issued to boot, run command 53 54 spl export fdt <address> 55 56 where the address is the location of FIT image. U-Boot goes through the booting 57 process as if "bootm start", "bootm loados", "bootm ramdisk"... commands but 58 stops before "bootm go". There we have the fixed-up device tree in memory. 59 We can check the device tree header by these commands 60 61 fdt addr <fdt address> 62 fdt header 63 64 Where the fdt address is the device tree in memory. It is printed by U-Boot. 65 It is useful to know the exact size. One way to extract this static device 66 tree is to save it to eMMC/SD using command in U-Boot, and extract under Linux 67 with these commands, repectively 68 69 mmc write <address> <sector> <sectors> 70 dd if=/dev/mmcblk0 of=<filename> bs=512 skip=<sector> count=<sectors> 71 72 Note, U-Boot takes values as hexadecimals while Linux takes them as decimals by 73 default. If using NAND or other storage, the commands are slightly different. 74 When we have the static device tree image, we can re-make the FIT image with 75 it. It is important to specify the load addresses in FIT image for every 76 components. Otherwise U-Boot cannot load them correctly. 77 78 Generate FIT image with static device tree 79 ------------------------------------------ 80 Example: 81 82 /dts-v1/; 83 84 / { 85 description = "Image file for the LS1043A Linux Kernel"; 86 #address-cells = <1>; 87 88 images { 89 kernel { 90 description = "ARM64 Linux kernel"; 91 data = /incbin/("./arch/arm64/boot/Image.gz"); 92 type = "kernel"; 93 arch = "arm64"; 94 os = "linux"; 95 compression = "gzip"; 96 load = <0x80080000>; 97 entry = <0x80080000>; 98 }; 99 fdt-1 { 100 description = "Flattened Device Tree blob"; 101 data = /incbin/("./fsl-ls1043ardb-static.dtb"); 102 type = "flat_dt"; 103 arch = "arm64"; 104 compression = "none"; 105 load = <0x90000000>; 106 }; 107 ramdisk { 108 description = "LS1043 Ramdisk"; 109 data = /incbin/("./rootfs.cpio.gz"); 110 type = "ramdisk"; 111 arch = "arm64"; 112 os = "linux"; 113 compression = "gzip"; 114 load = <0xa0000000>; 115 }; 116 }; 117 118 configurations { 119 default = "config-1"; 120 config-1 { 121 description = "Boot Linux kernel"; 122 kernel = "kernel"; 123 fdt = "fdt-1"; 124 ramdisk = "ramdisk"; 125 loadables = "fdt", "ramdisk"; 126 }; 127 }; 128 }; 129 130 The "loadables" is not optional. It tells SPL which images to load into memory. 131 132 Other things to consider 133 ----------------------- 134 Falcon boot skips a lot of initialization in U-Boot. If Linux expects the 135 hardware to be initialized by U-Boot, the related code should be ported to SPL 136 build. For example, if Linux expect Ethernet PHY to be initialized in U-Boot 137 (which is not a common case), the PHY initialization has to be included in 138 falcon boot. This increases the SPL image size and should be handled carefully. 139 If Linux has PHY driver enabled, it still depends on the correct MDIO bus setup 140 in U-Boot. Normal U-Boot sets the MDC ratio to generate a proper clock signal. 141
README.lsch2
1 # 2 # Copyright 2015 Freescale Semiconductor 3 # 4 # SPDX-License-Identifier: GPL-2.0+ 5 # 6 7 Freescale LayerScape with Chassis Generation 2 8 9 This architecture supports Freescale ARMv8 SoCs with Chassis generation 2, 10 for example LS1043A. 11
README.lsch3
1 # 2 # Copyright 2014-2015 Freescale Semiconductor 3 # 4 # SPDX-License-Identifier: GPL-2.0+ 5 # 6 7 Freescale LayerScape with Chassis Generation 3 8 9 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, 10 for example LS2080A. 11 12 DDR Layout 13 ============ 14 Entire DDR region splits into two regions. 15 - Region 1 is at address 0x8000_0000 to 0xffff_ffff. 16 - Region 2 is at 0x80_8000_0000 to the top of total memory, 17 for example 16GB, 0x83_ffff_ffff. 18 19 All DDR memory is marked as cache-enabled. 20 21 When MC and Debug server is enabled, they carve 512MB away from the high 22 end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB 23 with MC and Debug server enabled. Linux only sees 15.5GB. 24 25 The reserved 512MB layout looks like 26 27 +---------------+ <-- top/end of memory 28 | 256MB | debug server 29 +---------------+ 30 | 256MB | MC 31 +---------------+ 32 | ... | 33 34 MC requires the memory to be aligned with 512MB, so even debug server is 35 not enabled, 512MB is reserved, not 256MB. 36 37 Flash Layout 38 ============ 39 40 (1) A typical layout of various images (including Linux and other firmware images) 41 is shown below considering a 32MB NOR flash device present on most 42 pre-silicon platforms (simulator and emulator): 43 44 ------------------------- 45 | FIT Image | 46 | (linux + DTB + RFS) | 47 ------------------------- ----> 0x0120_0000 48 | Debug Server FW | 49 ------------------------- ----> 0x00C0_0000 50 | AIOP FW | 51 ------------------------- ----> 0x0070_0000 52 | MC FW | 53 ------------------------- ----> 0x006C_0000 54 | MC DPL Blob | 55 ------------------------- ----> 0x0020_0000 56 | BootLoader + Env| 57 ------------------------- ----> 0x0000_1000 58 | PBI | 59 ------------------------- ----> 0x0000_0080 60 | RCW | 61 ------------------------- ----> 0x0000_0000 62 63 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator) 64 65 (2) A typical layout of various images (including Linux and other firmware images) 66 is shown below considering a 128MB NOR flash device present on QDS and RDB 67 boards: 68 ----------------------------------------- ----> 0x5_8800_0000 --- 69 | .. Unused .. (7M) | | 70 ----------------------------------------- ----> 0x5_8790_0000 | 71 | FIT Image (linux + DTB + RFS) (40M) | | 72 ----------------------------------------- ----> 0x5_8510_0000 | 73 | PHY firmware (2M) | | 74 ----------------------------------------- ----> 0x5_84F0_0000 | 64K 75 | Debug Server FW (2M) | | Alt 76 ----------------------------------------- ----> 0x5_84D0_0000 | Bank 77 | AIOP FW (4M) | | 78 ----------------------------------------- ----> 0x5_8490_0000 (vbank4) 79 | MC DPC Blob (1M) | | 80 ----------------------------------------- ----> 0x5_8480_0000 | 81 | MC DPL Blob (1M) | | 82 ----------------------------------------- ----> 0x5_8470_0000 | 83 | MC FW (4M) | | 84 ----------------------------------------- ----> 0x5_8430_0000 | 85 | BootLoader Environment (1M) | | 86 ----------------------------------------- ----> 0x5_8420_0000 | 87 | BootLoader (1M) | | 88 ----------------------------------------- ----> 0x5_8410_0000 | 89 | RCW and PBI (1M) | | 90 ----------------------------------------- ----> 0x5_8400_0000 --- 91 | .. Unused .. (7M) | | 92 ----------------------------------------- ----> 0x5_8390_0000 | 93 | FIT Image (linux + DTB + RFS) (40M) | | 94 ----------------------------------------- ----> 0x5_8110_0000 | 95 | PHY firmware (2M) | | 96 ----------------------------------------- ----> 0x5_80F0_0000 | 64K 97 | Debug Server FW (2M) | | Bank 98 ----------------------------------------- ----> 0x5_80D0_0000 | 99 | AIOP FW (4M) | | 100 ----------------------------------------- ----> 0x5_8090_0000 (vbank0) 101 | MC DPC Blob (1M) | | 102 ----------------------------------------- ----> 0x5_8080_0000 | 103 | MC DPL Blob (1M) | | 104 ----------------------------------------- ----> 0x5_8070_0000 | 105 | MC FW (4M) | | 106 ----------------------------------------- ----> 0x5_8030_0000 | 107 | BootLoader Environment (1M) | | 108 ----------------------------------------- ----> 0x5_8020_0000 | 109 | BootLoader (1M) | | 110 ----------------------------------------- ----> 0x5_8010_0000 | 111 | RCW and PBI (1M) | | 112 ----------------------------------------- ----> 0x5_8000_0000 --- 113 114 128-MB NOR flash layout for QDS and RDB boards 115 116 Environment Variables 117 ===================== 118 mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined 119 the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. 120 121 mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value 122 CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. 123 124 mcinitcmd: This environment variable is defined to initiate MC and DPL deployment 125 from the location where it is stored(NOR, NAND, SD, SATA, USB)during 126 u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR 127 will be null and MC will not be booted and DPL will not be applied 128 during U-boot booting.However the MC, DPC and DPL can be applied from 129 console independently. 130 The variable needs to be set from the console once and then on 131 rebooting the parameters set in the variable will automatically be 132 executed. The commmand is demostrated taking an example of mc boot 133 using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR flash: 134 135 cp.b 0xa0000000 0x580300000 $filesize 136 cp.b 0x80000000 0x580800000 $filesize 137 cp.b 0x90000000 0x580700000 $filesize 138 139 setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000' 140 141 If only linux is to be booted then the mcinitcmd environment should be set as 142 143 setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000' 144 145 Here the addresses 0xa0000000, 0x80000000, 0x80000000 are of DDR to where 146 MC binary, DPC binary and DPL binary are stored and 0x580300000, 0x580800000 147 and 0x580700000 are addresses in NOR where these are copied. It is to be 148 noted that these addresses in 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000' 149 can be replaced with the addresses of DDR to 150 which these will be copied in case of these binaries being stored in other 151 devices like SATA, USB, NAND, SD etc. 152 153 Booting from NAND 154 ------------------- 155 Booting from NAND requires two images, RCW and u-boot-with-spl.bin. 156 The difference between NAND boot RCW image and NOR boot image is the PBI 157 command sequence. Below is one example for PBI commands for LS2085AQDS which 158 uses NAND device with 2KB/page, block size 128KB. 159 160 1) CCSR 4-byte write to 0x00e00404, data=0x00000000 161 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 162 The above two commands set bootloc register to 0x00000000_1800a000 where 163 the u-boot code will be running in OCRAM. 164 165 3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000, 166 BLOCK_SIZE=0x00014000 167 This command copies u-boot image from NAND device into OCRAM. The values need 168 to adjust accordingly. 169 170 SRC should match the cfg_rcw_src, the reset config pins. It depends 171 on the NAND device. See reference manual for cfg_rcw_src. 172 SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In 173 the example above, 128KB. For easy maintenance, we put it at 174 the beginning of next block from RCW. 175 DEST_ADDR is fixed at 0x1800a000, matching bootloc set above. 176 BLOCK_SIZE is the size to be copied by PBI. 177 178 RCW image should be written to the beginning of NAND device. Example of using 179 u-boot command 180 181 nand write <rcw image in memory> 0 <size of rcw image> 182 183 To form the NAND image, build u-boot with NAND config, for example, 184 ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin. 185 The u-boot image should be written to match SRC_ADDR, in above example 0x20000. 186 187 nand write <u-boot image in memory> 200000 <size of u-boot image> 188 189 With these two images in NAND device, the board can boot from NAND. 190 191 Another example for LS2085ARDB boards, 192 193 1) CCSR 4-byte write to 0x00e00404, data=0x00000000 194 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 195 3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000, 196 BLOCK_SIZE=0x00014000 197 198 nand write <rcw image in memory> 0 <size of rcw image> 199 nand write <u-boot image in memory> 80000 <size of u-boot image> 200 201 Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image 202 to match board NAND device with 4KB/page, block size 512KB. 203 204 Note, LS2088A and LS1088A don't support booting from NAND. 205 206 Booting from SD/eMMC 207 ------------------- 208 Booting from SD/eMMC requires two images, RCW and u-boot-with-spl.bin. 209 The difference between SD boot RCW image and QSPI-NOR boot image is the 210 PBI command sequence. Below is one example for PBI commands for RDB 211 and QDS which uses SD device with block size 512. Block location can be 212 calculated by dividing offset with block size. 213 214 1) Block Copy: SRC=0x0040, SRC_ADDR=0x00100000, DEST_ADDR=0x1800a000, 215 BLOCK_SIZE=0x00016000 216 217 This command copies u-boot image from SD device into OCRAM. The values 218 need to adjust accordingly for SD/eMMC 219 220 SRC should match the cfg_rcw_src, the reset config pins. 221 The value for source(SRC) can be 0x0040 or 0x0041 222 depending upon SD or eMMC. 223 SRC_ADDR is the offset of u-boot-with-spl.bin image in SD device. 224 In the example above, 1MB. This is same as QSPI-NOR. 225 DEST_ADDR is configured at 0x1800a000, matching bootloc set above. 226 BLOCK_SIZE is the size to be copied by PBI. 227 228 2) CCSR 4-byte write to 0x01e00404, data=0x00000000 229 3) CCSR 4-byte write to 0x01e00400, data=0x1800a000 230 The above two commands set bootloc register to 0x00000000_1800a000 where 231 the u-boot code will be running in OCRAM. 232 233 234 RCW image should be written at 8th block of device(SD/eMMC). Example of 235 using u-boot command 236 237 mmc erase 0x8 0x10 238 mmc write <rcw image in memory> 0x8 <size of rcw in block count typical value=10> 239 240 To form the SD-Boot image, build u-boot with SD config, for example, 241 ls1088ardb_sdcard_qspi_defconfig. The image needed is u-boot-with-spl.bin. 242 The u-boot image should be written to match SRC_ADDR, in above example 243 offset 0x100000 in other work it means block location 0x800 244 245 mmc erase 0x800 0x1800 246 mmc write <u-boot image in memory> 0x800 <size of u-boot image in block count> 247 248 With these two images in SD/eMMC device, the board can boot from SD/eMMC. 249 250 MMU Translation Tables 251 ====================== 252 253 (1) Early MMU Tables: 254 255 Level 0 Level 1 Level 2 256 ------------------ ------------------ ------------------ 257 | 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | 258 ------------------ ------------------ ------------------ 259 | 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | 260 ------------------ | ------------------ ------------------ 261 | invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | 262 ------------------ | ------------------ ------------------ 263 | | 0x00_c000_0000 | | 0x00_0060_0000 | 264 | ------------------ ------------------ 265 | | 0x01_0000_0000 | | 0x00_0080_0000 | 266 | ------------------ ------------------ 267 | ... ... 268 | ------------------ 269 | | 0x05_8000_0000 | --| 270 | ------------------ | 271 | | 0x05_c000_0000 | | 272 | ------------------ | 273 | ... | 274 | ------------------ | ------------------ 275 |--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 | 276 ------------------ ------------------ 277 | 0x80_4000_0000 | | 0x00_3020_0000 | 278 ------------------ ------------------ 279 | 0x80_8000_0000 | | 0x00_3040_0000 | 280 ------------------ ------------------ 281 | 0x80_c000_0000 | | 0x00_3060_0000 | 282 ------------------ ------------------ 283 | 0x81_0000_0000 | | 0x00_3080_0000 | 284 ------------------ ------------------ 285 ... ... 286 287 (2) Final MMU Tables: 288 289 Level 0 Level 1 Level 2 290 ------------------ ------------------ ------------------ 291 | 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | 292 ------------------ ------------------ ------------------ 293 | 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | 294 ------------------ | ------------------ ------------------ 295 | invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | 296 ------------------ | ------------------ ------------------ 297 | | 0x00_c000_0000 | | 0x00_0060_0000 | 298 | ------------------ ------------------ 299 | | 0x01_0000_0000 | | 0x00_0080_0000 | 300 | ------------------ ------------------ 301 | ... ... 302 | ------------------ 303 | | 0x08_0000_0000 | --| 304 | ------------------ | 305 | | 0x08_4000_0000 | | 306 | ------------------ | 307 | ... | 308 | ------------------ | ------------------ 309 |--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 | 310 ------------------ ------------------ 311 | 0x80_4000_0000 | | 0x08_0020_0000 | 312 ------------------ ------------------ 313 | 0x80_8000_0000 | | 0x08_0040_0000 | 314 ------------------ ------------------ 315 | 0x80_c000_0000 | | 0x08_0060_0000 | 316 ------------------ ------------------ 317 | 0x81_0000_0000 | | 0x08_0080_0000 | 318 ------------------ ------------------ 319 ... ... 320 321 322 DPAA2 commands to manage Management Complex (MC) 323 ------------------------------------------------ 324 DPAA2 commands has been introduced to manage Management Complex 325 (MC). These commands are used to start mc, aiop and apply DPL 326 from u-boot command prompt. 327 328 Please note Management complex Firmware(MC), DPL and DPC are no 329 more deployed during u-boot boot-sequence. 330 331 Commands: 332 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex 333 b) fsl_mc apply DPL <DPL_addr> - Apply DPL file 334 c) fsl_mc start aiop <FW_addr> - Start AIOP 335 336 How to use commands :- 337 1. Command sequence for u-boot ethernet: 338 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex 339 b) DPMAC net-devices are now available for use 340 341 Example- 342 Assumption: MC firmware, DPL and DPC dtb is already programmed 343 on NOR flash. 344 345 => fsl_mc start mc 580300000 580800000 346 => setenv ethact DPMAC1@xgmii 347 => ping $serverip 348 349 2. Command sequence for Linux boot: 350 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex 351 b) fsl_mc apply DPL <DPL_addr> - Apply DPL file 352 c) No DPMAC net-devices are available for use in u-boot 353 d) boot Linux 354 355 Example- 356 Assumption: MC firmware, DPL and DPC dtb is already programmed 357 on NOR flash. 358 359 => fsl_mc start mc 580300000 580800000 360 => setenv ethact DPMAC1@xgmii 361 => tftp a0000000 kernel.itb 362 => fsl_mc apply dpl 580700000 363 => bootm a0000000 364 365 3. Command sequence for AIOP boot: 366 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex 367 b) fsl_mc start aiop <FW_addr> - Start AIOP 368 c) fsl_mc apply DPL <DPL_addr> - Apply DPL file 369 d) No DPMAC net-devices are availabe for use in u-boot 370 Please note actual AIOP start will happen during DPL parsing of 371 Management complex 372 373 Example- 374 Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already 375 programmed on NOR flash. 376 377 => fsl_mc start mc 580300000 580800000 378 => fsl_mc start aiop 0x580900000 379 => setenv ethact DPMAC1@xgmii 380 => fsl_mc apply dpl 580700000 381 382 Errata A009635 383 --------------- 384 If the core runs at higher than x3 speed of the platform, there is 385 possiblity about sev instruction to getting missed by other cores. 386 This is because of SoC Run Control block may not able to sample 387 the EVENTI(Sev) signals. 388 389 Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to 390 wake up A57 cores 391 392 Errata workaround uses Env variable "a009635_interval_val". It uses decimal 393 value. 394 - Default value of env variable is platform clock (MHz) 395 396 - User can modify default value by updating the env variable 397 setenv a009635_interval_val 600; saveenv; 398 It configure platform clock as 600 MHz 399 400 - Env variable as 0 signifies no workaround 401
README.qspi
1 QSPI Boot source support Overview 2 ------------------- 3 1. LS1043A 4 LS1043AQDS 5 2. LS2080A 6 LS2080AQDS 7 3. LS1012A 8 LS1012AQDS 9 LS1012ARDB 10 4. LS1046A 11 LS1046AQDS 12 LS1046ARDB 13 14 Booting from QSPI 15 ------------------- 16 Booting from QSPI requires two images, RCW and u-boot-dtb.bin. 17 The difference between QSPI boot RCW image and NOR boot image is the PBI 18 command sequence for setting the boot location pointer. It's should point 19 to the address for u-boot in QSPI flash. 20 21 RCW image should be written to the beginning of QSPI flash device. 22 Example of using u-boot command 23 24 => sf probe 0:0 25 SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB 26 => sf erase 0 +<size of rcw image> 27 SF: 65536 bytes @ 0x0 Erased: OK 28 => sf write <rcw image in memory> 0 <size of rcw image> 29 SF: 164 bytes @ 0x0 Written: OK 30 31 To get the QSPI image, build u-boot with QSPI config, for example, 32 <board_name>_qspi_defconfig. The image needed is u-boot-dtb.bin. 33 The u-boot image should be written to 0x10000(but 0x1000 for LS1043A, LS2080A). 34 35 => sf probe 0:0 36 SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB 37 => sf erase 10000 +<size of u-boot image> 38 SF: 589824 bytes @ 0x10000 Erased: OK 39 => sf write <u-boot image in memory> 10000 <size of u-boot image> 40 SF: 580966 bytes @ 0x10000 Written: OK 41 42 With these two images in QSPI flash device, the board can boot from QSPI. 43
README.soc
1 SoC overview 2 3 1. LS1043A 4 2. LS1088A 5 3. LS2080A 6 4. LS1012A 7 5. LS1046A 8 6. LS2088A 9 7. LS2081A 10 11 LS1043A 12 --------- 13 The LS1043A integrated multicore processor combines four ARM Cortex-A53 14 processor cores with datapath acceleration optimized for L2/3 packet 15 processing, single pass security offload and robust traffic management 16 and quality of service. 17 18 The LS1043A SoC includes the following function and features: 19 - Four 64-bit ARM Cortex-A53 CPUs 20 - 1 MB unified L2 Cache 21 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving 22 support 23 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the 24 the following functions: 25 - Packet parsing, classification, and distribution (FMan) 26 - Queue management for scheduling, packet sequencing, and congestion 27 management (QMan) 28 - Hardware buffer management for buffer allocation and de-allocation (BMan) 29 - Cryptography acceleration (SEC) 30 - Ethernet interfaces by FMan 31 - Up to 1 x XFI supporting 10G interface 32 - Up to 1 x QSGMII 33 - Up to 4 x SGMII supporting 1000Mbps 34 - Up to 2 x SGMII supporting 2500Mbps 35 - Up to 2 x RGMII supporting 1000Mbps 36 - High-speed peripheral interfaces 37 - Three PCIe 2.0 controllers, one supporting x4 operation 38 - One serial ATA (SATA 3.0) controllers 39 - Additional peripheral interfaces 40 - Three high-speed USB 3.0 controllers with integrated PHY 41 - Enhanced secure digital host controller (eSDXC/eMMC) 42 - Quad Serial Peripheral Interface (QSPI) Controller 43 - Serial peripheral interface (SPI) controller 44 - Four I2C controllers 45 - Two DUARTs 46 - Integrated flash controller supporting NAND and NOR flash 47 - QorIQ platform's trust architecture 2.1 48 49 LS1088A 50 -------- 51 The QorIQ LS1088A processor is built on the Layerscape 52 architecture combining eight ARM A53 processor cores 53 with advanced, high-performance datapath acceleration 54 and networks, peripheral interfaces required for 55 networking, wireless infrastructure, and general-purpose 56 embedded applications. 57 58 LS1088A is compliant with the Layerscape Chassis Generation 3. 59 60 Features summary: 61 - 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs 62 - Cores are in 2 cluster of 4-cores each 63 - 1MB L2 - Cache per cluster 64 - Cache coherent interconnect (CCI-400) 65 - 1 64-bit DDR4 SDRAM memory controller with ECC 66 - Data path acceleration architecture 2.0 (DPAA2) 67 - 4-Lane 10GHz SerDes comprising of WRIOP 68 - 4-Lane 10GHz SerDes comprising of PCI, SATA, uQE(TDM/HLDC/UART) 69 - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs 70 - QSPI, SPI, IFC2.0 supporting NAND, NOR flash 71 - 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc 72 - 2 DUARTs 73 - 4 I2C, GPIO 74 - Thermal monitor unit(TMU) 75 - 4 Flextimers and 1 generic timer 76 - Support for hardware virtualization and partitioning enforcement 77 - QorIQ platform's trust architecture 3.0 78 - Service processor (SP) provides pre-boot initialization and secure-boot 79 capabilities 80 81 LS2080A 82 -------- 83 The LS2080A integrated multicore processor combines eight ARM Cortex-A57 84 processor cores with high-performance data path acceleration logic and network 85 and peripheral bus interfaces required for networking, telecom/datacom, 86 wireless infrastructure, and mil/aerospace applications. 87 88 The LS2080A SoC includes the following function and features: 89 90 - Eight 64-bit ARM Cortex-A57 CPUs 91 - 1 MB platform cache with ECC 92 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support 93 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by 94 the AIOP 95 - Data path acceleration architecture (DPAA2) incorporating acceleration for 96 the following functions: 97 - Packet parsing, classification, and distribution (WRIOP) 98 - Queue and Hardware buffer management for scheduling, packet sequencing, and 99 congestion management, buffer allocation and de-allocation (QBMan) 100 - Cryptography acceleration (SEC) at up to 10 Gbps 101 - RegEx pattern matching acceleration (PME) at up to 10 Gbps 102 - Decompression/compression acceleration (DCE) at up to 20 Gbps 103 - Accelerated I/O processing (AIOP) at up to 20 Gbps 104 - QDMA engine 105 - 16 SerDes lanes at up to 10.3125 GHz 106 - Ethernet interfaces 107 - Up to eight 10 Gbps Ethernet MACs 108 - Up to eight 1 / 2.5 Gbps Ethernet MACs 109 - High-speed peripheral interfaces 110 - Four PCIe 3.0 controllers, one supporting SR-IOV 111 - Additional peripheral interfaces 112 - Two serial ATA (SATA 3.0) controllers 113 - Two high-speed USB 3.0 controllers with integrated PHY 114 - Enhanced secure digital host controller (eSDXC/eMMC) 115 - Serial peripheral interface (SPI) controller 116 - Quad Serial Peripheral Interface (QSPI) Controller 117 - Four I2C controllers 118 - Two DUARTs 119 - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash 120 - Support for hardware virtualization and partitioning enforcement 121 - QorIQ platform's trust architecture 3.0 122 - Service processor (SP) provides pre-boot initialization and secure-boot 123 capabilities 124 125 LS1012A 126 -------- 127 The LS1012A features an advanced 64-bit ARM v8 Cortex- 128 A53 processor, with 32 KB of parity protected L1-I cache, 129 32 KB of ECC protected L1-D cache, as well as 256 KB of 130 ECC protected L2 cache. 131 132 The LS1012A SoC includes the following function and features: 133 - One 64-bit ARM v8 Cortex-A53 core with the following capabilities: 134 - ARM v8 cryptography extensions 135 - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports 136 16-/8-bit operation (no ECC support) 137 - ARM core-link CCI-400 cache coherent interconnect 138 - Packet Forwarding Engine (PFE) 139 - Cryptography acceleration (SEC) 140 - Ethernet interfaces supported by PFE: 141 - One Configurable x3 SerDes: 142 Two Serdes PLLs supported for usage by any SerDes data lane 143 Support for up to 6 GBaud operation 144 - High-speed peripheral interfaces: 145 - One PCI Express Gen2 controller, supporting x1 operation 146 - One serial ATA (SATA Gen 3.0) controller 147 - One USB 3.0/2.0 controller with integrated PHY 148 - One USB 2.0 controller with ULPI interface. . 149 - Additional peripheral interfaces: 150 - One quad serial peripheral interface (QuadSPI) controller 151 - One serial peripheral interface (SPI) controller 152 - Two enhanced secure digital host controllers 153 - Two I2C controllers 154 - One 16550 compliant DUART (two UART interfaces) 155 - Two general purpose IOs (GPIO) 156 - Two FlexTimers 157 - Five synchronous audio interfaces (SAI) 158 - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading 159 - Single-source clocking solution enabling generation of core, platform, 160 DDR, SerDes, and USB clocks from a single external crystal and internal 161 crystaloscillator 162 - Thermal monitor unit (TMU) with +/- 3C accuracy 163 - Two WatchDog timers 164 - ARM generic timer 165 - QorIQ platform's trust architecture 2.1 166 167 LS1046A 168 -------- 169 The LS1046A integrated multicore processor combines four ARM Cortex-A72 170 processor cores with datapath acceleration optimized for L2/3 packet 171 processing, single pass security offload and robust traffic management 172 and quality of service. 173 174 The LS1046A SoC includes the following function and features: 175 - Four 64-bit ARM Cortex-A72 CPUs 176 - 2 MB unified L2 Cache 177 - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving 178 support 179 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the 180 the following functions: 181 - Packet parsing, classification, and distribution (FMan) 182 - Queue management for scheduling, packet sequencing, and congestion 183 management (QMan) 184 - Hardware buffer management for buffer allocation and de-allocation (BMan) 185 - Cryptography acceleration (SEC) 186 - Two Configurable x4 SerDes 187 - Two PLLs per four-lane SerDes 188 - Support for 10G operation 189 - Ethernet interfaces by FMan 190 - Up to 2 x XFI supporting 10G interface (MAC 9, 10) 191 - Up to 1 x QSGMII (MAC 5, 6, 10, 1) 192 - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) 193 - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10) 194 - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4) 195 - High-speed peripheral interfaces 196 - Three PCIe 3.0 controllers, one supporting x4 operation 197 - One serial ATA (SATA 3.0) controllers 198 - Additional peripheral interfaces 199 - Three high-speed USB 3.0 controllers with integrated PHY 200 - Enhanced secure digital host controller (eSDXC/eMMC) 201 - Quad Serial Peripheral Interface (QSPI) Controller 202 - Serial peripheral interface (SPI) controller 203 - Four I2C controllers 204 - Two DUARTs 205 - Integrated flash controller (IFC) supporting NAND and NOR flash 206 - QorIQ platform's trust architecture 2.1 207 208 LS2088A 209 -------- 210 The LS2088A integrated multicore processor combines eight ARM Cortex-A72 211 processor cores with high-performance data path acceleration logic and network 212 and peripheral bus interfaces required for networking, telecom/datacom, 213 wireless infrastructure, and mil/aerospace applications. 214 215 The LS2088A SoC includes the following function and features: 216 217 - Eight 64-bit ARM Cortex-A72 CPUs 218 - 1 MB platform cache with ECC 219 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support 220 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by 221 the AIOP 222 - Data path acceleration architecture (DPAA2) incorporating acceleration for 223 the following functions: 224 - Packet parsing, classification, and distribution (WRIOP) 225 - Queue and Hardware buffer management for scheduling, packet sequencing, and 226 congestion management, buffer allocation and de-allocation (QBMan) 227 - Cryptography acceleration (SEC) at up to 10 Gbps 228 - RegEx pattern matching acceleration (PME) at up to 10 Gbps 229 - Decompression/compression acceleration (DCE) at up to 20 Gbps 230 - Accelerated I/O processing (AIOP) at up to 20 Gbps 231 - QDMA engine 232 - 16 SerDes lanes at up to 10.3125 GHz 233 - Ethernet interfaces 234 - Up to eight 10 Gbps Ethernet MACs 235 - Up to eight 1 / 2.5 Gbps Ethernet MACs 236 - High-speed peripheral interfaces 237 - Four PCIe 3.0 controllers, one supporting SR-IOV 238 - Additional peripheral interfaces 239 - Two serial ATA (SATA 3.0) controllers 240 - Two high-speed USB 3.0 controllers with integrated PHY 241 - Enhanced secure digital host controller (eSDXC/eMMC) 242 - Serial peripheral interface (SPI) controller 243 - Quad Serial Peripheral Interface (QSPI) Controller 244 - Four I2C controllers 245 - Two DUARTs 246 - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash 247 - Support for hardware virtualization and partitioning enforcement 248 - QorIQ platform's trust architecture 3.0 249 - Service processor (SP) provides pre-boot initialization and secure-boot 250 capabilities 251 252 LS2088A SoC has 3 more similar SoC personalities 253 1)LS2048A, few difference w.r.t. LS2088A: 254 a) Four 64-bit ARM v8 Cortex-A72 CPUs 255 256 2)LS2084A, few difference w.r.t. LS2088A: 257 a) No AIOP 258 b) No 32-bit DDR3 SDRAM memory 259 c) 5 * 1/10G + 5 *1G WRIOP 260 d) No L2 switch 261 262 3)LS2044A, few difference w.r.t. LS2084A: 263 a) Four 64-bit ARM v8 Cortex-A72 CPUs 264 265 LS2081A 266 -------- 267 LS2081A is 40-pin derivative of LS2084A. 268 So feature-wise it is same as LS2084A. 269 Refer to LS2084A(LS2088A) section above for details. 270 271 It has one more similar SoC personality 272 1)LS2041A, few difference w.r.t. LS2081A: 273 a) Four 64-bit ARM v8 Cortex-A72 CPUs 274
