1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/processor.h> 8 #include <asm/mmu.h> 9 #include <asm/cache.h> 10 #include <asm/immap_85xx.h> 11 #include <asm/io.h> 12 #include <miiphy.h> 13 #include <linux/libfdt.h> 14 #include <fdt_support.h> 15 #include <fsl_mdio.h> 16 #include <tsec.h> 17 #include <mmc.h> 18 #include <netdev.h> 19 #include <fsl_ifc.h> 20 #include <hwconfig.h> 21 #include <i2c.h> 22 #include <fsl_ddr_sdram.h> 23 #include <jffs2/load_kernel.h> 24 #include <mtd_node.h> 25 #include <flash.h> 26 27 #ifdef CONFIG_PCI 28 #include <pci.h> 29 #include <asm/fsl_pci.h> 30 #endif 31 32 #include "../common/qixis.h" 33 DECLARE_GLOBAL_DATA_PTR; 34 35 36 int board_early_init_f(void) 37 { 38 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; 39 40 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); 41 42 return 0; 43 } 44 45 void board_config_serdes_mux(void) 46 { 47 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 48 u32 pordevsr = in_be32(&gur->pordevsr); 49 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 50 MPC85xx_PORDEVSR_IO_SEL_SHIFT; 51 52 switch (srds_cfg) { 53 /* PEX(1) PEX(2) CPRI 2 CPRI 1 */ 54 case 1: 55 case 2: 56 case 3: 57 case 4: 58 case 5: 59 case 22: 60 case 23: 61 case 24: 62 case 25: 63 case 26: 64 QIXIS_WRITE_I2C(brdcfg[4], 0x03); 65 break; 66 67 /* PEX(1) PEX(2) SGMII1 CPRI 1 */ 68 case 6: 69 case 7: 70 case 8: 71 case 9: 72 case 10: 73 case 27: 74 case 28: 75 case 29: 76 case 30: 77 case 31: 78 QIXIS_WRITE_I2C(brdcfg[4], 0x01); 79 break; 80 81 /* PEX(1) PEX(2) SGMII1 SGMII2 */ 82 case 11: 83 case 32: 84 QIXIS_WRITE_I2C(brdcfg[4], 0x00); 85 break; 86 87 /* PEX(1) SGMII2 CPRI 2 CPRI 1 */ 88 case 12: 89 case 13: 90 case 14: 91 case 15: 92 case 16: 93 case 33: 94 case 34: 95 case 35: 96 case 36: 97 case 37: 98 QIXIS_WRITE_I2C(brdcfg[4], 0x07); 99 break; 100 101 /* PEX(1) SGMII2 SGMII1 CPRI 1 */ 102 case 17: 103 case 18: 104 case 19: 105 case 20: 106 case 21: 107 case 38: 108 case 39: 109 case 40: 110 case 41: 111 case 42: 112 QIXIS_WRITE_I2C(brdcfg[4], 0x05); 113 break; 114 115 /* SGMII1 SGMII2 CPRI 2 CPRI 1 */ 116 case 43: 117 case 44: 118 case 45: 119 case 46: 120 case 47: 121 QIXIS_WRITE_I2C(brdcfg[4], 0x0F); 122 break; 123 124 125 default: 126 break; 127 } 128 } 129 130 /* Configure DSP DDR controller */ 131 void dsp_ddr_configure(void) 132 { 133 /* 134 *There are separate DDR-controllers for DSP and PowerPC side DDR. 135 *copy the ddr controller settings from PowerPC side DDR controller 136 *to the DSP DDR controller as connected DDR memories are similar. 137 */ 138 struct ccsr_ddr __iomem *pa_ddr = 139 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; 140 struct ccsr_ddr temp_ddr; 141 struct ccsr_ddr __iomem *dsp_ddr = 142 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; 143 144 memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr)); 145 temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS; 146 temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN; 147 memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr)); 148 dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN; 149 } 150 151 int board_early_init_r(void) 152 { 153 #ifdef CONFIG_MTD_NOR_FLASH 154 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 155 int flash_esel = find_tlb_idx((void *)flashbase, 1); 156 157 /* 158 * Remap Boot flash region to caching-inhibited 159 * so that flash can be erased properly. 160 */ 161 162 /* Flush d-cache and invalidate i-cache of any FLASH data */ 163 flush_dcache(); 164 invalidate_icache(); 165 166 if (flash_esel == -1) { 167 /* very unlikely unless something is messed up */ 168 puts("Error: Could not find TLB for FLASH BASE\n"); 169 flash_esel = 2; /* give our best effort to continue */ 170 } else { 171 /* invalidate existing TLB entry for flash */ 172 disable_tlb(flash_esel); 173 } 174 175 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 176 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 177 0, flash_esel, BOOKE_PAGESZ_64M, 1); 178 179 set_tlb(1, flashbase + 0x4000000, 180 CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, 181 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 182 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); 183 #endif 184 board_config_serdes_mux(); 185 dsp_ddr_configure(); 186 return 0; 187 } 188 189 #ifdef CONFIG_PCI 190 void pci_init_board(void) 191 { 192 fsl_pcie_init_board(0); 193 } 194 #endif /* ifdef CONFIG_PCI */ 195 196 int checkboard(void) 197 { 198 struct cpu_type *cpu; 199 u8 sw; 200 201 cpu = gd->arch.cpu; 202 printf("Board: %sQDS\n", cpu->name); 203 204 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n", 205 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); 206 207 sw = QIXIS_READ(brdcfg[0]); 208 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 209 210 printf("IFC chip select:"); 211 switch (sw) { 212 case 0: 213 printf("NOR\n"); 214 break; 215 case 2: 216 printf("Promjet\n"); 217 break; 218 case 4: 219 printf("NAND\n"); 220 break; 221 default: 222 printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 223 break; 224 } 225 226 return 0; 227 } 228 229 int board_eth_init(bd_t *bis) 230 { 231 #ifdef CONFIG_TSEC_ENET 232 struct fsl_pq_mdio_info mdio_info; 233 struct tsec_info_struct tsec_info[4]; 234 int num = 0; 235 236 #ifdef CONFIG_TSEC1 237 SET_STD_TSEC_INFO(tsec_info[num], 1); 238 num++; 239 240 #endif 241 242 #ifdef CONFIG_TSEC2 243 SET_STD_TSEC_INFO(tsec_info[num], 2); 244 num++; 245 #endif 246 247 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; 248 mdio_info.name = DEFAULT_MII_NAME; 249 250 fsl_pq_mdio_init(bis, &mdio_info); 251 tsec_eth_init(bis, tsec_info, num); 252 #endif 253 254 #ifdef CONFIG_PCI 255 pci_eth_init(bis); 256 #endif 257 258 return 0; 259 } 260 261 #define USBMUX_SEL_MASK 0xc0 262 #define USBMUX_SEL_UART2 0xc0 263 #define USBMUX_SEL_USB 0x40 264 #define SPIMUX_SEL_UART3 0x80 265 #define GPS_MUX_SEL_GPS 0x40 266 267 #define TSEC_1588_CLKIN_MASK 0x03 268 #define CON_XCVR_REF_CLK 0x00 269 270 int misc_init_r(void) 271 { 272 u8 val; 273 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 274 u32 porbmsr = in_be32(&gur->porbmsr); 275 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; 276 277 /*Configure 1588 clock-in source from RF Card*/ 278 val = QIXIS_READ_I2C(brdcfg[5]); 279 QIXIS_WRITE_I2C(brdcfg[5], 280 (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK); 281 282 if (hwconfig("uart2") && hwconfig("usb1")) { 283 printf("UART2 and USB cannot work together on the board\n"); 284 printf("Remove one from hwconfig and reset\n"); 285 } else { 286 if (hwconfig("uart2")) { 287 val = QIXIS_READ_I2C(brdcfg[5]); 288 QIXIS_WRITE_I2C(brdcfg[5], 289 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2); 290 clrbits_be32(&gur->pmuxcr3, 291 MPC85xx_PMUXCR3_USB_SEL_MASK); 292 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL); 293 } else { 294 /* By default USB should be selected. 295 * Programming FPGA to select USB. */ 296 val = QIXIS_READ_I2C(brdcfg[5]); 297 QIXIS_WRITE_I2C(brdcfg[5], 298 (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB); 299 } 300 301 } 302 303 if (hwconfig("sim")) { 304 if (romloc == PORBMSR_ROMLOC_NAND_2K || 305 romloc == PORBMSR_ROMLOC_NOR || 306 romloc == PORBMSR_ROMLOC_SPI) { 307 308 val = QIXIS_READ_I2C(brdcfg[3]); 309 QIXIS_WRITE_I2C(brdcfg[3], val|0x10); 310 clrbits_be32(&gur->pmuxcr, 311 MPC85xx_PMUXCR0_SIM_SEL_MASK); 312 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL); 313 } 314 } 315 316 if (hwconfig("uart3")) { 317 if (romloc == PORBMSR_ROMLOC_NAND_2K || 318 romloc == PORBMSR_ROMLOC_NOR || 319 romloc == PORBMSR_ROMLOC_SDHC) { 320 321 /* UART3 and SPI1 (Flashes) are muxed together */ 322 val = QIXIS_READ_I2C(brdcfg[3]); 323 QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3)); 324 clrbits_be32(&gur->pmuxcr3, 325 MPC85xx_PMUXCR3_UART3_SEL_MASK); 326 setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL); 327 328 /* MUX to select UART3 connection to J24 header 329 * or to GPS */ 330 val = QIXIS_READ_I2C(brdcfg[6]); 331 if (hwconfig("gps")) 332 QIXIS_WRITE_I2C(brdcfg[6], 333 (val | GPS_MUX_SEL_GPS)); 334 else 335 QIXIS_WRITE_I2C(brdcfg[6], 336 (val & ~(GPS_MUX_SEL_GPS))); 337 } 338 } 339 return 0; 340 } 341 342 void fdt_del_node_compat(void *blob, const char *compatible) 343 { 344 int err; 345 int off = fdt_node_offset_by_compatible(blob, -1, compatible); 346 if (off < 0) { 347 printf("WARNING: could not find compatible node %s: %s.\n", 348 compatible, fdt_strerror(off)); 349 return; 350 } 351 err = fdt_del_node(blob, off); 352 if (err < 0) { 353 printf("WARNING: could not remove %s: %s.\n", 354 compatible, fdt_strerror(err)); 355 } 356 } 357 358 #if defined(CONFIG_OF_BOARD_SETUP) 359 #ifdef CONFIG_FDT_FIXUP_PARTITIONS 360 struct node_info nodes[] = { 361 { "cfi-flash", MTD_DEV_TYPE_NOR, }, 362 { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, 363 }; 364 #endif 365 int ft_board_setup(void *blob, bd_t *bd) 366 { 367 phys_addr_t base; 368 phys_size_t size; 369 370 ft_cpu_setup(blob, bd); 371 372 base = env_get_bootm_low(); 373 size = env_get_bootm_size(); 374 375 #if defined(CONFIG_PCI) 376 FT_FSL_PCI_SETUP; 377 #endif 378 379 fdt_fixup_memory(blob, (u64)base, (u64)size); 380 #ifdef CONFIG_FDT_FIXUP_PARTITIONS 381 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 382 #endif 383 384 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 385 u32 porbmsr = in_be32(&gur->porbmsr); 386 u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; 387 388 if (!(hwconfig("uart2") && hwconfig("usb1"))) { 389 /* If uart2 is there in hwconfig remove usb node from 390 * device tree */ 391 392 if (hwconfig("uart2")) { 393 /* remove dts usb node */ 394 fdt_del_node_compat(blob, "fsl-usb2-dr"); 395 } else { 396 fsl_fdt_fixup_dr_usb(blob, bd); 397 fdt_del_node_and_alias(blob, "serial2"); 398 } 399 } 400 401 if (hwconfig("uart3")) { 402 if (romloc == PORBMSR_ROMLOC_NAND_2K || 403 romloc == PORBMSR_ROMLOC_NOR || 404 romloc == PORBMSR_ROMLOC_SDHC) 405 /* Delete SPI node from the device tree */ 406 fdt_del_node_and_alias(blob, "spi1"); 407 } else 408 fdt_del_node_and_alias(blob, "serial3"); 409 410 if (hwconfig("sim")) { 411 if (romloc == PORBMSR_ROMLOC_NAND_2K || 412 romloc == PORBMSR_ROMLOC_NOR || 413 romloc == PORBMSR_ROMLOC_SPI) { 414 415 /* remove dts sdhc node */ 416 fdt_del_node_compat(blob, "fsl,esdhc"); 417 } else if (romloc == PORBMSR_ROMLOC_SDHC) { 418 419 /* remove dts sim node */ 420 fdt_del_node_compat(blob, "fsl,sim-v1.0"); 421 printf("SIM & SDHC can't work together on the board"); 422 printf("\nRemove sim from hwconfig and reset\n"); 423 } 424 } 425 426 return 0; 427 } 428 #endif 429
