1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 */ 5 6 #include <asm/arch/clock.h> 7 #include <asm/arch/iomux.h> 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/crm_regs.h> 10 #include <asm/arch/mx6ul_pins.h> 11 #include <asm/arch/mx6-pins.h> 12 #include <asm/arch/sys_proto.h> 13 #include <asm/gpio.h> 14 #include <asm/mach-imx/iomux-v3.h> 15 #include <asm/mach-imx/boot_mode.h> 16 #include <asm/mach-imx/mxc_i2c.h> 17 #include <asm/io.h> 18 #include <common.h> 19 #include <fsl_esdhc.h> 20 #include <i2c.h> 21 #include <miiphy.h> 22 #include <linux/sizes.h> 23 #include <mmc.h> 24 #include <netdev.h> 25 #include <power/pmic.h> 26 #include <power/pfuze3000_pmic.h> 27 #include "../common/pfuze.h" 28 #include <usb.h> 29 #include <usb/ehci-ci.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 34 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 35 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 36 37 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 38 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 39 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 40 41 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 42 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ 43 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 44 45 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 46 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 47 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 48 PAD_CTL_ODE) 49 50 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 51 PAD_CTL_SPEED_HIGH | \ 52 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 53 54 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 55 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) 56 57 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 58 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) 59 60 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 61 62 #define IOX_SDI IMX_GPIO_NR(5, 10) 63 #define IOX_STCP IMX_GPIO_NR(5, 7) 64 #define IOX_SHCP IMX_GPIO_NR(5, 11) 65 #define IOX_OE IMX_GPIO_NR(5, 8) 66 67 static iomux_v3_cfg_t const iox_pads[] = { 68 /* IOX_SDI */ 69 MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 70 /* IOX_SHCP */ 71 MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 72 /* IOX_STCP */ 73 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 74 /* IOX_nOE */ 75 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 76 }; 77 78 /* 79 * HDMI_nRST --> Q0 80 * ENET1_nRST --> Q1 81 * ENET2_nRST --> Q2 82 * CAN1_2_STBY --> Q3 83 * BT_nPWD --> Q4 84 * CSI_RST --> Q5 85 * CSI_PWDN --> Q6 86 * LCD_nPWREN --> Q7 87 */ 88 enum qn { 89 HDMI_NRST, 90 ENET1_NRST, 91 ENET2_NRST, 92 CAN1_2_STBY, 93 BT_NPWD, 94 CSI_RST, 95 CSI_PWDN, 96 LCD_NPWREN, 97 }; 98 99 enum qn_func { 100 qn_reset, 101 qn_enable, 102 qn_disable, 103 }; 104 105 enum qn_level { 106 qn_low = 0, 107 qn_high = 1, 108 }; 109 110 static enum qn_level seq[3][2] = { 111 {0, 1}, {1, 1}, {0, 0} 112 }; 113 114 static enum qn_func qn_output[8] = { 115 qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, 116 qn_disable, qn_disable 117 }; 118 119 static void iox74lv_init(void) 120 { 121 int i; 122 123 gpio_direction_output(IOX_OE, 0); 124 125 for (i = 7; i >= 0; i--) { 126 gpio_direction_output(IOX_SHCP, 0); 127 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 128 udelay(500); 129 gpio_direction_output(IOX_SHCP, 1); 130 udelay(500); 131 } 132 133 gpio_direction_output(IOX_STCP, 0); 134 udelay(500); 135 /* 136 * shift register will be output to pins 137 */ 138 gpio_direction_output(IOX_STCP, 1); 139 140 for (i = 7; i >= 0; i--) { 141 gpio_direction_output(IOX_SHCP, 0); 142 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 143 udelay(500); 144 gpio_direction_output(IOX_SHCP, 1); 145 udelay(500); 146 } 147 gpio_direction_output(IOX_STCP, 0); 148 udelay(500); 149 /* 150 * shift register will be output to pins 151 */ 152 gpio_direction_output(IOX_STCP, 1); 153 }; 154 155 #ifdef CONFIG_SYS_I2C_MXC 156 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 157 /* I2C1 for PMIC and EEPROM */ 158 static struct i2c_pads_info i2c_pad_info1 = { 159 .scl = { 160 .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, 161 .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, 162 .gp = IMX_GPIO_NR(1, 28), 163 }, 164 .sda = { 165 .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, 166 .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, 167 .gp = IMX_GPIO_NR(1, 29), 168 }, 169 }; 170 171 #ifdef CONFIG_POWER 172 #define I2C_PMIC 0 173 int power_init_board(void) 174 { 175 if (is_mx6ul_9x9_evk()) { 176 struct pmic *pfuze; 177 int ret; 178 unsigned int reg, rev_id; 179 180 ret = power_pfuze3000_init(I2C_PMIC); 181 if (ret) 182 return ret; 183 184 pfuze = pmic_get("PFUZE3000"); 185 ret = pmic_probe(pfuze); 186 if (ret) 187 return ret; 188 189 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); 190 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); 191 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", 192 reg, rev_id); 193 194 /* disable Low Power Mode during standby mode */ 195 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); 196 197 /* SW1B step ramp up time from 2us to 4us/25mV */ 198 reg = 0x40; 199 pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); 200 201 /* SW1B mode to APS/PFM */ 202 reg = 0xc; 203 pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); 204 205 /* SW1B standby voltage set to 0.975V */ 206 reg = 0xb; 207 pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); 208 } 209 210 return 0; 211 } 212 #endif 213 #endif 214 215 int dram_init(void) 216 { 217 gd->ram_size = imx_ddr_size(); 218 219 return 0; 220 } 221 222 static iomux_v3_cfg_t const uart1_pads[] = { 223 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 224 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 225 }; 226 227 #ifndef CONFIG_SPL_BUILD 228 static iomux_v3_cfg_t const usdhc1_pads[] = { 229 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 230 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 231 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 232 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 233 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 234 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 235 236 /* VSELECT */ 237 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), 238 /* CD */ 239 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 240 /* RST_B */ 241 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 242 }; 243 #endif 244 245 /* 246 * mx6ul_14x14_evk board default supports sd card. If want to use 247 * EMMC, need to do board rework for sd2. 248 * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support 249 * emmc, need to define this macro. 250 */ 251 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 252 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { 253 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 254 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 255 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 256 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 257 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 258 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 259 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 260 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 261 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 262 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 263 264 /* 265 * RST_B 266 */ 267 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 268 }; 269 #else 270 static iomux_v3_cfg_t const usdhc2_pads[] = { 271 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 272 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 273 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 274 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 275 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 276 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 277 }; 278 279 /* 280 * The evk board uses DAT3 to detect CD card plugin, 281 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. 282 */ 283 static iomux_v3_cfg_t const usdhc2_cd_pad = 284 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL); 285 286 static iomux_v3_cfg_t const usdhc2_dat3_pad = 287 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | 288 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL); 289 #endif 290 291 static void setup_iomux_uart(void) 292 { 293 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 294 } 295 296 #ifdef CONFIG_FSL_QSPI 297 298 #define QSPI_PAD_CTRL1 \ 299 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ 300 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) 301 302 static iomux_v3_cfg_t const quadspi_pads[] = { 303 MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 304 MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 305 MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 306 MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 307 MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 308 MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 309 }; 310 311 static int board_qspi_init(void) 312 { 313 /* Set the iomux */ 314 imx_iomux_v3_setup_multiple_pads(quadspi_pads, 315 ARRAY_SIZE(quadspi_pads)); 316 /* Set the clock */ 317 enable_qspi_clk(0); 318 319 return 0; 320 } 321 #endif 322 323 #ifdef CONFIG_FSL_ESDHC 324 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 325 {USDHC1_BASE_ADDR, 0, 4}, 326 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 327 {USDHC2_BASE_ADDR, 0, 8}, 328 #else 329 {USDHC2_BASE_ADDR, 0, 4}, 330 #endif 331 }; 332 333 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) 334 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) 335 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) 336 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) 337 338 int board_mmc_getcd(struct mmc *mmc) 339 { 340 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 341 int ret = 0; 342 343 switch (cfg->esdhc_base) { 344 case USDHC1_BASE_ADDR: 345 ret = !gpio_get_value(USDHC1_CD_GPIO); 346 break; 347 case USDHC2_BASE_ADDR: 348 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 349 ret = 1; 350 #else 351 imx_iomux_v3_setup_pad(usdhc2_cd_pad); 352 gpio_direction_input(USDHC2_CD_GPIO); 353 354 /* 355 * Since it is the DAT3 pin, this pin is pulled to 356 * low voltage if no card 357 */ 358 ret = gpio_get_value(USDHC2_CD_GPIO); 359 360 imx_iomux_v3_setup_pad(usdhc2_dat3_pad); 361 #endif 362 break; 363 } 364 365 return ret; 366 } 367 368 int board_mmc_init(bd_t *bis) 369 { 370 #ifdef CONFIG_SPL_BUILD 371 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 372 imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads, 373 ARRAY_SIZE(usdhc2_emmc_pads)); 374 #else 375 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 376 #endif 377 gpio_direction_output(USDHC2_PWR_GPIO, 0); 378 udelay(500); 379 gpio_direction_output(USDHC2_PWR_GPIO, 1); 380 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 381 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); 382 #else 383 int i, ret; 384 385 /* 386 * According to the board_mmc_init() the following map is done: 387 * (U-Boot device node) (Physical Port) 388 * mmc0 USDHC1 389 * mmc1 USDHC2 390 */ 391 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 392 switch (i) { 393 case 0: 394 imx_iomux_v3_setup_multiple_pads( 395 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 396 gpio_direction_input(USDHC1_CD_GPIO); 397 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 398 399 gpio_direction_output(USDHC1_PWR_GPIO, 0); 400 udelay(500); 401 gpio_direction_output(USDHC1_PWR_GPIO, 1); 402 break; 403 case 1: 404 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK) 405 imx_iomux_v3_setup_multiple_pads( 406 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); 407 #else 408 imx_iomux_v3_setup_multiple_pads( 409 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 410 #endif 411 gpio_direction_output(USDHC2_PWR_GPIO, 0); 412 udelay(500); 413 gpio_direction_output(USDHC2_PWR_GPIO, 1); 414 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 415 break; 416 default: 417 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); 418 return -EINVAL; 419 } 420 421 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 422 if (ret) { 423 printf("Warning: failed to initialize mmc dev %d\n", i); 424 return ret; 425 } 426 } 427 #endif 428 return 0; 429 } 430 #endif 431 432 #ifdef CONFIG_USB_EHCI_MX6 433 #define USB_OTHERREGS_OFFSET 0x800 434 #define UCTRL_PWR_POL (1 << 9) 435 436 static iomux_v3_cfg_t const usb_otg_pads[] = { 437 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), 438 }; 439 440 /* At default the 3v3 enables the MIC2026 for VBUS power */ 441 static void setup_usb(void) 442 { 443 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 444 ARRAY_SIZE(usb_otg_pads)); 445 } 446 447 int board_usb_phy_mode(int port) 448 { 449 if (port == 1) 450 return USB_INIT_HOST; 451 else 452 return usb_phy_mode(port); 453 } 454 455 int board_ehci_hcd_init(int port) 456 { 457 u32 *usbnc_usb_ctrl; 458 459 if (port > 1) 460 return -EINVAL; 461 462 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 463 port * 4); 464 465 /* Set Power polarity */ 466 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 467 468 return 0; 469 } 470 #endif 471 472 #ifdef CONFIG_FEC_MXC 473 /* 474 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only 475 * be used for ENET1 or ENET2, cannot be used for both. 476 */ 477 static iomux_v3_cfg_t const fec1_pads[] = { 478 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 479 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 480 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 481 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 482 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 483 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 484 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 485 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 486 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 487 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 488 }; 489 490 static iomux_v3_cfg_t const fec2_pads[] = { 491 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 492 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 493 494 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 495 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 496 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 497 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 498 499 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 500 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 501 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 502 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 503 }; 504 505 static void setup_iomux_fec(int fec_id) 506 { 507 if (fec_id == 0) 508 imx_iomux_v3_setup_multiple_pads(fec1_pads, 509 ARRAY_SIZE(fec1_pads)); 510 else 511 imx_iomux_v3_setup_multiple_pads(fec2_pads, 512 ARRAY_SIZE(fec2_pads)); 513 } 514 515 int board_eth_init(bd_t *bis) 516 { 517 setup_iomux_fec(CONFIG_FEC_ENET_DEV); 518 519 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, 520 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 521 } 522 523 static int setup_fec(int fec_id) 524 { 525 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 526 int ret; 527 528 if (fec_id == 0) { 529 /* 530 * Use 50M anatop loopback REF_CLK1 for ENET1, 531 * clear gpr1[13], set gpr1[17]. 532 */ 533 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 534 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); 535 } else { 536 /* 537 * Use 50M anatop loopback REF_CLK2 for ENET2, 538 * clear gpr1[14], set gpr1[18]. 539 */ 540 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 541 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); 542 } 543 544 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); 545 if (ret) 546 return ret; 547 548 enable_enet_clk(1); 549 550 return 0; 551 } 552 553 int board_phy_config(struct phy_device *phydev) 554 { 555 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); 556 557 if (phydev->drv->config) 558 phydev->drv->config(phydev); 559 560 return 0; 561 } 562 #endif 563 564 #ifdef CONFIG_VIDEO_MXS 565 static iomux_v3_cfg_t const lcd_pads[] = { 566 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 567 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 568 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 569 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 570 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), 571 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), 572 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), 573 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), 574 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), 575 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), 576 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), 577 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), 578 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), 579 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), 580 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 581 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 582 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 583 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 584 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 585 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 586 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 587 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 588 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 589 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 590 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 591 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 592 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 593 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 594 595 /* LCD_RST */ 596 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 597 598 /* Use GPIO for Brightness adjustment, duty cycle = period. */ 599 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 600 }; 601 602 static int setup_lcd(void) 603 { 604 enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); 605 606 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 607 608 /* Reset the LCD */ 609 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); 610 udelay(500); 611 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); 612 613 /* Set Brightness to high */ 614 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); 615 616 return 0; 617 } 618 #endif 619 620 int board_early_init_f(void) 621 { 622 setup_iomux_uart(); 623 624 return 0; 625 } 626 627 int board_init(void) 628 { 629 /* Address of boot parameters */ 630 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 631 632 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); 633 634 iox74lv_init(); 635 636 #ifdef CONFIG_SYS_I2C_MXC 637 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 638 #endif 639 640 #ifdef CONFIG_FEC_MXC 641 setup_fec(CONFIG_FEC_ENET_DEV); 642 #endif 643 644 #ifdef CONFIG_USB_EHCI_MX6 645 setup_usb(); 646 #endif 647 648 #ifdef CONFIG_FSL_QSPI 649 board_qspi_init(); 650 #endif 651 652 #ifdef CONFIG_VIDEO_MXS 653 setup_lcd(); 654 #endif 655 656 return 0; 657 } 658 659 #ifdef CONFIG_CMD_BMODE 660 static const struct boot_mode board_boot_modes[] = { 661 /* 4 bit bus width */ 662 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, 663 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 664 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, 665 {NULL, 0}, 666 }; 667 #endif 668 669 int board_late_init(void) 670 { 671 #ifdef CONFIG_CMD_BMODE 672 add_board_boot_modes(board_boot_modes); 673 #endif 674 675 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 676 env_set("board_name", "EVK"); 677 678 if (is_mx6ul_9x9_evk()) 679 env_set("board_rev", "9X9"); 680 else 681 env_set("board_rev", "14X14"); 682 #endif 683 684 return 0; 685 } 686 687 int checkboard(void) 688 { 689 if (is_mx6ul_9x9_evk()) 690 puts("Board: MX6UL 9x9 EVK\n"); 691 else 692 puts("Board: MX6UL 14x14 EVK\n"); 693 694 return 0; 695 } 696 697 #ifdef CONFIG_SPL_BUILD 698 #include <linux/libfdt.h> 699 #include <spl.h> 700 #include <asm/arch/mx6-ddr.h> 701 702 703 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 704 .grp_addds = 0x00000030, 705 .grp_ddrmode_ctl = 0x00020000, 706 .grp_b0ds = 0x00000030, 707 .grp_ctlds = 0x00000030, 708 .grp_b1ds = 0x00000030, 709 .grp_ddrpke = 0x00000000, 710 .grp_ddrmode = 0x00020000, 711 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK 712 .grp_ddr_type = 0x00080000, 713 #else 714 .grp_ddr_type = 0x000c0000, 715 #endif 716 }; 717 718 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK 719 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 720 .dram_dqm0 = 0x00000030, 721 .dram_dqm1 = 0x00000030, 722 .dram_ras = 0x00000030, 723 .dram_cas = 0x00000030, 724 .dram_odt0 = 0x00000000, 725 .dram_odt1 = 0x00000000, 726 .dram_sdba2 = 0x00000000, 727 .dram_sdclk_0 = 0x00000030, 728 .dram_sdqs0 = 0x00003030, 729 .dram_sdqs1 = 0x00003030, 730 .dram_reset = 0x00000030, 731 }; 732 733 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 734 .p0_mpwldectrl0 = 0x00000000, 735 .p0_mpdgctrl0 = 0x20000000, 736 .p0_mprddlctl = 0x4040484f, 737 .p0_mpwrdlctl = 0x40405247, 738 .mpzqlp2ctl = 0x1b4700c7, 739 }; 740 741 static struct mx6_lpddr2_cfg mem_ddr = { 742 .mem_speed = 800, 743 .density = 2, 744 .width = 16, 745 .banks = 4, 746 .rowaddr = 14, 747 .coladdr = 10, 748 .trcd_lp = 1500, 749 .trppb_lp = 1500, 750 .trpab_lp = 2000, 751 .trasmin = 4250, 752 }; 753 754 struct mx6_ddr_sysinfo ddr_sysinfo = { 755 .dsize = 0, 756 .cs_density = 18, 757 .ncs = 1, 758 .cs1_mirror = 0, 759 .walat = 0, 760 .ralat = 5, 761 .mif3_mode = 3, 762 .bi_on = 1, 763 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ 764 .rtt_nom = 0, 765 .sde_to_rst = 0, /* LPDDR2 does not need this field */ 766 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ 767 .ddr_type = DDR_TYPE_LPDDR2, 768 .refsel = 0, /* Refresh cycles at 64KHz */ 769 .refr = 3, /* 4 refresh commands per refresh cycle */ 770 }; 771 772 #else 773 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 774 .dram_dqm0 = 0x00000030, 775 .dram_dqm1 = 0x00000030, 776 .dram_ras = 0x00000030, 777 .dram_cas = 0x00000030, 778 .dram_odt0 = 0x00000030, 779 .dram_odt1 = 0x00000030, 780 .dram_sdba2 = 0x00000000, 781 .dram_sdclk_0 = 0x00000030, 782 .dram_sdqs0 = 0x00000030, 783 .dram_sdqs1 = 0x00000030, 784 .dram_reset = 0x00000030, 785 }; 786 787 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 788 .p0_mpwldectrl0 = 0x00000000, 789 .p0_mpdgctrl0 = 0x41570155, 790 .p0_mprddlctl = 0x4040474A, 791 .p0_mpwrdlctl = 0x40405550, 792 }; 793 794 struct mx6_ddr_sysinfo ddr_sysinfo = { 795 .dsize = 0, 796 .cs_density = 20, 797 .ncs = 1, 798 .cs1_mirror = 0, 799 .rtt_wr = 2, 800 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 801 .walat = 0, /* Write additional latency */ 802 .ralat = 5, /* Read additional latency */ 803 .mif3_mode = 3, /* Command prediction working mode */ 804 .bi_on = 1, /* Bank interleaving enabled */ 805 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 806 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 807 .ddr_type = DDR_TYPE_DDR3, 808 .refsel = 0, /* Refresh cycles at 64KHz */ 809 .refr = 1, /* 2 refresh commands per refresh cycle */ 810 }; 811 812 static struct mx6_ddr3_cfg mem_ddr = { 813 .mem_speed = 800, 814 .density = 4, 815 .width = 16, 816 .banks = 8, 817 .rowaddr = 15, 818 .coladdr = 10, 819 .pagesz = 2, 820 .trcd = 1375, 821 .trcmin = 4875, 822 .trasmin = 3500, 823 }; 824 #endif 825 826 static void ccgr_init(void) 827 { 828 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 829 830 writel(0xFFFFFFFF, &ccm->CCGR0); 831 writel(0xFFFFFFFF, &ccm->CCGR1); 832 writel(0xFFFFFFFF, &ccm->CCGR2); 833 writel(0xFFFFFFFF, &ccm->CCGR3); 834 writel(0xFFFFFFFF, &ccm->CCGR4); 835 writel(0xFFFFFFFF, &ccm->CCGR5); 836 writel(0xFFFFFFFF, &ccm->CCGR6); 837 writel(0xFFFFFFFF, &ccm->CCGR7); 838 } 839 840 static void spl_dram_init(void) 841 { 842 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 843 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 844 } 845 846 void board_init_f(ulong dummy) 847 { 848 ccgr_init(); 849 850 /* setup AIPS and disable watchdog */ 851 arch_cpu_init(); 852 853 /* iomux and setup of i2c */ 854 board_early_init_f(); 855 856 /* setup GP timer */ 857 timer_init(); 858 859 /* UART clocks enabled and gd valid - init serial console */ 860 preloader_console_init(); 861 862 /* DDR initialization */ 863 spl_dram_init(); 864 865 /* Clear the BSS. */ 866 memset(__bss_start, 0, __bss_end - __bss_start); 867 868 /* load/boot image from boot device */ 869 board_init_r(NULL, 0); 870 } 871 #endif 872
