1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Thumb2InstrInfo.h" 15 #include "ARM.h" 16 #include "ARMConstantPoolValue.h" 17 #include "ARMAddressingModes.h" 18 #include "ARMMachineFunctionInfo.h" 19 #include "Thumb2InstrInfo.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineMemOperand.h" 23 #include "llvm/CodeGen/PseudoSourceValue.h" 24 #include "llvm/ADT/SmallVector.h" 25 #include "llvm/Support/CommandLine.h" 26 27 using namespace llvm; 28 29 static cl::opt<bool> 30 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden, 31 cl::desc("Use old-style Thumb2 if-conversion heuristics"), 32 cl::init(false)); 33 34 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI) 35 : ARMBaseInstrInfo(STI), RI(*this, STI) { 36 } 37 38 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const { 39 // FIXME 40 return 0; 41 } 42 43 void 44 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 45 MachineBasicBlock *NewDest) const { 46 MachineBasicBlock *MBB = Tail->getParent(); 47 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 48 if (!AFI->hasITBlocks()) { 49 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest); 50 return; 51 } 52 53 // If the first instruction of Tail is predicated, we may have to update 54 // the IT instruction. 55 unsigned PredReg = 0; 56 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg); 57 MachineBasicBlock::iterator MBBI = Tail; 58 if (CC != ARMCC::AL) 59 // Expecting at least the t2IT instruction before it. 60 --MBBI; 61 62 // Actually replace the tail. 63 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest); 64 65 // Fix up IT. 66 if (CC != ARMCC::AL) { 67 MachineBasicBlock::iterator E = MBB->begin(); 68 unsigned Count = 4; // At most 4 instructions in an IT block. 69 while (Count && MBBI != E) { 70 if (MBBI->isDebugValue()) { 71 --MBBI; 72 continue; 73 } 74 if (MBBI->getOpcode() == ARM::t2IT) { 75 unsigned Mask = MBBI->getOperand(1).getImm(); 76 if (Count == 4) 77 MBBI->eraseFromParent(); 78 else { 79 unsigned MaskOn = 1 << Count; 80 unsigned MaskOff = ~(MaskOn - 1); 81 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn); 82 } 83 return; 84 } 85 --MBBI; 86 --Count; 87 } 88 89 // Ctrl flow can reach here if branch folding is run before IT block 90 // formation pass. 91 } 92 } 93 94 bool 95 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, 96 MachineBasicBlock::iterator MBBI) const { 97 while (MBBI->isDebugValue()) { 98 ++MBBI; 99 if (MBBI == MBB.end()) 100 return false; 101 } 102 103 unsigned PredReg = 0; 104 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; 105 } 106 107 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 108 MachineBasicBlock::iterator I, DebugLoc DL, 109 unsigned DestReg, unsigned SrcReg, 110 bool KillSrc) const { 111 // Handle SPR, DPR, and QPR copies. 112 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) 113 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); 114 115 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 116 .addReg(SrcReg, getKillRegState(KillSrc))); 117 } 118 119 void Thumb2InstrInfo:: 120 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 121 unsigned SrcReg, bool isKill, int FI, 122 const TargetRegisterClass *RC, 123 const TargetRegisterInfo *TRI) const { 124 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || 125 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) { 126 DebugLoc DL; 127 if (I != MBB.end()) DL = I->getDebugLoc(); 128 129 MachineFunction &MF = *MBB.getParent(); 130 MachineFrameInfo &MFI = *MF.getFrameInfo(); 131 MachineMemOperand *MMO = 132 MF.getMachineMemOperand( 133 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 134 MachineMemOperand::MOStore, 135 MFI.getObjectSize(FI), 136 MFI.getObjectAlignment(FI)); 137 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12)) 138 .addReg(SrcReg, getKillRegState(isKill)) 139 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 140 return; 141 } 142 143 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI); 144 } 145 146 void Thumb2InstrInfo:: 147 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 148 unsigned DestReg, int FI, 149 const TargetRegisterClass *RC, 150 const TargetRegisterInfo *TRI) const { 151 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || 152 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) { 153 DebugLoc DL; 154 if (I != MBB.end()) DL = I->getDebugLoc(); 155 156 MachineFunction &MF = *MBB.getParent(); 157 MachineFrameInfo &MFI = *MF.getFrameInfo(); 158 MachineMemOperand *MMO = 159 MF.getMachineMemOperand( 160 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 161 MachineMemOperand::MOLoad, 162 MFI.getObjectSize(FI), 163 MFI.getObjectAlignment(FI)); 164 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) 165 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 166 return; 167 } 168 169 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI); 170 } 171 172 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB, 173 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 174 unsigned DestReg, unsigned BaseReg, int NumBytes, 175 ARMCC::CondCodes Pred, unsigned PredReg, 176 const ARMBaseInstrInfo &TII, unsigned MIFlags) { 177 bool isSub = NumBytes < 0; 178 if (isSub) NumBytes = -NumBytes; 179 180 // If profitable, use a movw or movt to materialize the offset. 181 // FIXME: Use the scavenger to grab a scratch register. 182 if (DestReg != ARM::SP && DestReg != BaseReg && 183 NumBytes >= 4096 && 184 ARM_AM::getT2SOImmVal(NumBytes) == -1) { 185 bool Fits = false; 186 if (NumBytes < 65536) { 187 // Use a movw to materialize the 16-bit constant. 188 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) 189 .addImm(NumBytes) 190 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 191 Fits = true; 192 } else if ((NumBytes & 0xffff) == 0) { 193 // Use a movt to materialize the 32-bit constant. 194 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg) 195 .addReg(DestReg) 196 .addImm(NumBytes >> 16) 197 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 198 Fits = true; 199 } 200 201 if (Fits) { 202 if (isSub) { 203 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg) 204 .addReg(BaseReg, RegState::Kill) 205 .addReg(DestReg, RegState::Kill) 206 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 207 .setMIFlags(MIFlags); 208 } else { 209 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg) 210 .addReg(DestReg, RegState::Kill) 211 .addReg(BaseReg, RegState::Kill) 212 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 213 .setMIFlags(MIFlags); 214 } 215 return; 216 } 217 } 218 219 while (NumBytes) { 220 unsigned ThisVal = NumBytes; 221 unsigned Opc = 0; 222 if (DestReg == ARM::SP && BaseReg != ARM::SP) { 223 // mov sp, rn. Note t2MOVr cannot be used. 224 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg) 225 .addReg(BaseReg).setMIFlags(MIFlags)); 226 BaseReg = ARM::SP; 227 continue; 228 } 229 230 bool HasCCOut = true; 231 if (BaseReg == ARM::SP) { 232 // sub sp, sp, #imm7 233 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) { 234 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?"); 235 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 236 // FIXME: Fix Thumb1 immediate encoding. 237 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 238 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags); 239 NumBytes = 0; 240 continue; 241 } 242 243 // sub rd, sp, so_imm 244 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; 245 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { 246 NumBytes = 0; 247 } else { 248 // FIXME: Move this to ARMAddressingModes.h? 249 unsigned RotAmt = CountLeadingZeros_32(ThisVal); 250 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); 251 NumBytes &= ~ThisVal; 252 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && 253 "Bit extraction didn't work?"); 254 } 255 } else { 256 assert(DestReg != ARM::SP && BaseReg != ARM::SP); 257 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; 258 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { 259 NumBytes = 0; 260 } else if (ThisVal < 4096) { 261 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; 262 HasCCOut = false; 263 NumBytes = 0; 264 } else { 265 // FIXME: Move this to ARMAddressingModes.h? 266 unsigned RotAmt = CountLeadingZeros_32(ThisVal); 267 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); 268 NumBytes &= ~ThisVal; 269 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && 270 "Bit extraction didn't work?"); 271 } 272 } 273 274 // Build the new ADD / SUB. 275 MachineInstrBuilder MIB = 276 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 277 .addReg(BaseReg, RegState::Kill) 278 .addImm(ThisVal)).setMIFlags(MIFlags); 279 if (HasCCOut) 280 AddDefaultCC(MIB); 281 282 BaseReg = DestReg; 283 } 284 } 285 286 static unsigned 287 negativeOffsetOpcode(unsigned opcode) 288 { 289 switch (opcode) { 290 case ARM::t2LDRi12: return ARM::t2LDRi8; 291 case ARM::t2LDRHi12: return ARM::t2LDRHi8; 292 case ARM::t2LDRBi12: return ARM::t2LDRBi8; 293 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8; 294 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8; 295 case ARM::t2STRi12: return ARM::t2STRi8; 296 case ARM::t2STRBi12: return ARM::t2STRBi8; 297 case ARM::t2STRHi12: return ARM::t2STRHi8; 298 299 case ARM::t2LDRi8: 300 case ARM::t2LDRHi8: 301 case ARM::t2LDRBi8: 302 case ARM::t2LDRSHi8: 303 case ARM::t2LDRSBi8: 304 case ARM::t2STRi8: 305 case ARM::t2STRBi8: 306 case ARM::t2STRHi8: 307 return opcode; 308 309 default: 310 break; 311 } 312 313 return 0; 314 } 315 316 static unsigned 317 positiveOffsetOpcode(unsigned opcode) 318 { 319 switch (opcode) { 320 case ARM::t2LDRi8: return ARM::t2LDRi12; 321 case ARM::t2LDRHi8: return ARM::t2LDRHi12; 322 case ARM::t2LDRBi8: return ARM::t2LDRBi12; 323 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12; 324 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12; 325 case ARM::t2STRi8: return ARM::t2STRi12; 326 case ARM::t2STRBi8: return ARM::t2STRBi12; 327 case ARM::t2STRHi8: return ARM::t2STRHi12; 328 329 case ARM::t2LDRi12: 330 case ARM::t2LDRHi12: 331 case ARM::t2LDRBi12: 332 case ARM::t2LDRSHi12: 333 case ARM::t2LDRSBi12: 334 case ARM::t2STRi12: 335 case ARM::t2STRBi12: 336 case ARM::t2STRHi12: 337 return opcode; 338 339 default: 340 break; 341 } 342 343 return 0; 344 } 345 346 static unsigned 347 immediateOffsetOpcode(unsigned opcode) 348 { 349 switch (opcode) { 350 case ARM::t2LDRs: return ARM::t2LDRi12; 351 case ARM::t2LDRHs: return ARM::t2LDRHi12; 352 case ARM::t2LDRBs: return ARM::t2LDRBi12; 353 case ARM::t2LDRSHs: return ARM::t2LDRSHi12; 354 case ARM::t2LDRSBs: return ARM::t2LDRSBi12; 355 case ARM::t2STRs: return ARM::t2STRi12; 356 case ARM::t2STRBs: return ARM::t2STRBi12; 357 case ARM::t2STRHs: return ARM::t2STRHi12; 358 359 case ARM::t2LDRi12: 360 case ARM::t2LDRHi12: 361 case ARM::t2LDRBi12: 362 case ARM::t2LDRSHi12: 363 case ARM::t2LDRSBi12: 364 case ARM::t2STRi12: 365 case ARM::t2STRBi12: 366 case ARM::t2STRHi12: 367 case ARM::t2LDRi8: 368 case ARM::t2LDRHi8: 369 case ARM::t2LDRBi8: 370 case ARM::t2LDRSHi8: 371 case ARM::t2LDRSBi8: 372 case ARM::t2STRi8: 373 case ARM::t2STRBi8: 374 case ARM::t2STRHi8: 375 return opcode; 376 377 default: 378 break; 379 } 380 381 return 0; 382 } 383 384 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 385 unsigned FrameReg, int &Offset, 386 const ARMBaseInstrInfo &TII) { 387 unsigned Opcode = MI.getOpcode(); 388 const MCInstrDesc &Desc = MI.getDesc(); 389 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 390 bool isSub = false; 391 392 // Memory operands in inline assembly always use AddrModeT2_i12. 393 if (Opcode == ARM::INLINEASM) 394 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2? 395 396 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) { 397 Offset += MI.getOperand(FrameRegIdx+1).getImm(); 398 399 unsigned PredReg; 400 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { 401 // Turn it into a move. 402 MI.setDesc(TII.get(ARM::tMOVr)); 403 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 404 // Remove offset and remaining explicit predicate operands. 405 do MI.RemoveOperand(FrameRegIdx+1); 406 while (MI.getNumOperands() > FrameRegIdx+1); 407 MachineInstrBuilder MIB(&MI); 408 AddDefaultPred(MIB); 409 return true; 410 } 411 412 bool HasCCOut = Opcode != ARM::t2ADDri12; 413 414 if (Offset < 0) { 415 Offset = -Offset; 416 isSub = true; 417 MI.setDesc(TII.get(ARM::t2SUBri)); 418 } else { 419 MI.setDesc(TII.get(ARM::t2ADDri)); 420 } 421 422 // Common case: small offset, fits into instruction. 423 if (ARM_AM::getT2SOImmVal(Offset) != -1) { 424 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 425 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 426 // Add cc_out operand if the original instruction did not have one. 427 if (!HasCCOut) 428 MI.addOperand(MachineOperand::CreateReg(0, false)); 429 Offset = 0; 430 return true; 431 } 432 // Another common case: imm12. 433 if (Offset < 4096 && 434 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) { 435 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; 436 MI.setDesc(TII.get(NewOpc)); 437 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 438 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 439 // Remove the cc_out operand. 440 if (HasCCOut) 441 MI.RemoveOperand(MI.getNumOperands()-1); 442 Offset = 0; 443 return true; 444 } 445 446 // Otherwise, extract 8 adjacent bits from the immediate into this 447 // t2ADDri/t2SUBri. 448 unsigned RotAmt = CountLeadingZeros_32(Offset); 449 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt); 450 451 // We will handle these bits from offset, clear them. 452 Offset &= ~ThisImmVal; 453 454 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 && 455 "Bit extraction didn't work?"); 456 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 457 // Add cc_out operand if the original instruction did not have one. 458 if (!HasCCOut) 459 MI.addOperand(MachineOperand::CreateReg(0, false)); 460 461 } else { 462 463 // AddrMode4 and AddrMode6 cannot handle any offset. 464 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 465 return false; 466 467 // AddrModeT2_so cannot handle any offset. If there is no offset 468 // register then we change to an immediate version. 469 unsigned NewOpc = Opcode; 470 if (AddrMode == ARMII::AddrModeT2_so) { 471 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg(); 472 if (OffsetReg != 0) { 473 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 474 return Offset == 0; 475 } 476 477 MI.RemoveOperand(FrameRegIdx+1); 478 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0); 479 NewOpc = immediateOffsetOpcode(Opcode); 480 AddrMode = ARMII::AddrModeT2_i12; 481 } 482 483 unsigned NumBits = 0; 484 unsigned Scale = 1; 485 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) { 486 // i8 supports only negative, and i12 supports only positive, so 487 // based on Offset sign convert Opcode to the appropriate 488 // instruction 489 Offset += MI.getOperand(FrameRegIdx+1).getImm(); 490 if (Offset < 0) { 491 NewOpc = negativeOffsetOpcode(Opcode); 492 NumBits = 8; 493 isSub = true; 494 Offset = -Offset; 495 } else { 496 NewOpc = positiveOffsetOpcode(Opcode); 497 NumBits = 12; 498 } 499 } else if (AddrMode == ARMII::AddrMode5) { 500 // VFP address mode. 501 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1); 502 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 503 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 504 InstrOffs *= -1; 505 NumBits = 8; 506 Scale = 4; 507 Offset += InstrOffs * 4; 508 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 509 if (Offset < 0) { 510 Offset = -Offset; 511 isSub = true; 512 } 513 } else { 514 llvm_unreachable("Unsupported addressing mode!"); 515 } 516 517 if (NewOpc != Opcode) 518 MI.setDesc(TII.get(NewOpc)); 519 520 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1); 521 522 // Attempt to fold address computation 523 // Common case: small offset, fits into instruction. 524 int ImmedOffset = Offset / Scale; 525 unsigned Mask = (1 << NumBits) - 1; 526 if ((unsigned)Offset <= Mask * Scale) { 527 // Replace the FrameIndex with fp/sp 528 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 529 if (isSub) { 530 if (AddrMode == ARMII::AddrMode5) 531 // FIXME: Not consistent. 532 ImmedOffset |= 1 << NumBits; 533 else 534 ImmedOffset = -ImmedOffset; 535 } 536 ImmOp.ChangeToImmediate(ImmedOffset); 537 Offset = 0; 538 return true; 539 } 540 541 // Otherwise, offset doesn't fit. Pull in what we can to simplify 542 ImmedOffset = ImmedOffset & Mask; 543 if (isSub) { 544 if (AddrMode == ARMII::AddrMode5) 545 // FIXME: Not consistent. 546 ImmedOffset |= 1 << NumBits; 547 else { 548 ImmedOffset = -ImmedOffset; 549 if (ImmedOffset == 0) 550 // Change the opcode back if the encoded offset is zero. 551 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); 552 } 553 } 554 ImmOp.ChangeToImmediate(ImmedOffset); 555 Offset &= ~(Mask*Scale); 556 } 557 558 Offset = (isSub) ? -Offset : Offset; 559 return Offset == 0; 560 } 561 562 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 563 /// two-addrss instruction inserted by two-address pass. 564 void 565 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI, 566 MachineInstr *UseMI, 567 const TargetRegisterInfo &TRI) const { 568 if (SrcMI->getOpcode() != ARM::tMOVr || SrcMI->getOperand(1).isKill()) 569 return; 570 571 unsigned PredReg = 0; 572 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg); 573 if (CC == ARMCC::AL || PredReg != ARM::CPSR) 574 return; 575 576 // Schedule the copy so it doesn't come between previous instructions 577 // and UseMI which can form an IT block. 578 unsigned SrcReg = SrcMI->getOperand(1).getReg(); 579 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); 580 MachineBasicBlock *MBB = UseMI->getParent(); 581 MachineBasicBlock::iterator MBBI = SrcMI; 582 unsigned NumInsts = 0; 583 while (--MBBI != MBB->begin()) { 584 if (MBBI->isDebugValue()) 585 continue; 586 587 MachineInstr *NMI = &*MBBI; 588 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg); 589 if (!(NCC == CC || NCC == OCC) || 590 NMI->modifiesRegister(SrcReg, &TRI) || 591 NMI->definesRegister(ARM::CPSR)) 592 break; 593 if (++NumInsts == 4) 594 // Too many in a row! 595 return; 596 } 597 598 if (NumInsts) { 599 MBB->remove(SrcMI); 600 MBB->insert(++MBBI, SrcMI); 601 } 602 } 603 604 ARMCC::CondCodes 605 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 606 unsigned Opc = MI->getOpcode(); 607 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc) 608 return ARMCC::AL; 609 return llvm::getInstrPredicate(MI, PredReg); 610 } 611
