| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.h | 38 unsigned PredReg = 0,
|
| Thumb2InstrInfo.cpp | 55 unsigned PredReg = 0;
56 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
103 unsigned PredReg = 0;
104 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
175 ARMCC::CondCodes Pred, unsigned PredReg,
190 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
197 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
206 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
212 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
399 unsigned PredReg;
[all...] |
| Thumb2InstrInfo.h | 73 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
|
| Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg,
|
| ARMLoadStoreOptimizer.cpp | 91 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
103 unsigned PredReg,
109 ARMCC::CondCodes Pred, unsigned PredReg,
292 unsigned PredReg, unsigned Scratch, DebugLoc dl,
345 .addImm(Pred).addReg(PredReg).addReg(0);
356 .addImm(Pred).addReg(PredReg);
372 ARMCC::CondCodes Pred, unsigned PredReg,
407 Pred, PredReg, Scratch, dl, Regs))
439 ARMCC::CondCodes Pred, unsigned PredReg,
492 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges)
[all...] |
| Thumb1RegisterInfo.h | 43 unsigned PredReg = 0,
|
| ARMBaseRegisterInfo.cpp | 858 unsigned PredReg, unsigned MIFlags) const {
868 .addImm(0).addImm(Pred).addReg(PredReg)
892 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
895 Pred, PredReg, TII);
898 Pred, PredReg, TII);
931 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
932 unsigned PredReg = Old->getOperand(2).getReg();
933 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
935 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
936 unsigned PredReg = Old->getOperand(3).getReg()
[all...] |
| MLxExpansionPass.cpp | 219 unsigned PredReg = MI->getOperand(++NextOp).getReg();
230 MIB.addImm(Pred).addReg(PredReg);
242 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb2ITBlockPass.cpp | 151 unsigned PredReg = 0;
152 ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg);
|
| ARMBaseInstrInfo.h | 463 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
473 ARMCC::CondCodes Pred, unsigned PredReg,
479 ARMCC::CondCodes Pred, unsigned PredReg,
|
| ARMBaseRegisterInfo.h | 185 unsigned PredReg = 0,
|
| Thumb2SizeReduction.cpp | 532 unsigned PredReg = 0;
533 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
609 unsigned PredReg = 0;
610 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
700 unsigned PredReg = 0;
701 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
|
| Thumb1RegisterInfo.cpp | 69 ARMCC::CondCodes Pred, unsigned PredReg,
79 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
416 unsigned PredReg;
417 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
|
| ARMConstantIslandPass.cpp | [all...] |
| ARMExpandPseudoInsts.cpp | 642 unsigned PredReg = 0;
643 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
666 LO16.addImm(Pred).addReg(PredReg).addReg(0);
667 HI16.addImm(Pred).addReg(PredReg).addReg(0);
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
