HomeSort by relevance Sort by last modified time
    Searched refs:SPU (Results 1 - 13 of 13) sorted by null

  /external/llvm/lib/Target/CellSPU/
SPURegisterInfo.cpp 1 //===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
15 #include "SPU.h"
52 using namespace SPU;
54 case SPU::R0: return 0;
55 case SPU::R1: return 1;
56 case SPU::R2: return 2;
57 case SPU::R3: return 3;
58 case SPU::R4: return 4;
59 case SPU::R5: return 5;
60 case SPU::R6: return 6
    [all...]
SPUHazardRecognizers.cpp 10 // This file implements hazard recognizers for scheduling on Cell SPU
18 #include "SPU.h"
27 // Cell SPU hazard recognizer
29 // This is the pipeline hazard recognizer for the Cell SPU processor. It does
50 assert(Stalls == 0 && "SPU hazards don't yet support scoreboard lookahead");
57 case SPU::LQDv16i8:
58 case SPU::LQDv8i16:
59 case SPU::LQDv4i32:
60 case SPU::LQDv4f32:
61 case SPU::LQDv2f64
    [all...]
SPUInstrInfo.cpp 1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
35 return (opc == SPU::BR
36 || opc == SPU::BRA
37 || opc == SPU::BI);
44 return (opc == SPU::BRNZr32
45 || opc == SPU::BRNZv4i32
46 || opc == SPU::BRZr32
47 || opc == SPU::BRZv4i32
48 || opc == SPU::BRHNZr1
    [all...]
SPUFrameLowering.cpp 1 //===-- SPUTargetMachine.cpp - Define TargetMachine for Cell SPU ----------===//
10 // Top-level implementation for the Cell SPU target.
14 #include "SPU.h"
37 LR[0].first = SPU::R0;
119 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel);
124 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
125 .addReg(SPU::R1);
128 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize
    [all...]
SPUSubtarget.cpp 1 //===- SPUSubtarget.cpp - STI Cell SPU Subtarget Information --------------===//
15 #include "SPU.h"
30 ProcDirective(SPU::DEFAULT_PROC),
33 // Should be the target SPU processor type. For now, since there's only
59 CriticalPathRCs.push_back(&SPU::R8CRegClass);
60 CriticalPathRCs.push_back(&SPU::R16CRegClass);
61 CriticalPathRCs.push_back(&SPU::R32CRegClass);
62 CriticalPathRCs.push_back(&SPU::R32FPRegClass);
63 CriticalPathRCs.push_back(&SPU::R64CRegClass);
64 CriticalPathRCs.push_back(&SPU::VECREGRegClass)
    [all...]
Makefile 12 TARGET = SPU
SPUNopFiller.cpp 17 #include "SPU.h"
40 DEBUG( dbgs() << "********** SPU Nop filler **********\n" ; );
44 return "SPU nop/lnop Filler";
96 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::ENOP));
105 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::LNOP));
121 BuildMI(MBB, J, J->getDebugLoc(), TII->get(SPU::ENOP));
126 BuildMI(MBB, J, DebugLoc(), TII->get(SPU::LNOP));
SPUSubtarget.h 1 //===-- SPUSubtarget.h - Define Subtarget for the Cell SPU ------*- C++ -*-===//
10 // This file declares the Cell SPU-specific subclass of TargetSubtargetInfo.
28 namespace SPU {
44 /// Which SPU processor (this isn't really used, but it's there to keep
SPUISelDAGToDAG.cpp 10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
15 #include "SPU.h"
144 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
186 (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
188 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
189 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
190 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
191 (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) |
    [all...]
SPUISelLowering.cpp 1 //===-- SPUISelLowering.cpp - Cell SPU DAG Lowering Implementation --------===//
103 // Set RTLIB libcall names as used by SPU:
106 // Set up the SPU's register classes:
107 addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
108 addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
109 addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
110 addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
111 addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
112 addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
113 addRegisterClass(MVT::i128, SPU::GPRCRegisterClass)
    [all...]
SPUISelLowering.h 1 //===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
10 // This file defines the interfaces that Cell SPU uses to lower LLVM code into
20 #include "SPU.h"
63 namespace SPU {
  /external/llvm/lib/Target/CellSPU/MCTargetDesc/
SPUMCTargetDesc.cpp 1 //===-- SPUMCTargetDesc.cpp - Cell SPU Target Descriptions -----*- C++ -*-===//
10 // This file provides Cell SPU specific target descriptions.
45 InitSPUMCRegisterInfo(X, SPU::R0);
71 MachineLocation Src(SPU::R1, 0);
  /external/llvm/
configure     [all...]

Completed in 581 milliseconds