1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the pass that transforms the ARM machine instructions into 11 // relocatable machine code. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "jit" 16 #include "ARM.h" 17 #include "ARMAddressingModes.h" 18 #include "ARMConstantPoolValue.h" 19 #include "ARMInstrInfo.h" 20 #include "ARMRelocations.h" 21 #include "ARMSubtarget.h" 22 #include "ARMTargetMachine.h" 23 #include "llvm/Constants.h" 24 #include "llvm/DerivedTypes.h" 25 #include "llvm/Function.h" 26 #include "llvm/PassManager.h" 27 #include "llvm/CodeGen/JITCodeEmitter.h" 28 #include "llvm/CodeGen/MachineConstantPool.h" 29 #include "llvm/CodeGen/MachineFunctionPass.h" 30 #include "llvm/CodeGen/MachineInstr.h" 31 #include "llvm/CodeGen/MachineJumpTableInfo.h" 32 #include "llvm/CodeGen/MachineModuleInfo.h" 33 #include "llvm/CodeGen/Passes.h" 34 #include "llvm/ADT/Statistic.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/raw_ostream.h" 38 #ifndef NDEBUG 39 #include <iomanip> 40 #endif 41 using namespace llvm; 42 43 STATISTIC(NumEmitted, "Number of machine instructions emitted"); 44 45 namespace { 46 47 class ARMCodeEmitter : public MachineFunctionPass { 48 ARMJITInfo *JTI; 49 const ARMInstrInfo *II; 50 const TargetData *TD; 51 const ARMSubtarget *Subtarget; 52 TargetMachine &TM; 53 JITCodeEmitter &MCE; 54 MachineModuleInfo *MMI; 55 const std::vector<MachineConstantPoolEntry> *MCPEs; 56 const std::vector<MachineJumpTableEntry> *MJTEs; 57 bool IsPIC; 58 bool IsThumb; 59 60 void getAnalysisUsage(AnalysisUsage &AU) const { 61 AU.addRequired<MachineModuleInfo>(); 62 MachineFunctionPass::getAnalysisUsage(AU); 63 } 64 65 static char ID; 66 public: 67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 68 : MachineFunctionPass(ID), JTI(0), 69 II((const ARMInstrInfo *)tm.getInstrInfo()), 70 TD(tm.getTargetData()), TM(tm), 71 MCE(mce), MCPEs(0), MJTEs(0), 72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {} 73 74 /// getBinaryCodeForInstr - This function, generated by the 75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 76 /// machine instructions. 77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const; 78 79 bool runOnMachineFunction(MachineFunction &MF); 80 81 virtual const char *getPassName() const { 82 return "ARM Machine Code Emitter"; 83 } 84 85 void emitInstruction(const MachineInstr &MI); 86 87 private: 88 89 void emitWordLE(unsigned Binary); 90 void emitDWordLE(uint64_t Binary); 91 void emitConstantToMemory(unsigned CPI, const Constant *CV); 92 void emitConstPoolInstruction(const MachineInstr &MI); 93 void emitMOVi32immInstruction(const MachineInstr &MI); 94 void emitMOVi2piecesInstruction(const MachineInstr &MI); 95 void emitLEApcrelInstruction(const MachineInstr &MI); 96 void emitLEApcrelJTInstruction(const MachineInstr &MI); 97 void emitPseudoMoveInstruction(const MachineInstr &MI); 98 void addPCLabel(unsigned LabelID); 99 void emitPseudoInstruction(const MachineInstr &MI); 100 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 101 const MCInstrDesc &MCID, 102 const MachineOperand &MO, 103 unsigned OpIdx); 104 105 unsigned getMachineSoImmOpValue(unsigned SoImm); 106 unsigned getAddrModeSBit(const MachineInstr &MI, 107 const MCInstrDesc &MCID) const; 108 109 void emitDataProcessingInstruction(const MachineInstr &MI, 110 unsigned ImplicitRd = 0, 111 unsigned ImplicitRn = 0); 112 113 void emitLoadStoreInstruction(const MachineInstr &MI, 114 unsigned ImplicitRd = 0, 115 unsigned ImplicitRn = 0); 116 117 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 118 unsigned ImplicitRn = 0); 119 120 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 121 122 void emitMulFrmInstruction(const MachineInstr &MI); 123 124 void emitExtendInstruction(const MachineInstr &MI); 125 126 void emitMiscArithInstruction(const MachineInstr &MI); 127 128 void emitSaturateInstruction(const MachineInstr &MI); 129 130 void emitBranchInstruction(const MachineInstr &MI); 131 132 void emitInlineJumpTable(unsigned JTIndex); 133 134 void emitMiscBranchInstruction(const MachineInstr &MI); 135 136 void emitVFPArithInstruction(const MachineInstr &MI); 137 138 void emitVFPConversionInstruction(const MachineInstr &MI); 139 140 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 141 142 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 143 144 void emitMiscInstruction(const MachineInstr &MI); 145 146 void emitNEONLaneInstruction(const MachineInstr &MI); 147 void emitNEONDupInstruction(const MachineInstr &MI); 148 void emitNEON1RegModImmInstruction(const MachineInstr &MI); 149 void emitNEON2RegInstruction(const MachineInstr &MI); 150 void emitNEON3RegInstruction(const MachineInstr &MI); 151 152 /// getMachineOpValue - Return binary encoding of operand. If the machine 153 /// operand requires relocation, record the relocation and return zero. 154 unsigned getMachineOpValue(const MachineInstr &MI, 155 const MachineOperand &MO) const; 156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 157 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 158 } 159 160 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the 161 // TableGen'erated getBinaryCodeForInstr() function to encode any 162 // operand values, instead querying getMachineOpValue() directly for 163 // each operand it needs to encode. Thus, any of the new encoder 164 // helper functions can simply return 0 as the values the return 165 // are already handled elsewhere. They are placeholders to allow this 166 // encoder to continue to function until the MC encoder is sufficiently 167 // far along that this one can be eliminated entirely. 168 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) 169 const { return 0; } 170 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) 171 const { return 0; } 172 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val) 173 const { return 0; } 174 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val) 175 const { 176 if (IsThumb) { 177 Val &= 0x0FFFFFFF; 178 Val |= 0xE0000000; 179 } 180 return Val; 181 } 182 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 183 const { return 0; } 184 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 185 const { return 0; } 186 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op) 187 const { return 0; } 188 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op) 189 const { return 0; } 190 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op) 191 const { return 0; } 192 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op) 193 const { return 0; } 194 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op) 195 const { return 0; } 196 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 197 const { return 0; } 198 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI, 199 unsigned Op) const { return 0; } 200 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 201 const { return 0; } 202 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) 203 const { return 0; } 204 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) 205 const { return 0; } 206 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op) 207 const { return 0; } 208 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op) 209 const { return 0; } 210 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op) 211 const { return 0; } 212 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 213 const { return 0; } 214 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op) 215 const { return 0; } 216 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op) 217 const { return 0; } 218 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op) 219 const { return 0; } 220 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op) 221 const { return 0; } 222 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op) 223 const { return 0; } 224 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) 225 const { return 0; } 226 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op) 227 const { return 0; } 228 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op) 229 const { return 0; } 230 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op) 231 const { return 0; } 232 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) 233 const { return 0; } 234 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI, 235 unsigned Op) 236 const { return 0; } 237 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op) 238 const { return 0; } 239 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) 240 const { return 0; } 241 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, 242 unsigned Op) const { return 0; } 243 unsigned getMsbOpValue(const MachineInstr &MI, 244 unsigned Op) const { return 0; } 245 unsigned getSsatBitPosValue(const MachineInstr &MI, 246 unsigned Op) const { return 0; } 247 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) 248 const {return 0; } 249 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) 250 const { return 0; } 251 252 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 253 const { 254 // {17-13} = reg 255 // {12} = (U)nsigned (add == '1', sub == '0') 256 // {11-0} = imm12 257 const MachineOperand &MO = MI.getOperand(Op); 258 const MachineOperand &MO1 = MI.getOperand(Op + 1); 259 if (!MO.isReg()) { 260 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 261 return 0; 262 } 263 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 264 int32_t Imm12 = MO1.getImm(); 265 uint32_t Binary; 266 Binary = Imm12 & 0xfff; 267 if (Imm12 >= 0) 268 Binary |= (1 << 12); 269 Binary |= (Reg << 13); 270 return Binary; 271 } 272 273 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) 274 const { 275 const MCInstrDesc &MCID = MI.getDesc(); 276 const MachineOperand &MO = MI.getOperand(Op); 277 278 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ? 279 ARM::reloc_arm_movw : ARM::reloc_arm_movt); 280 281 if (!MO.isImm()) { 282 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 283 return 0; 284 } 285 unsigned Imm16 = static_cast<unsigned>(MO.getImm()); 286 return Imm16; 287 } 288 289 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) 290 const { return 0;} 291 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 292 const { return 0;} 293 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 294 const { return 0;} 295 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) 296 const { return 0; } 297 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op) 298 const { return 0; } 299 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op) 300 const { return 0; } 301 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op) 302 const { return 0; } 303 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op) 304 const { return 0; } 305 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { 306 // {12-9} = reg 307 // {8} = (U)nsigned (add == '1', sub == '0') 308 // {7-0} = imm8 309 uint32_t Binary = 0; 310 const MachineOperand &MO = MI.getOperand(Op); 311 uint32_t Reg = getMachineOpValue(MI, MO); 312 Binary |= (Reg << 9); 313 314 // If there is a non-zero immediate offset, encode it. 315 if (MO.isReg()) { 316 const MachineOperand &MO1 = MI.getOperand(Op + 1); 317 if (uint32_t ImmOffs = ARM_AM::getAM5Offset(MO1.getImm())) { 318 if (ARM_AM::getAM5Op(MO1.getImm()) == ARM_AM::add) 319 Binary |= 1 << 8; 320 Binary |= ImmOffs & 0xff; 321 return Binary; 322 } 323 } 324 325 // If immediate offset is omitted, default to +0. 326 Binary |= 1 << 8; 327 return Binary; 328 } 329 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) 330 const { return 0; } 331 332 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) 333 const { return 0; } 334 335 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op) 336 const { return 0; } 337 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op) 338 const { return 0; } 339 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op) 340 const { return 0; } 341 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op) 342 const { return 0; } 343 344 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 345 /// machine operand requires relocation, record the relocation and return 346 /// zero. 347 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, 348 unsigned Reloc); 349 350 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 351 /// 352 unsigned getShiftOp(unsigned Imm) const ; 353 354 /// Routines that handle operands which add machine relocations which are 355 /// fixed up by the relocation stage. 356 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 357 bool MayNeedFarStub, bool Indirect, 358 intptr_t ACPV = 0) const; 359 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const; 360 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const; 361 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const; 362 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 363 intptr_t JTBase = 0) const; 364 }; 365 } 366 367 char ARMCodeEmitter::ID = 0; 368 369 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 370 /// code to the specified MCE object. 371 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 372 JITCodeEmitter &JCE) { 373 return new ARMCodeEmitter(TM, JCE); 374 } 375 376 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 377 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 378 MF.getTarget().getRelocationModel() != Reloc::Static) && 379 "JIT relocation model must be set to static or default!"); 380 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo(); 381 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo(); 382 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData(); 383 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 384 MCPEs = &MF.getConstantPool()->getConstants(); 385 MJTEs = 0; 386 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 387 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 388 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction(); 389 JTI->Initialize(MF, IsPIC); 390 MMI = &getAnalysis<MachineModuleInfo>(); 391 MCE.setModuleInfo(MMI); 392 393 do { 394 DEBUG(errs() << "JITTing function '" 395 << MF.getFunction()->getName() << "'\n"); 396 MCE.startFunction(MF); 397 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 398 MBB != E; ++MBB) { 399 MCE.StartMachineBasicBlock(MBB); 400 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); 401 I != E; ++I) 402 emitInstruction(*I); 403 } 404 } while (MCE.finishFunction(MF)); 405 406 return false; 407 } 408 409 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 410 /// 411 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 412 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 413 default: llvm_unreachable("Unknown shift opc!"); 414 case ARM_AM::asr: return 2; 415 case ARM_AM::lsl: return 0; 416 case ARM_AM::lsr: return 1; 417 case ARM_AM::ror: 418 case ARM_AM::rrx: return 3; 419 } 420 return 0; 421 } 422 423 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 424 /// machine operand requires relocation, record the relocation and return zero. 425 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, 426 const MachineOperand &MO, 427 unsigned Reloc) { 428 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) 429 && "Relocation to this function should be for movt or movw"); 430 431 if (MO.isImm()) 432 return static_cast<unsigned>(MO.getImm()); 433 else if (MO.isGlobal()) 434 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 435 else if (MO.isSymbol()) 436 emitExternalSymbolAddress(MO.getSymbolName(), Reloc); 437 else if (MO.isMBB()) 438 emitMachineBasicBlock(MO.getMBB(), Reloc); 439 else { 440 #ifndef NDEBUG 441 errs() << MO; 442 #endif 443 llvm_unreachable("Unsupported operand type for movw/movt"); 444 } 445 return 0; 446 } 447 448 /// getMachineOpValue - Return binary encoding of operand. If the machine 449 /// operand requires relocation, record the relocation and return zero. 450 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 451 const MachineOperand &MO) const { 452 if (MO.isReg()) 453 return getARMRegisterNumbering(MO.getReg()); 454 else if (MO.isImm()) 455 return static_cast<unsigned>(MO.getImm()); 456 else if (MO.isFPImm()) 457 return static_cast<unsigned>(MO.getFPImm()->getValueAPF() 458 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 459 else if (MO.isGlobal()) 460 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 461 else if (MO.isSymbol()) 462 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 463 else if (MO.isCPI()) { 464 const MCInstrDesc &MCID = MI.getDesc(); 465 // For VFP load, the immediate offset is multiplied by 4. 466 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 467 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 468 emitConstPoolAddress(MO.getIndex(), Reloc); 469 } else if (MO.isJTI()) 470 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 471 else if (MO.isMBB()) 472 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 473 else 474 llvm_unreachable("Unable to encode MachineOperand!"); 475 return 0; 476 } 477 478 /// emitGlobalAddress - Emit the specified address to the code stream. 479 /// 480 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 481 bool MayNeedFarStub, bool Indirect, 482 intptr_t ACPV) const { 483 MachineRelocation MR = Indirect 484 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 485 const_cast<GlobalValue *>(GV), 486 ACPV, MayNeedFarStub) 487 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 488 const_cast<GlobalValue *>(GV), ACPV, 489 MayNeedFarStub); 490 MCE.addRelocation(MR); 491 } 492 493 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to 494 /// be emitted to the current location in the function, and allow it to be PC 495 /// relative. 496 void ARMCodeEmitter:: 497 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { 498 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 499 Reloc, ES)); 500 } 501 502 /// emitConstPoolAddress - Arrange for the address of an constant pool 503 /// to be emitted to the current location in the function, and allow it to be PC 504 /// relative. 505 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const { 506 // Tell JIT emitter we'll resolve the address. 507 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 508 Reloc, CPI, 0, true)); 509 } 510 511 /// emitJumpTableAddress - Arrange for the address of a jump table to 512 /// be emitted to the current location in the function, and allow it to be PC 513 /// relative. 514 void ARMCodeEmitter:: 515 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const { 516 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 517 Reloc, JTIndex, 0, true)); 518 } 519 520 /// emitMachineBasicBlock - Emit the specified address basic block. 521 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, 522 unsigned Reloc, 523 intptr_t JTBase) const { 524 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 525 Reloc, BB, JTBase)); 526 } 527 528 void ARMCodeEmitter::emitWordLE(unsigned Binary) { 529 DEBUG(errs() << " 0x"; 530 errs().write_hex(Binary) << "\n"); 531 MCE.emitWordLE(Binary); 532 } 533 534 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { 535 DEBUG(errs() << " 0x"; 536 errs().write_hex(Binary) << "\n"); 537 MCE.emitDWordLE(Binary); 538 } 539 540 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { 541 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 542 543 MCE.processDebugLoc(MI.getDebugLoc(), true); 544 545 ++NumEmitted; // Keep track of the # of mi's emitted 546 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 547 default: { 548 llvm_unreachable("Unhandled instruction encoding format!"); 549 break; 550 } 551 case ARMII::MiscFrm: 552 if (MI.getOpcode() == ARM::LEApcrelJT) { 553 // Materialize jumptable address. 554 emitLEApcrelJTInstruction(MI); 555 break; 556 } 557 llvm_unreachable("Unhandled instruction encoding!"); 558 break; 559 case ARMII::Pseudo: 560 emitPseudoInstruction(MI); 561 break; 562 case ARMII::DPFrm: 563 case ARMII::DPSoRegFrm: 564 emitDataProcessingInstruction(MI); 565 break; 566 case ARMII::LdFrm: 567 case ARMII::StFrm: 568 emitLoadStoreInstruction(MI); 569 break; 570 case ARMII::LdMiscFrm: 571 case ARMII::StMiscFrm: 572 emitMiscLoadStoreInstruction(MI); 573 break; 574 case ARMII::LdStMulFrm: 575 emitLoadStoreMultipleInstruction(MI); 576 break; 577 case ARMII::MulFrm: 578 emitMulFrmInstruction(MI); 579 break; 580 case ARMII::ExtFrm: 581 emitExtendInstruction(MI); 582 break; 583 case ARMII::ArithMiscFrm: 584 emitMiscArithInstruction(MI); 585 break; 586 case ARMII::SatFrm: 587 emitSaturateInstruction(MI); 588 break; 589 case ARMII::BrFrm: 590 emitBranchInstruction(MI); 591 break; 592 case ARMII::BrMiscFrm: 593 emitMiscBranchInstruction(MI); 594 break; 595 // VFP instructions. 596 case ARMII::VFPUnaryFrm: 597 case ARMII::VFPBinaryFrm: 598 emitVFPArithInstruction(MI); 599 break; 600 case ARMII::VFPConv1Frm: 601 case ARMII::VFPConv2Frm: 602 case ARMII::VFPConv3Frm: 603 case ARMII::VFPConv4Frm: 604 case ARMII::VFPConv5Frm: 605 emitVFPConversionInstruction(MI); 606 break; 607 case ARMII::VFPLdStFrm: 608 emitVFPLoadStoreInstruction(MI); 609 break; 610 case ARMII::VFPLdStMulFrm: 611 emitVFPLoadStoreMultipleInstruction(MI); 612 break; 613 case ARMII::VFPMiscFrm: 614 emitMiscInstruction(MI); 615 break; 616 // NEON instructions. 617 case ARMII::NGetLnFrm: 618 case ARMII::NSetLnFrm: 619 emitNEONLaneInstruction(MI); 620 break; 621 case ARMII::NDupFrm: 622 emitNEONDupInstruction(MI); 623 break; 624 case ARMII::N1RegModImmFrm: 625 emitNEON1RegModImmInstruction(MI); 626 break; 627 case ARMII::N2RegFrm: 628 emitNEON2RegInstruction(MI); 629 break; 630 case ARMII::N3RegFrm: 631 emitNEON3RegInstruction(MI); 632 break; 633 } 634 MCE.processDebugLoc(MI.getDebugLoc(), false); 635 } 636 637 void ARMCodeEmitter::emitConstantToMemory(unsigned CPI, const Constant *C) { 638 DEBUG({ 639 errs() << " ** Constant pool #" << CPI << " @ " 640 << (void*)MCE.getCurrentPCValue() << " "; 641 if (const Function *F = dyn_cast<Function>(C)) 642 errs() << F->getName(); 643 else 644 errs() << *C; 645 errs() << '\n'; 646 }); 647 648 switch (C->getValueID()) { 649 default: { 650 llvm_unreachable("Unable to handle this constantpool entry!"); 651 break; 652 } 653 case Value::GlobalVariableVal: { 654 emitGlobalAddress(static_cast<const GlobalValue*>(C), 655 ARM::reloc_arm_absolute, isa<Function>(C), false); 656 emitWordLE(0); 657 break; 658 } 659 case Value::ConstantIntVal: { 660 const ConstantInt *CI = static_cast<const ConstantInt*>(C); 661 uint32_t Val = *(uint32_t*)CI->getValue().getRawData(); 662 emitWordLE(Val); 663 break; 664 } 665 case Value::ConstantFPVal: { 666 const ConstantFP *CFP = static_cast<const ConstantFP*>(C); 667 if (CFP->getType()->isFloatTy()) 668 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 669 else if (CFP->getType()->isDoubleTy()) 670 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 671 else { 672 llvm_unreachable("Unable to handle this constantpool entry!"); 673 } 674 break; 675 } 676 case Value::ConstantArrayVal: { 677 const ConstantArray *CA = static_cast<const ConstantArray*>(C); 678 for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i) 679 emitConstantToMemory(CPI, CA->getOperand(i)); 680 break; 681 } 682 case Value::ConstantVectorVal:{ 683 //FIXME:emit vector 684 const ConstantVector *CV = static_cast<const ConstantVector*>(C); 685 break; 686 } 687 } 688 689 return; 690 } 691 692 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { 693 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 694 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 695 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 696 697 // Remember the CONSTPOOL_ENTRY address for later relocation. 698 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 699 700 // Emit constpool island entry. In most cases, the actual values will be 701 // resolved and relocated after code emission. 702 if (MCPE.isMachineConstantPoolEntry()) { 703 ARMConstantPoolValue *ACPV = 704 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 705 706 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 707 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 708 709 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 710 const GlobalValue *GV = ACPV->getGV(); 711 if (GV) { 712 Reloc::Model RelocM = TM.getRelocationModel(); 713 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 714 isa<Function>(GV), 715 Subtarget->GVIsIndirectSymbol(GV, RelocM), 716 (intptr_t)ACPV); 717 } else { 718 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute); 719 } 720 emitWordLE(0); 721 } else { 722 emitConstantToMemory(CPI, MCPE.Val.ConstVal); 723 } 724 } 725 726 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) { 727 const MachineOperand &MO0 = MI.getOperand(0); 728 const MachineOperand &MO1 = MI.getOperand(1); 729 730 // Emit the 'movw' instruction. 731 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000 732 733 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF; 734 735 // Set the conditional execution predicate. 736 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 737 738 // Encode Rd. 739 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 740 741 // Encode imm16 as imm4:imm12 742 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12 743 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4 744 emitWordLE(Binary); 745 746 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16; 747 // Emit the 'movt' instruction. 748 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100 749 750 // Set the conditional execution predicate. 751 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 752 753 // Encode Rd. 754 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 755 756 // Encode imm16 as imm4:imm1, same as movw above. 757 Binary |= Hi16 & 0xFFF; 758 Binary |= ((Hi16 >> 12) & 0xF) << 16; 759 emitWordLE(Binary); 760 } 761 762 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { 763 const MachineOperand &MO0 = MI.getOperand(0); 764 const MachineOperand &MO1 = MI.getOperand(1); 765 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 766 "Not a valid so_imm value!"); 767 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 768 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 769 770 // Emit the 'mov' instruction. 771 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 772 773 // Set the conditional execution predicate. 774 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 775 776 // Encode Rd. 777 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 778 779 // Encode so_imm. 780 // Set bit I(25) to identify this is the immediate form of <shifter_op> 781 Binary |= 1 << ARMII::I_BitShift; 782 Binary |= getMachineSoImmOpValue(V1); 783 emitWordLE(Binary); 784 785 // Now the 'orr' instruction. 786 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 787 788 // Set the conditional execution predicate. 789 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 790 791 // Encode Rd. 792 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 793 794 // Encode Rn. 795 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 796 797 // Encode so_imm. 798 // Set bit I(25) to identify this is the immediate form of <shifter_op> 799 Binary |= 1 << ARMII::I_BitShift; 800 Binary |= getMachineSoImmOpValue(V2); 801 emitWordLE(Binary); 802 } 803 804 void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) { 805 // It's basically add r, pc, (LCPI - $+8) 806 const MCInstrDesc &MCID = MI.getDesc(); 807 808 unsigned Binary = 0; 809 810 // Set the conditional execution predicate 811 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 812 813 // Encode S bit if MI modifies CPSR. 814 Binary |= getAddrModeSBit(MI, MCID); 815 816 // Encode Rd. 817 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 818 819 // Encode Rn which is PC. 820 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 821 822 // Encode the displacement which is a so_imm. 823 // Set bit I(25) to identify this is the immediate form of <shifter_op> 824 Binary |= 1 << ARMII::I_BitShift; 825 emitConstPoolAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_so_imm_cp_entry); 826 827 emitWordLE(Binary); 828 } 829 830 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { 831 // It's basically add r, pc, (LJTI - $+8) 832 833 const MCInstrDesc &MCID = MI.getDesc(); 834 835 // Emit the 'add' instruction. 836 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100 837 838 // Set the conditional execution predicate 839 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 840 841 // Encode S bit if MI modifies CPSR. 842 Binary |= getAddrModeSBit(MI, MCID); 843 844 // Encode Rd. 845 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 846 847 // Encode Rn which is PC. 848 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 849 850 // Encode the displacement. 851 Binary |= 1 << ARMII::I_BitShift; 852 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 853 854 emitWordLE(Binary); 855 } 856 857 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { 858 unsigned Opcode = MI.getDesc().Opcode; 859 860 // Part of binary is determined by TableGn. 861 unsigned Binary = getBinaryCodeForInstr(MI); 862 863 // Set the conditional execution predicate 864 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 865 866 // Encode S bit if MI modifies CPSR. 867 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 868 Binary |= 1 << ARMII::S_BitShift; 869 870 // Encode register def if there is one. 871 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 872 873 // Encode the shift operation. 874 switch (Opcode) { 875 default: break; 876 case ARM::RRX: 877 // rrx 878 Binary |= 0x6 << 4; 879 break; 880 case ARM::MOVsrl_flag: 881 // lsr #1 882 Binary |= (0x2 << 4) | (1 << 7); 883 break; 884 case ARM::MOVsra_flag: 885 // asr #1 886 Binary |= (0x4 << 4) | (1 << 7); 887 break; 888 } 889 890 // Encode register Rm. 891 Binary |= getMachineOpValue(MI, 1); 892 893 emitWordLE(Binary); 894 } 895 896 void ARMCodeEmitter::addPCLabel(unsigned LabelID) { 897 DEBUG(errs() << " ** LPC" << LabelID << " @ " 898 << (void*)MCE.getCurrentPCValue() << '\n'); 899 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 900 } 901 902 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { 903 unsigned Opcode = MI.getDesc().Opcode; 904 switch (Opcode) { 905 default: 906 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 907 case ARM::B: 908 emitBranchInstruction(MI); 909 break; 910 case ARM::BR_JTr: 911 case ARM::BR_JTm: 912 case ARM::BR_JTadd: 913 emitMiscBranchInstruction(MI); 914 break; 915 case ARM::BX_CALL: 916 case ARM::BMOVPCRX_CALL: 917 case ARM::BXr9_CALL: 918 case ARM::BMOVPCRXr9_CALL: { 919 // First emit mov lr, pc 920 unsigned Binary = 0x01a0e00f; 921 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 922 emitWordLE(Binary); 923 924 // and then emit the branch. 925 emitMiscBranchInstruction(MI); 926 break; 927 } 928 case TargetOpcode::INLINEASM: { 929 // We allow inline assembler nodes with empty bodies - they can 930 // implicitly define registers, which is ok for JIT. 931 if (MI.getOperand(0).getSymbolName()[0]) { 932 report_fatal_error("JIT does not support inline asm!"); 933 } 934 break; 935 } 936 case TargetOpcode::PROLOG_LABEL: 937 case TargetOpcode::EH_LABEL: 938 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 939 break; 940 case TargetOpcode::IMPLICIT_DEF: 941 case TargetOpcode::KILL: 942 // Do nothing. 943 break; 944 case ARM::CONSTPOOL_ENTRY: 945 emitConstPoolInstruction(MI); 946 break; 947 case ARM::LDMIA_RET: 948 emitLoadStoreMultipleInstruction(MI); 949 break; 950 case ARM::PICADD: { 951 // Remember of the address of the PC label for relocation later. 952 addPCLabel(MI.getOperand(2).getImm()); 953 // PICADD is just an add instruction that implicitly read pc. 954 emitDataProcessingInstruction(MI, 0, ARM::PC); 955 break; 956 } 957 case ARM::PICLDR: 958 case ARM::PICLDRB: 959 case ARM::PICSTR: 960 case ARM::PICSTRB: { 961 // Remember of the address of the PC label for relocation later. 962 addPCLabel(MI.getOperand(2).getImm()); 963 // These are just load / store instructions that implicitly read pc. 964 emitLoadStoreInstruction(MI, 0, ARM::PC); 965 break; 966 } 967 case ARM::PICLDRH: 968 case ARM::PICLDRSH: 969 case ARM::PICLDRSB: 970 case ARM::PICSTRH: { 971 // Remember of the address of the PC label for relocation later. 972 addPCLabel(MI.getOperand(2).getImm()); 973 // These are just load / store instructions that implicitly read pc. 974 emitMiscLoadStoreInstruction(MI, ARM::PC); 975 break; 976 } 977 978 case ARM::MOVi32imm: 979 // Two instructions to materialize a constant. 980 if (Subtarget->hasV6T2Ops()) 981 emitMOVi32immInstruction(MI); 982 else 983 emitMOVi2piecesInstruction(MI); 984 break; 985 case ARM::LEApcrel: 986 // Materialize constantpool index address. 987 emitLEApcrelInstruction(MI); 988 break; 989 case ARM::LEApcrelJT: 990 // Materialize jumptable address. 991 emitLEApcrelJTInstruction(MI); 992 break; 993 case ARM::RRX: 994 case ARM::MOVsrl_flag: 995 case ARM::MOVsra_flag: 996 emitPseudoMoveInstruction(MI); 997 break; 998 } 999 } 1000 1001 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, 1002 const MCInstrDesc &MCID, 1003 const MachineOperand &MO, 1004 unsigned OpIdx) { 1005 unsigned Binary = getMachineOpValue(MI, MO); 1006 1007 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 1008 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 1009 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1010 1011 // Encode the shift opcode. 1012 unsigned SBits = 0; 1013 unsigned Rs = MO1.getReg(); 1014 if (Rs) { 1015 // Set shift operand (bit[7:4]). 1016 // LSL - 0001 1017 // LSR - 0011 1018 // ASR - 0101 1019 // ROR - 0111 1020 // RRX - 0110 and bit[11:8] clear. 1021 switch (SOpc) { 1022 default: llvm_unreachable("Unknown shift opc!"); 1023 case ARM_AM::lsl: SBits = 0x1; break; 1024 case ARM_AM::lsr: SBits = 0x3; break; 1025 case ARM_AM::asr: SBits = 0x5; break; 1026 case ARM_AM::ror: SBits = 0x7; break; 1027 case ARM_AM::rrx: SBits = 0x6; break; 1028 } 1029 } else { 1030 // Set shift operand (bit[6:4]). 1031 // LSL - 000 1032 // LSR - 010 1033 // ASR - 100 1034 // ROR - 110 1035 switch (SOpc) { 1036 default: llvm_unreachable("Unknown shift opc!"); 1037 case ARM_AM::lsl: SBits = 0x0; break; 1038 case ARM_AM::lsr: SBits = 0x2; break; 1039 case ARM_AM::asr: SBits = 0x4; break; 1040 case ARM_AM::ror: SBits = 0x6; break; 1041 } 1042 } 1043 Binary |= SBits << 4; 1044 if (SOpc == ARM_AM::rrx) 1045 return Binary; 1046 1047 // Encode the shift operation Rs or shift_imm (except rrx). 1048 if (Rs) { 1049 // Encode Rs bit[11:8]. 1050 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1051 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); 1052 } 1053 1054 // Encode shift_imm bit[11:7]. 1055 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 1056 } 1057 1058 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { 1059 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 1060 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 1061 1062 // Encode rotate_imm. 1063 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 1064 << ARMII::SoRotImmShift; 1065 1066 // Encode immed_8. 1067 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 1068 return Binary; 1069 } 1070 1071 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, 1072 const MCInstrDesc &MCID) const { 1073 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e; --i){ 1074 const MachineOperand &MO = MI.getOperand(i-1); 1075 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 1076 return 1 << ARMII::S_BitShift; 1077 } 1078 return 0; 1079 } 1080 1081 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, 1082 unsigned ImplicitRd, 1083 unsigned ImplicitRn) { 1084 const MCInstrDesc &MCID = MI.getDesc(); 1085 1086 // Part of binary is determined by TableGn. 1087 unsigned Binary = getBinaryCodeForInstr(MI); 1088 1089 if (MCID.Opcode == ARM::MOVi16 || MCID.Opcode == ARM::MOVTi16) { 1090 emitWordLE(Binary); 1091 return; 1092 } 1093 1094 // Set the conditional execution predicate 1095 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1096 1097 // Encode S bit if MI modifies CPSR. 1098 Binary |= getAddrModeSBit(MI, MCID); 1099 1100 // Encode register def if there is one. 1101 unsigned NumDefs = MCID.getNumDefs(); 1102 unsigned OpIdx = 0; 1103 if (NumDefs) 1104 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1105 else if (ImplicitRd) 1106 // Special handling for implicit use (e.g. PC). 1107 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 1108 1109 if (MCID.Opcode == ARM::MOVi16) { 1110 // Get immediate from MI. 1111 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), 1112 ARM::reloc_arm_movw); 1113 // Encode imm which is the same as in emitMOVi32immInstruction(). 1114 Binary |= Lo16 & 0xFFF; 1115 Binary |= ((Lo16 >> 12) & 0xF) << 16; 1116 emitWordLE(Binary); 1117 return; 1118 } else if(MCID.Opcode == ARM::MOVTi16) { 1119 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), 1120 ARM::reloc_arm_movt) >> 16); 1121 Binary |= Hi16 & 0xFFF; 1122 Binary |= ((Hi16 >> 12) & 0xF) << 16; 1123 emitWordLE(Binary); 1124 return; 1125 } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) { 1126 uint32_t v = ~MI.getOperand(2).getImm(); 1127 int32_t lsb = CountTrailingZeros_32(v); 1128 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1; 1129 // Instr{20-16} = msb, Instr{11-7} = lsb 1130 Binary |= (msb & 0x1F) << 16; 1131 Binary |= (lsb & 0x1F) << 7; 1132 emitWordLE(Binary); 1133 return; 1134 } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) { 1135 // Encode Rn in Instr{0-3} 1136 Binary |= getMachineOpValue(MI, OpIdx++); 1137 1138 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); 1139 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; 1140 1141 // Instr{20-16} = widthm1, Instr{11-7} = lsb 1142 Binary |= (widthm1 & 0x1F) << 16; 1143 Binary |= (lsb & 0x1F) << 7; 1144 emitWordLE(Binary); 1145 return; 1146 } 1147 1148 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 1149 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1150 ++OpIdx; 1151 1152 // Encode first non-shifter register operand if there is one. 1153 bool isUnary = MCID.TSFlags & ARMII::UnaryDP; 1154 if (!isUnary) { 1155 if (ImplicitRn) 1156 // Special handling for implicit use (e.g. PC). 1157 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1158 else { 1159 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 1160 ++OpIdx; 1161 } 1162 } 1163 1164 // Encode shifter operand. 1165 const MachineOperand &MO = MI.getOperand(OpIdx); 1166 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 1167 // Encode SoReg. 1168 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx)); 1169 return; 1170 } 1171 1172 if (MO.isReg()) { 1173 // Encode register Rm. 1174 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg())); 1175 return; 1176 } 1177 1178 // Encode so_imm. 1179 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 1180 1181 emitWordLE(Binary); 1182 } 1183 1184 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, 1185 unsigned ImplicitRd, 1186 unsigned ImplicitRn) { 1187 const MCInstrDesc &MCID = MI.getDesc(); 1188 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1189 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1190 1191 // Part of binary is determined by TableGn. 1192 unsigned Binary = getBinaryCodeForInstr(MI); 1193 1194 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done. 1195 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp || 1196 MI.getOpcode() == ARM::STRi12 || MI.getOpcode() == ARM::LDRBi12 || 1197 MI.getOpcode() == ARM::STRBi12) { 1198 emitWordLE(Binary); 1199 return; 1200 } 1201 1202 if (MI.getOpcode() == ARM::BR_JTm) 1203 Binary = 0x710F000; 1204 else if (MI.getOpcode() == ARM::BR_JTr) 1205 Binary = 0x1A0F000; 1206 1207 // Set the conditional execution predicate 1208 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1209 1210 unsigned OpIdx = 0; 1211 1212 // Operand 0 of a pre- and post-indexed store is the address base 1213 // writeback. Skip it. 1214 bool Skipped = false; 1215 if (IsPrePost && Form == ARMII::StFrm) { 1216 ++OpIdx; 1217 Skipped = true; 1218 } 1219 1220 // Set first operand 1221 if (ImplicitRd) 1222 // Special handling for implicit use (e.g. PC). 1223 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 1224 else 1225 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1226 1227 // Set second operand 1228 if (ImplicitRn) 1229 // Special handling for implicit use (e.g. PC). 1230 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1231 else 1232 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1233 1234 // If this is a two-address operand, skip it. e.g. LDR_PRE. 1235 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1236 ++OpIdx; 1237 1238 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1239 unsigned AM2Opc = (ImplicitRn == ARM::PC) 1240 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1241 1242 // Set bit U(23) according to sign of immed value (positive or negative). 1243 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 1244 ARMII::U_BitShift); 1245 if (!MO2.getReg()) { // is immediate 1246 if (ARM_AM::getAM2Offset(AM2Opc)) 1247 // Set the value of offset_12 field 1248 Binary |= ARM_AM::getAM2Offset(AM2Opc); 1249 emitWordLE(Binary); 1250 return; 1251 } 1252 1253 // Set bit I(25), because this is not in immediate encoding. 1254 Binary |= 1 << ARMII::I_BitShift; 1255 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 1256 // Set bit[3:0] to the corresponding Rm register 1257 Binary |= getARMRegisterNumbering(MO2.getReg()); 1258 1259 // If this instr is in scaled register offset/index instruction, set 1260 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 1261 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 1262 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 1263 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 1264 } 1265 1266 emitWordLE(Binary); 1267 } 1268 1269 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, 1270 unsigned ImplicitRn) { 1271 const MCInstrDesc &MCID = MI.getDesc(); 1272 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1273 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1274 1275 // Part of binary is determined by TableGn. 1276 unsigned Binary = getBinaryCodeForInstr(MI); 1277 1278 // Set the conditional execution predicate 1279 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1280 1281 unsigned OpIdx = 0; 1282 1283 // Operand 0 of a pre- and post-indexed store is the address base 1284 // writeback. Skip it. 1285 bool Skipped = false; 1286 if (IsPrePost && Form == ARMII::StMiscFrm) { 1287 ++OpIdx; 1288 Skipped = true; 1289 } 1290 1291 // Set first operand 1292 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1293 1294 // Skip LDRD and STRD's second operand. 1295 if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD) 1296 ++OpIdx; 1297 1298 // Set second operand 1299 if (ImplicitRn) 1300 // Special handling for implicit use (e.g. PC). 1301 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1302 else 1303 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1304 1305 // If this is a two-address operand, skip it. e.g. LDRH_POST. 1306 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1307 ++OpIdx; 1308 1309 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1310 unsigned AM3Opc = (ImplicitRn == ARM::PC) 1311 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1312 1313 // Set bit U(23) according to sign of immed value (positive or negative) 1314 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 1315 ARMII::U_BitShift); 1316 1317 // If this instr is in register offset/index encoding, set bit[3:0] 1318 // to the corresponding Rm register. 1319 if (MO2.getReg()) { 1320 Binary |= getARMRegisterNumbering(MO2.getReg()); 1321 emitWordLE(Binary); 1322 return; 1323 } 1324 1325 // This instr is in immediate offset/index encoding, set bit 22 to 1. 1326 Binary |= 1 << ARMII::AM3_I_BitShift; 1327 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 1328 // Set operands 1329 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 1330 Binary |= (ImmOffs & 0xF); // immedL 1331 } 1332 1333 emitWordLE(Binary); 1334 } 1335 1336 static unsigned getAddrModeUPBits(unsigned Mode) { 1337 unsigned Binary = 0; 1338 1339 // Set addressing mode by modifying bits U(23) and P(24) 1340 // IA - Increment after - bit U = 1 and bit P = 0 1341 // IB - Increment before - bit U = 1 and bit P = 1 1342 // DA - Decrement after - bit U = 0 and bit P = 0 1343 // DB - Decrement before - bit U = 0 and bit P = 1 1344 switch (Mode) { 1345 default: llvm_unreachable("Unknown addressing sub-mode!"); 1346 case ARM_AM::da: break; 1347 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 1348 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 1349 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 1350 } 1351 1352 return Binary; 1353 } 1354 1355 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { 1356 const MCInstrDesc &MCID = MI.getDesc(); 1357 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1358 1359 // Part of binary is determined by TableGn. 1360 unsigned Binary = getBinaryCodeForInstr(MI); 1361 1362 if (MCID.getOpcode() == ARM::LDMIA_RET) { 1363 IsUpdating = true; 1364 Binary |= 0x8B00000; 1365 } 1366 1367 // Set the conditional execution predicate 1368 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1369 1370 // Skip operand 0 of an instruction with base register update. 1371 unsigned OpIdx = 0; 1372 if (IsUpdating) 1373 ++OpIdx; 1374 1375 // Set base address operand 1376 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1377 1378 // Set addressing mode by modifying bits U(23) and P(24) 1379 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1380 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1381 1382 // Set bit W(21) 1383 if (IsUpdating) 1384 Binary |= 0x1 << ARMII::W_BitShift; 1385 1386 // Set registers 1387 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { 1388 const MachineOperand &MO = MI.getOperand(i); 1389 if (!MO.isReg() || MO.isImplicit()) 1390 break; 1391 unsigned RegNum = getARMRegisterNumbering(MO.getReg()); 1392 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 1393 RegNum < 16); 1394 Binary |= 0x1 << RegNum; 1395 } 1396 1397 emitWordLE(Binary); 1398 } 1399 1400 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { 1401 const MCInstrDesc &MCID = MI.getDesc(); 1402 1403 // Part of binary is determined by TableGn. 1404 unsigned Binary = getBinaryCodeForInstr(MI); 1405 1406 // Set the conditional execution predicate 1407 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1408 1409 // Encode S bit if MI modifies CPSR. 1410 Binary |= getAddrModeSBit(MI, MCID); 1411 1412 // 32x32->64bit operations have two destination registers. The number 1413 // of register definitions will tell us if that's what we're dealing with. 1414 unsigned OpIdx = 0; 1415 if (MCID.getNumDefs() == 2) 1416 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1417 1418 // Encode Rd 1419 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1420 1421 // Encode Rm 1422 Binary |= getMachineOpValue(MI, OpIdx++); 1423 1424 // Encode Rs 1425 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1426 1427 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1428 // it as Rn (for multiply, that's in the same offset as RdLo. 1429 if (MCID.getNumOperands() > OpIdx && 1430 !MCID.OpInfo[OpIdx].isPredicate() && 1431 !MCID.OpInfo[OpIdx].isOptionalDef()) 1432 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1433 1434 emitWordLE(Binary); 1435 } 1436 1437 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { 1438 const MCInstrDesc &MCID = MI.getDesc(); 1439 1440 // Part of binary is determined by TableGn. 1441 unsigned Binary = getBinaryCodeForInstr(MI); 1442 1443 // Set the conditional execution predicate 1444 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1445 1446 unsigned OpIdx = 0; 1447 1448 // Encode Rd 1449 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1450 1451 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1452 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1453 if (MO2.isReg()) { 1454 // Two register operand form. 1455 // Encode Rn. 1456 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1457 1458 // Encode Rm. 1459 Binary |= getMachineOpValue(MI, MO2); 1460 ++OpIdx; 1461 } else { 1462 Binary |= getMachineOpValue(MI, MO1); 1463 } 1464 1465 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1466 if (MI.getOperand(OpIdx).isImm() && 1467 !MCID.OpInfo[OpIdx].isPredicate() && 1468 !MCID.OpInfo[OpIdx].isOptionalDef()) 1469 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1470 1471 emitWordLE(Binary); 1472 } 1473 1474 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { 1475 const MCInstrDesc &MCID = MI.getDesc(); 1476 1477 // Part of binary is determined by TableGn. 1478 unsigned Binary = getBinaryCodeForInstr(MI); 1479 1480 // Set the conditional execution predicate 1481 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1482 1483 // PKH instructions are finished at this point 1484 if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) { 1485 emitWordLE(Binary); 1486 return; 1487 } 1488 1489 unsigned OpIdx = 0; 1490 1491 // Encode Rd 1492 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1493 1494 const MachineOperand &MO = MI.getOperand(OpIdx++); 1495 if (OpIdx == MCID.getNumOperands() || 1496 MCID.OpInfo[OpIdx].isPredicate() || 1497 MCID.OpInfo[OpIdx].isOptionalDef()) { 1498 // Encode Rm and it's done. 1499 Binary |= getMachineOpValue(MI, MO); 1500 emitWordLE(Binary); 1501 return; 1502 } 1503 1504 // Encode Rn. 1505 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1506 1507 // Encode Rm. 1508 Binary |= getMachineOpValue(MI, OpIdx++); 1509 1510 // Encode shift_imm. 1511 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1512 if (MCID.Opcode == ARM::PKHTB) { 1513 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); 1514 if (ShiftAmt == 32) 1515 ShiftAmt = 0; 1516 } 1517 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1518 Binary |= ShiftAmt << ARMII::ShiftShift; 1519 1520 emitWordLE(Binary); 1521 } 1522 1523 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { 1524 const MCInstrDesc &MCID = MI.getDesc(); 1525 1526 // Part of binary is determined by TableGen. 1527 unsigned Binary = getBinaryCodeForInstr(MI); 1528 1529 // Set the conditional execution predicate 1530 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1531 1532 // Encode Rd 1533 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 1534 1535 // Encode saturate bit position. 1536 unsigned Pos = MI.getOperand(1).getImm(); 1537 if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16) 1538 Pos -= 1; 1539 assert((Pos < 16 || (Pos < 32 && 1540 MCID.Opcode != ARM::SSAT16 && 1541 MCID.Opcode != ARM::USAT16)) && 1542 "saturate bit position out of range"); 1543 Binary |= Pos << 16; 1544 1545 // Encode Rm 1546 Binary |= getMachineOpValue(MI, 2); 1547 1548 // Encode shift_imm. 1549 if (MCID.getNumOperands() == 4) { 1550 unsigned ShiftOp = MI.getOperand(3).getImm(); 1551 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); 1552 if (Opc == ARM_AM::asr) 1553 Binary |= (1 << 6); 1554 unsigned ShiftAmt = MI.getOperand(3).getImm(); 1555 if (ShiftAmt == 32 && Opc == ARM_AM::asr) 1556 ShiftAmt = 0; 1557 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1558 Binary |= ShiftAmt << ARMII::ShiftShift; 1559 } 1560 1561 emitWordLE(Binary); 1562 } 1563 1564 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { 1565 const MCInstrDesc &MCID = MI.getDesc(); 1566 1567 if (MCID.Opcode == ARM::TPsoft) { 1568 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1569 } 1570 1571 // Part of binary is determined by TableGn. 1572 unsigned Binary = getBinaryCodeForInstr(MI); 1573 1574 if (MCID.Opcode == ARM::B) { 1575 Binary = 0xEA000000; 1576 } 1577 1578 // Set the conditional execution predicate 1579 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1580 1581 // Set signed_immed_24 field 1582 Binary |= getMachineOpValue(MI, 0); 1583 1584 emitWordLE(Binary); 1585 } 1586 1587 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { 1588 // Remember the base address of the inline jump table. 1589 uintptr_t JTBase = MCE.getCurrentPCValue(); 1590 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1591 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1592 << '\n'); 1593 1594 // Now emit the jump table entries. 1595 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1596 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1597 if (IsPIC) 1598 // DestBB address - JT base. 1599 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1600 else 1601 // Absolute DestBB address. 1602 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1603 emitWordLE(0); 1604 } 1605 } 1606 1607 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { 1608 const MCInstrDesc &MCID = MI.getDesc(); 1609 1610 // Handle jump tables. 1611 if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) { 1612 // First emit a ldr pc, [] instruction. 1613 emitDataProcessingInstruction(MI, ARM::PC); 1614 1615 // Then emit the inline jump table. 1616 unsigned JTIndex = 1617 (MCID.Opcode == ARM::BR_JTr) 1618 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1619 emitInlineJumpTable(JTIndex); 1620 return; 1621 } else if (MCID.Opcode == ARM::BR_JTm) { 1622 // First emit a ldr pc, [] instruction. 1623 emitLoadStoreInstruction(MI, ARM::PC); 1624 1625 // Then emit the inline jump table. 1626 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1627 return; 1628 } 1629 1630 // Part of binary is determined by TableGn. 1631 unsigned Binary = getBinaryCodeForInstr(MI); 1632 1633 // Set the conditional execution predicate 1634 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1635 1636 if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR) 1637 // The return register is LR. 1638 Binary |= getARMRegisterNumbering(ARM::LR); 1639 else 1640 // otherwise, set the return register 1641 Binary |= getMachineOpValue(MI, 0); 1642 1643 emitWordLE(Binary); 1644 } 1645 1646 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { 1647 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1648 unsigned Binary = 0; 1649 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD); 1650 RegD = getARMRegisterNumbering(RegD); 1651 if (!isSPVFP) { 1652 Binary |= (RegD & 0x0F) << ARMII::RegRdShift; 1653 Binary |= ((RegD & 0x10) >> 4) << ARMII::D_BitShift; 1654 } else { 1655 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1656 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1657 } 1658 return Binary; 1659 } 1660 1661 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { 1662 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1663 unsigned Binary = 0; 1664 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN); 1665 RegN = getARMRegisterNumbering(RegN); 1666 if (!isSPVFP) { 1667 Binary |= (RegN & 0x0F) << ARMII::RegRnShift; 1668 Binary |= ((RegN & 0x10) >> 4) << ARMII::N_BitShift; 1669 } else { 1670 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1671 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1672 } 1673 return Binary; 1674 } 1675 1676 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { 1677 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1678 unsigned Binary = 0; 1679 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM); 1680 RegM = getARMRegisterNumbering(RegM); 1681 if (!isSPVFP) { 1682 Binary |= (RegM & 0x0F); 1683 Binary |= ((RegM & 0x10) >> 4) << ARMII::M_BitShift; 1684 } else { 1685 Binary |= ((RegM & 0x1E) >> 1); 1686 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1687 } 1688 return Binary; 1689 } 1690 1691 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { 1692 const MCInstrDesc &MCID = MI.getDesc(); 1693 1694 // Part of binary is determined by TableGn. 1695 unsigned Binary = getBinaryCodeForInstr(MI); 1696 1697 // Set the conditional execution predicate 1698 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1699 1700 unsigned OpIdx = 0; 1701 1702 // Encode Dd / Sd. 1703 Binary |= encodeVFPRd(MI, OpIdx++); 1704 1705 // If this is a two-address operand, skip it, e.g. FMACD. 1706 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1707 ++OpIdx; 1708 1709 // Encode Dn / Sn. 1710 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1711 Binary |= encodeVFPRn(MI, OpIdx++); 1712 1713 if (OpIdx == MCID.getNumOperands() || 1714 MCID.OpInfo[OpIdx].isPredicate() || 1715 MCID.OpInfo[OpIdx].isOptionalDef()) { 1716 // FCMPEZD etc. has only one operand. 1717 emitWordLE(Binary); 1718 return; 1719 } 1720 1721 // Encode Dm / Sm. 1722 Binary |= encodeVFPRm(MI, OpIdx); 1723 1724 emitWordLE(Binary); 1725 } 1726 1727 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { 1728 const MCInstrDesc &MCID = MI.getDesc(); 1729 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1730 1731 // Part of binary is determined by TableGn. 1732 unsigned Binary = getBinaryCodeForInstr(MI); 1733 1734 // Set the conditional execution predicate 1735 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1736 1737 switch (Form) { 1738 default: break; 1739 case ARMII::VFPConv1Frm: 1740 case ARMII::VFPConv2Frm: 1741 case ARMII::VFPConv3Frm: 1742 // Encode Dd / Sd. 1743 Binary |= encodeVFPRd(MI, 0); 1744 break; 1745 case ARMII::VFPConv4Frm: 1746 // Encode Dn / Sn. 1747 Binary |= encodeVFPRn(MI, 0); 1748 break; 1749 case ARMII::VFPConv5Frm: 1750 // Encode Dm / Sm. 1751 Binary |= encodeVFPRm(MI, 0); 1752 break; 1753 } 1754 1755 switch (Form) { 1756 default: break; 1757 case ARMII::VFPConv1Frm: 1758 // Encode Dm / Sm. 1759 Binary |= encodeVFPRm(MI, 1); 1760 break; 1761 case ARMII::VFPConv2Frm: 1762 case ARMII::VFPConv3Frm: 1763 // Encode Dn / Sn. 1764 Binary |= encodeVFPRn(MI, 1); 1765 break; 1766 case ARMII::VFPConv4Frm: 1767 case ARMII::VFPConv5Frm: 1768 // Encode Dd / Sd. 1769 Binary |= encodeVFPRd(MI, 1); 1770 break; 1771 } 1772 1773 if (Form == ARMII::VFPConv5Frm) 1774 // Encode Dn / Sn. 1775 Binary |= encodeVFPRn(MI, 2); 1776 else if (Form == ARMII::VFPConv3Frm) 1777 // Encode Dm / Sm. 1778 Binary |= encodeVFPRm(MI, 2); 1779 1780 emitWordLE(Binary); 1781 } 1782 1783 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1784 // Part of binary is determined by TableGn. 1785 unsigned Binary = getBinaryCodeForInstr(MI); 1786 1787 // Set the conditional execution predicate 1788 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1789 1790 if (MI.getOpcode() == ARM::VLDRS || MI.getOpcode() == ARM::VLDRD || 1791 MI.getOpcode() == ARM::VSTRS || MI.getOpcode() == ARM::VSTRD){ 1792 emitWordLE(Binary); 1793 return; 1794 } 1795 1796 unsigned OpIdx = 0; 1797 1798 // Encode Dd / Sd. 1799 Binary |= encodeVFPRd(MI, OpIdx++); 1800 1801 // Encode address base. 1802 const MachineOperand &Base = MI.getOperand(OpIdx++); 1803 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1804 1805 // If there is a non-zero immediate offset, encode it. 1806 if (Base.isReg()) { 1807 const MachineOperand &Offset = MI.getOperand(OpIdx); 1808 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1809 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1810 Binary |= 1 << ARMII::U_BitShift; 1811 Binary |= ImmOffs; 1812 emitWordLE(Binary); 1813 return; 1814 } 1815 } 1816 1817 // If immediate offset is omitted, default to +0. 1818 Binary |= 1 << ARMII::U_BitShift; 1819 1820 emitWordLE(Binary); 1821 } 1822 1823 void 1824 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { 1825 const MCInstrDesc &MCID = MI.getDesc(); 1826 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1827 1828 // Part of binary is determined by TableGn. 1829 unsigned Binary = getBinaryCodeForInstr(MI); 1830 1831 // Set the conditional execution predicate 1832 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1833 1834 // Skip operand 0 of an instruction with base register update. 1835 unsigned OpIdx = 0; 1836 if (IsUpdating) 1837 ++OpIdx; 1838 1839 // Set base address operand 1840 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1841 1842 // Set addressing mode by modifying bits U(23) and P(24) 1843 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1844 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1845 1846 // Set bit W(21) 1847 if (IsUpdating) 1848 Binary |= 0x1 << ARMII::W_BitShift; 1849 1850 // First register is encoded in Dd. 1851 Binary |= encodeVFPRd(MI, OpIdx+2); 1852 1853 // Count the number of registers. 1854 unsigned NumRegs = 1; 1855 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { 1856 const MachineOperand &MO = MI.getOperand(i); 1857 if (!MO.isReg() || MO.isImplicit()) 1858 break; 1859 ++NumRegs; 1860 } 1861 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0) 1862 // Otherwise, it will be 0, in the case of 32-bit registers. 1863 if(Binary & 0x100) 1864 Binary |= NumRegs * 2; 1865 else 1866 Binary |= NumRegs; 1867 1868 emitWordLE(Binary); 1869 } 1870 1871 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) { 1872 unsigned Opcode = MI.getDesc().Opcode; 1873 // Part of binary is determined by TableGn. 1874 unsigned Binary = getBinaryCodeForInstr(MI); 1875 1876 if (Opcode == ARM::FCONSTS) { 1877 unsigned Imm = getMachineOpValue(MI, 1); 1878 Binary &= ~(0x780000 >> 19); 1879 Binary |= (Imm & 0x780000) >> 19; 1880 Binary &= ~(0x3800000 >> 7); 1881 Binary |= (Imm & 0x3800000) >> 7; 1882 Binary = VFPThumb2PostEncoder(MI, Binary); 1883 } 1884 1885 // Set the conditional execution predicate 1886 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1887 1888 emitWordLE(Binary); 1889 } 1890 1891 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) { 1892 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1893 unsigned Binary = 0; 1894 RegD = getARMRegisterNumbering(RegD); 1895 Binary |= (RegD & 0xf) << ARMII::RegRdShift; 1896 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; 1897 return Binary; 1898 } 1899 1900 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) { 1901 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1902 unsigned Binary = 0; 1903 RegN = getARMRegisterNumbering(RegN); 1904 Binary |= (RegN & 0xf) << ARMII::RegRnShift; 1905 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; 1906 return Binary; 1907 } 1908 1909 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) { 1910 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1911 unsigned Binary = 0; 1912 RegM = getARMRegisterNumbering(RegM); 1913 Binary |= (RegM & 0xf); 1914 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; 1915 return Binary; 1916 } 1917 1918 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON 1919 /// data-processing instruction to the corresponding Thumb encoding. 1920 static unsigned convertNEONDataProcToThumb(unsigned Binary) { 1921 assert((Binary & 0xfe000000) == 0xf2000000 && 1922 "not an ARM NEON data-processing instruction"); 1923 unsigned UBit = (Binary >> 24) & 1; 1924 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff); 1925 } 1926 1927 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { 1928 unsigned Binary = getBinaryCodeForInstr(MI); 1929 1930 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx; 1931 const MCInstrDesc &MCID = MI.getDesc(); 1932 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { 1933 RegTOpIdx = 0; 1934 RegNOpIdx = 1; 1935 LnOpIdx = 2; 1936 } else { // ARMII::NSetLnFrm 1937 RegTOpIdx = 2; 1938 RegNOpIdx = 0; 1939 LnOpIdx = 3; 1940 } 1941 1942 // Set the conditional execution predicate 1943 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1944 1945 unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); 1946 RegT = getARMRegisterNumbering(RegT); 1947 Binary |= (RegT << ARMII::RegRdShift); 1948 Binary |= encodeNEONRn(MI, RegNOpIdx); 1949 1950 unsigned LaneShift; 1951 if ((Binary & (1 << 22)) != 0) 1952 LaneShift = 0; // 8-bit elements 1953 else if ((Binary & (1 << 5)) != 0) 1954 LaneShift = 1; // 16-bit elements 1955 else 1956 LaneShift = 2; // 32-bit elements 1957 1958 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; 1959 unsigned Opc1 = Lane >> 2; 1960 unsigned Opc2 = Lane & 3; 1961 assert((Opc1 & 3) == 0 && "out-of-range lane number operand"); 1962 Binary |= (Opc1 << 21); 1963 Binary |= (Opc2 << 5); 1964 1965 emitWordLE(Binary); 1966 } 1967 1968 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { 1969 unsigned Binary = getBinaryCodeForInstr(MI); 1970 1971 // Set the conditional execution predicate 1972 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1973 1974 unsigned RegT = MI.getOperand(1).getReg(); 1975 RegT = getARMRegisterNumbering(RegT); 1976 Binary |= (RegT << ARMII::RegRdShift); 1977 Binary |= encodeNEONRn(MI, 0); 1978 emitWordLE(Binary); 1979 } 1980 1981 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { 1982 unsigned Binary = getBinaryCodeForInstr(MI); 1983 // Destination register is encoded in Dd. 1984 Binary |= encodeNEONRd(MI, 0); 1985 // Immediate fields: Op, Cmode, I, Imm3, Imm4 1986 unsigned Imm = MI.getOperand(1).getImm(); 1987 unsigned Op = (Imm >> 12) & 1; 1988 unsigned Cmode = (Imm >> 8) & 0xf; 1989 unsigned I = (Imm >> 7) & 1; 1990 unsigned Imm3 = (Imm >> 4) & 0x7; 1991 unsigned Imm4 = Imm & 0xf; 1992 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4; 1993 if (IsThumb) 1994 Binary = convertNEONDataProcToThumb(Binary); 1995 emitWordLE(Binary); 1996 } 1997 1998 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { 1999 const MCInstrDesc &MCID = MI.getDesc(); 2000 unsigned Binary = getBinaryCodeForInstr(MI); 2001 // Destination register is encoded in Dd; source register in Dm. 2002 unsigned OpIdx = 0; 2003 Binary |= encodeNEONRd(MI, OpIdx++); 2004 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 2005 ++OpIdx; 2006 Binary |= encodeNEONRm(MI, OpIdx); 2007 if (IsThumb) 2008 Binary = convertNEONDataProcToThumb(Binary); 2009 // FIXME: This does not handle VDUPfdf or VDUPfqf. 2010 emitWordLE(Binary); 2011 } 2012 2013 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { 2014 const MCInstrDesc &MCID = MI.getDesc(); 2015 unsigned Binary = getBinaryCodeForInstr(MI); 2016 // Destination register is encoded in Dd; source registers in Dn and Dm. 2017 unsigned OpIdx = 0; 2018 Binary |= encodeNEONRd(MI, OpIdx++); 2019 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 2020 ++OpIdx; 2021 Binary |= encodeNEONRn(MI, OpIdx++); 2022 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 2023 ++OpIdx; 2024 Binary |= encodeNEONRm(MI, OpIdx); 2025 if (IsThumb) 2026 Binary = convertNEONDataProcToThumb(Binary); 2027 // FIXME: This does not handle VMOVDneon or VMOVQ. 2028 emitWordLE(Binary); 2029 } 2030 2031 #include "ARMGenCodeEmitter.inc" 2032
