1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file performs vector type splitting and scalarization for LegalizeTypes. 11 // Scalarization is the act of changing a computation in an illegal one-element 12 // vector type to be a computation in its scalar element type. For example, 13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed 14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which 15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32 16 // types. 17 // Splitting is the act of changing a computation in an invalid vector type to 18 // be a computation in two vectors of half the size. For example, implementing 19 // <128 x f32> operations in terms of two <64 x f32> operations. 20 // 21 //===----------------------------------------------------------------------===// 22 23 #include "LegalizeTypes.h" 24 #include "llvm/CodeGen/PseudoSourceValue.h" 25 #include "llvm/Target/TargetData.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/raw_ostream.h" 28 using namespace llvm; 29 30 //===----------------------------------------------------------------------===// 31 // Result Vector Scalarization: <1 x ty> -> ty. 32 //===----------------------------------------------------------------------===// 33 34 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { 35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; 36 N->dump(&DAG); 37 dbgs() << "\n"); 38 SDValue R = SDValue(); 39 40 switch (N->getOpcode()) { 41 default: 42 #ifndef NDEBUG 43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": "; 44 N->dump(&DAG); 45 dbgs() << "\n"; 46 #endif 47 report_fatal_error("Do not know how to scalarize the result of this " 48 "operator!\n"); 49 50 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; 51 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 52 case ISD::BUILD_VECTOR: R = N->getOperand(0); break; 53 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 56 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 57 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 58 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 59 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; 60 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; 61 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; 62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break; 63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; 65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break; 66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; 67 case ISD::ANY_EXTEND: 68 case ISD::CTLZ: 69 case ISD::CTPOP: 70 case ISD::CTTZ: 71 case ISD::FABS: 72 case ISD::FCEIL: 73 case ISD::FCOS: 74 case ISD::FEXP: 75 case ISD::FEXP2: 76 case ISD::FFLOOR: 77 case ISD::FLOG: 78 case ISD::FLOG10: 79 case ISD::FLOG2: 80 case ISD::FNEARBYINT: 81 case ISD::FNEG: 82 case ISD::FP_EXTEND: 83 case ISD::FP_TO_SINT: 84 case ISD::FP_TO_UINT: 85 case ISD::FRINT: 86 case ISD::FSIN: 87 case ISD::FSQRT: 88 case ISD::FTRUNC: 89 case ISD::SIGN_EXTEND: 90 case ISD::SINT_TO_FP: 91 case ISD::TRUNCATE: 92 case ISD::UINT_TO_FP: 93 case ISD::ZERO_EXTEND: 94 R = ScalarizeVecRes_UnaryOp(N); 95 break; 96 97 case ISD::ADD: 98 case ISD::AND: 99 case ISD::FADD: 100 case ISD::FDIV: 101 case ISD::FMUL: 102 case ISD::FPOW: 103 case ISD::FREM: 104 case ISD::FSUB: 105 case ISD::MUL: 106 case ISD::OR: 107 case ISD::SDIV: 108 case ISD::SREM: 109 case ISD::SUB: 110 case ISD::UDIV: 111 case ISD::UREM: 112 case ISD::XOR: 113 case ISD::SHL: 114 case ISD::SRA: 115 case ISD::SRL: 116 R = ScalarizeVecRes_BinOp(N); 117 break; 118 } 119 120 // If R is null, the sub-method took care of registering the result. 121 if (R.getNode()) 122 SetScalarizedVector(SDValue(N, ResNo), R); 123 } 124 125 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { 126 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 127 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 129 LHS.getValueType(), LHS, RHS); 130 } 131 132 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N, 133 unsigned ResNo) { 134 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); 135 return GetScalarizedVector(Op); 136 } 137 138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) { 139 EVT NewVT = N->getValueType(0).getVectorElementType(); 140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 141 NewVT, N->getOperand(0)); 142 } 143 144 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { 145 EVT NewVT = N->getValueType(0).getVectorElementType(); 146 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); 147 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), 148 Op0, DAG.getValueType(NewVT), 149 DAG.getValueType(Op0.getValueType()), 150 N->getOperand(3), 151 N->getOperand(4), 152 cast<CvtRndSatSDNode>(N)->getCvtCode()); 153 } 154 155 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 156 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 157 N->getValueType(0).getVectorElementType(), 158 N->getOperand(0), N->getOperand(1)); 159 } 160 161 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) { 162 EVT NewVT = N->getValueType(0).getVectorElementType(); 163 SDValue Op = GetScalarizedVector(N->getOperand(0)); 164 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), 165 NewVT, Op, N->getOperand(1)); 166 } 167 168 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) { 169 SDValue Op = GetScalarizedVector(N->getOperand(0)); 170 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(), 171 Op.getValueType(), Op, N->getOperand(1)); 172 } 173 174 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { 175 // The value to insert may have a wider type than the vector element type, 176 // so be sure to truncate it to the element type if necessary. 177 SDValue Op = N->getOperand(1); 178 EVT EltVT = N->getValueType(0).getVectorElementType(); 179 if (Op.getValueType() != EltVT) 180 // FIXME: Can this happen for floating point types? 181 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op); 182 return Op; 183 } 184 185 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { 186 assert(N->isUnindexed() && "Indexed vector load?"); 187 188 SDValue Result = DAG.getLoad(ISD::UNINDEXED, 189 N->getExtensionType(), 190 N->getValueType(0).getVectorElementType(), 191 N->getDebugLoc(), 192 N->getChain(), N->getBasePtr(), 193 DAG.getUNDEF(N->getBasePtr().getValueType()), 194 N->getPointerInfo(), 195 N->getMemoryVT().getVectorElementType(), 196 N->isVolatile(), N->isNonTemporal(), 197 N->getOriginalAlignment()); 198 199 // Legalized the chain result - switch anything that used the old chain to 200 // use the new one. 201 ReplaceValueWith(SDValue(N, 1), Result.getValue(1)); 202 return Result; 203 } 204 205 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { 206 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. 207 EVT DestVT = N->getValueType(0).getVectorElementType(); 208 SDValue Op = GetScalarizedVector(N->getOperand(0)); 209 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op); 210 } 211 212 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) { 213 EVT EltVT = N->getValueType(0).getVectorElementType(); 214 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType(); 215 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 216 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT, 217 LHS, DAG.getValueType(ExtVT)); 218 } 219 220 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) { 221 // If the operand is wider than the vector element type then it is implicitly 222 // truncated. Make that explicit here. 223 EVT EltVT = N->getValueType(0).getVectorElementType(); 224 SDValue InOp = N->getOperand(0); 225 if (InOp.getValueType() != EltVT) 226 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp); 227 return InOp; 228 } 229 230 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) { 231 SDValue LHS = GetScalarizedVector(N->getOperand(1)); 232 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 233 LHS.getValueType(), N->getOperand(0), LHS, 234 GetScalarizedVector(N->getOperand(2))); 235 } 236 237 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) { 238 SDValue LHS = GetScalarizedVector(N->getOperand(2)); 239 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(), 240 N->getOperand(0), N->getOperand(1), 241 LHS, GetScalarizedVector(N->getOperand(3)), 242 N->getOperand(4)); 243 } 244 245 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) { 246 assert(N->getValueType(0).isVector() == 247 N->getOperand(0).getValueType().isVector() && 248 "Scalar/Vector type mismatch"); 249 250 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N); 251 252 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 253 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 254 DebugLoc DL = N->getDebugLoc(); 255 256 // Turn it into a scalar SETCC. 257 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); 258 } 259 260 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { 261 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 262 } 263 264 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { 265 // Figure out if the scalar is the LHS or RHS and return it. 266 SDValue Arg = N->getOperand(2).getOperand(0); 267 if (Arg.getOpcode() == ISD::UNDEF) 268 return DAG.getUNDEF(N->getValueType(0).getVectorElementType()); 269 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue(); 270 return GetScalarizedVector(N->getOperand(Op)); 271 } 272 273 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { 274 assert(N->getValueType(0).isVector() && 275 N->getOperand(0).getValueType().isVector() && 276 "Operand types must be vectors"); 277 278 SDValue LHS = GetScalarizedVector(N->getOperand(0)); 279 SDValue RHS = GetScalarizedVector(N->getOperand(1)); 280 EVT NVT = N->getValueType(0).getVectorElementType(); 281 DebugLoc DL = N->getDebugLoc(); 282 283 // Turn it into a scalar SETCC. 284 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, 285 N->getOperand(2)); 286 // Vectors may have a different boolean contents to scalars. Promote the 287 // value appropriately. 288 ISD::NodeType ExtendCode = 289 TargetLowering::getExtendForContent(TLI.getBooleanContents(true)); 290 return DAG.getNode(ExtendCode, DL, NVT, Res); 291 } 292 293 294 //===----------------------------------------------------------------------===// 295 // Operand Vector Scalarization <1 x ty> -> ty. 296 //===----------------------------------------------------------------------===// 297 298 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { 299 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; 300 N->dump(&DAG); 301 dbgs() << "\n"); 302 SDValue Res = SDValue(); 303 304 if (Res.getNode() == 0) { 305 switch (N->getOpcode()) { 306 default: 307 #ifndef NDEBUG 308 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": "; 309 N->dump(&DAG); 310 dbgs() << "\n"; 311 #endif 312 llvm_unreachable("Do not know how to scalarize this operator's operand!"); 313 case ISD::BITCAST: 314 Res = ScalarizeVecOp_BITCAST(N); 315 break; 316 case ISD::CONCAT_VECTORS: 317 Res = ScalarizeVecOp_CONCAT_VECTORS(N); 318 break; 319 case ISD::EXTRACT_VECTOR_ELT: 320 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); 321 break; 322 case ISD::STORE: 323 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); 324 break; 325 } 326 } 327 328 // If the result is null, the sub-method took care of registering results etc. 329 if (!Res.getNode()) return false; 330 331 // If the result is N, the sub-method updated N in place. Tell the legalizer 332 // core about this. 333 if (Res.getNode() == N) 334 return true; 335 336 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 337 "Invalid operand expansion"); 338 339 ReplaceValueWith(SDValue(N, 0), Res); 340 return false; 341 } 342 343 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs 344 /// to be scalarized, it must be <1 x ty>. Convert the element instead. 345 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) { 346 SDValue Elt = GetScalarizedVector(N->getOperand(0)); 347 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 348 N->getValueType(0), Elt); 349 } 350 351 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one - 352 /// use a BUILD_VECTOR instead. 353 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) { 354 SmallVector<SDValue, 8> Ops(N->getNumOperands()); 355 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) 356 Ops[i] = GetScalarizedVector(N->getOperand(i)); 357 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0), 358 &Ops[0], Ops.size()); 359 } 360 361 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to 362 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the 363 /// index. 364 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 365 SDValue Res = GetScalarizedVector(N->getOperand(0)); 366 if (Res.getValueType() != N->getValueType(0)) 367 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), 368 Res); 369 return Res; 370 } 371 372 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be 373 /// scalarized, it must be <1 x ty>. Just store the element. 374 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ 375 assert(N->isUnindexed() && "Indexed store of one-element vector?"); 376 assert(OpNo == 1 && "Do not know how to scalarize this operand!"); 377 DebugLoc dl = N->getDebugLoc(); 378 379 if (N->isTruncatingStore()) 380 return DAG.getTruncStore(N->getChain(), dl, 381 GetScalarizedVector(N->getOperand(1)), 382 N->getBasePtr(), N->getPointerInfo(), 383 N->getMemoryVT().getVectorElementType(), 384 N->isVolatile(), N->isNonTemporal(), 385 N->getAlignment()); 386 387 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)), 388 N->getBasePtr(), N->getPointerInfo(), 389 N->isVolatile(), N->isNonTemporal(), 390 N->getOriginalAlignment()); 391 } 392 393 394 //===----------------------------------------------------------------------===// 395 // Result Vector Splitting 396 //===----------------------------------------------------------------------===// 397 398 /// SplitVectorResult - This method is called when the specified result of the 399 /// specified node is found to need vector splitting. At this point, the node 400 /// may also have invalid operands or may have other results that need 401 /// legalization, we just know that (at least) one result needs vector 402 /// splitting. 403 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { 404 DEBUG(dbgs() << "Split node result: "; 405 N->dump(&DAG); 406 dbgs() << "\n"); 407 SDValue Lo, Hi; 408 409 switch (N->getOpcode()) { 410 default: 411 #ifndef NDEBUG 412 dbgs() << "SplitVectorResult #" << ResNo << ": "; 413 N->dump(&DAG); 414 dbgs() << "\n"; 415 #endif 416 llvm_unreachable("Do not know how to split the result of this operator!"); 417 418 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 419 case ISD::VSELECT: 420 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 421 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 422 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 423 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 424 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 425 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 426 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 427 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 428 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break; 429 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; 430 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break; 431 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break; 432 case ISD::LOAD: 433 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); 434 break; 435 case ISD::SETCC: 436 SplitVecRes_SETCC(N, Lo, Hi); 437 break; 438 case ISD::VECTOR_SHUFFLE: 439 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); 440 break; 441 442 case ISD::ANY_EXTEND: 443 case ISD::CONVERT_RNDSAT: 444 case ISD::CTLZ: 445 case ISD::CTPOP: 446 case ISD::CTTZ: 447 case ISD::FABS: 448 case ISD::FCEIL: 449 case ISD::FCOS: 450 case ISD::FEXP: 451 case ISD::FEXP2: 452 case ISD::FFLOOR: 453 case ISD::FLOG: 454 case ISD::FLOG10: 455 case ISD::FLOG2: 456 case ISD::FNEARBYINT: 457 case ISD::FNEG: 458 case ISD::FP_EXTEND: 459 case ISD::FP_ROUND: 460 case ISD::FP_TO_SINT: 461 case ISD::FP_TO_UINT: 462 case ISD::FRINT: 463 case ISD::FSIN: 464 case ISD::FSQRT: 465 case ISD::FTRUNC: 466 case ISD::SIGN_EXTEND: 467 case ISD::SINT_TO_FP: 468 case ISD::TRUNCATE: 469 case ISD::UINT_TO_FP: 470 case ISD::ZERO_EXTEND: 471 SplitVecRes_UnaryOp(N, Lo, Hi); 472 break; 473 474 case ISD::ADD: 475 case ISD::SUB: 476 case ISD::MUL: 477 case ISD::FADD: 478 case ISD::FSUB: 479 case ISD::FMUL: 480 case ISD::SDIV: 481 case ISD::UDIV: 482 case ISD::FDIV: 483 case ISD::FPOW: 484 case ISD::AND: 485 case ISD::OR: 486 case ISD::XOR: 487 case ISD::SHL: 488 case ISD::SRA: 489 case ISD::SRL: 490 case ISD::UREM: 491 case ISD::SREM: 492 case ISD::FREM: 493 SplitVecRes_BinOp(N, Lo, Hi); 494 break; 495 } 496 497 // If Lo/Hi is null, the sub-method took care of registering results etc. 498 if (Lo.getNode()) 499 SetSplitVector(SDValue(N, ResNo), Lo, Hi); 500 } 501 502 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo, 503 SDValue &Hi) { 504 SDValue LHSLo, LHSHi; 505 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 506 SDValue RHSLo, RHSHi; 507 GetSplitVector(N->getOperand(1), RHSLo, RHSHi); 508 DebugLoc dl = N->getDebugLoc(); 509 510 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo); 511 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi); 512 } 513 514 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, 515 SDValue &Hi) { 516 // We know the result is a vector. The input may be either a vector or a 517 // scalar value. 518 EVT LoVT, HiVT; 519 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 520 DebugLoc dl = N->getDebugLoc(); 521 522 SDValue InOp = N->getOperand(0); 523 EVT InVT = InOp.getValueType(); 524 525 // Handle some special cases efficiently. 526 switch (getTypeAction(InVT)) { 527 case TargetLowering::TypeLegal: 528 case TargetLowering::TypePromoteInteger: 529 case TargetLowering::TypeSoftenFloat: 530 case TargetLowering::TypeScalarizeVector: 531 case TargetLowering::TypeWidenVector: 532 break; 533 case TargetLowering::TypeExpandInteger: 534 case TargetLowering::TypeExpandFloat: 535 // A scalar to vector conversion, where the scalar needs expansion. 536 // If the vector is being split in two then we can just convert the 537 // expanded pieces. 538 if (LoVT == HiVT) { 539 GetExpandedOp(InOp, Lo, Hi); 540 if (TLI.isBigEndian()) 541 std::swap(Lo, Hi); 542 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 543 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 544 return; 545 } 546 break; 547 case TargetLowering::TypeSplitVector: 548 // If the input is a vector that needs to be split, convert each split 549 // piece of the input now. 550 GetSplitVector(InOp, Lo, Hi); 551 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 552 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 553 return; 554 } 555 556 // In the general case, convert the input to an integer and split it by hand. 557 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits()); 558 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits()); 559 if (TLI.isBigEndian()) 560 std::swap(LoIntVT, HiIntVT); 561 562 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); 563 564 if (TLI.isBigEndian()) 565 std::swap(Lo, Hi); 566 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 567 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 568 } 569 570 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, 571 SDValue &Hi) { 572 EVT LoVT, HiVT; 573 DebugLoc dl = N->getDebugLoc(); 574 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 575 unsigned LoNumElts = LoVT.getVectorNumElements(); 576 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts); 577 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); 578 579 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end()); 580 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); 581 } 582 583 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, 584 SDValue &Hi) { 585 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 586 DebugLoc dl = N->getDebugLoc(); 587 unsigned NumSubvectors = N->getNumOperands() / 2; 588 if (NumSubvectors == 1) { 589 Lo = N->getOperand(0); 590 Hi = N->getOperand(1); 591 return; 592 } 593 594 EVT LoVT, HiVT; 595 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 596 597 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); 598 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); 599 600 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end()); 601 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size()); 602 } 603 604 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, 605 SDValue &Hi) { 606 SDValue Vec = N->getOperand(0); 607 SDValue Idx = N->getOperand(1); 608 DebugLoc dl = N->getDebugLoc(); 609 610 EVT LoVT, HiVT; 611 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 612 613 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); 614 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 615 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, 616 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements())); 617 } 618 619 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, 620 SDValue &Hi) { 621 DebugLoc dl = N->getDebugLoc(); 622 GetSplitVector(N->getOperand(0), Lo, Hi); 623 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1)); 624 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1)); 625 } 626 627 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo, 628 SDValue &Hi) { 629 SDValue LHSLo, LHSHi; 630 GetSplitVector(N->getOperand(0), LHSLo, LHSHi); 631 DebugLoc dl = N->getDebugLoc(); 632 633 EVT LoVT, HiVT; 634 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT); 635 636 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, 637 DAG.getValueType(LoVT)); 638 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, 639 DAG.getValueType(HiVT)); 640 } 641 642 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, 643 SDValue &Hi) { 644 SDValue Vec = N->getOperand(0); 645 SDValue Elt = N->getOperand(1); 646 SDValue Idx = N->getOperand(2); 647 DebugLoc dl = N->getDebugLoc(); 648 GetSplitVector(Vec, Lo, Hi); 649 650 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 651 unsigned IdxVal = CIdx->getZExtValue(); 652 unsigned LoNumElts = Lo.getValueType().getVectorNumElements(); 653 if (IdxVal < LoNumElts) 654 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 655 Lo.getValueType(), Lo, Elt, Idx); 656 else 657 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, 658 DAG.getIntPtrConstant(IdxVal - LoNumElts)); 659 return; 660 } 661 662 // Spill the vector to the stack. 663 EVT VecVT = Vec.getValueType(); 664 EVT EltVT = VecVT.getVectorElementType(); 665 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 666 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 667 MachinePointerInfo(), false, false, 0); 668 669 // Store the new element. This may be larger than the vector element type, 670 // so use a truncating store. 671 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 672 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); 673 unsigned Alignment = 674 TLI.getTargetData()->getPrefTypeAlignment(VecType); 675 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT, 676 false, false, 0); 677 678 // Load the Lo part from the stack slot. 679 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 680 false, false, 0); 681 682 // Increment the pointer to the other part. 683 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8; 684 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 685 DAG.getIntPtrConstant(IncrementSize)); 686 687 // Load the Hi part from the stack slot. 688 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), 689 false, false, MinAlign(Alignment, IncrementSize)); 690 } 691 692 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, 693 SDValue &Hi) { 694 EVT LoVT, HiVT; 695 DebugLoc dl = N->getDebugLoc(); 696 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 697 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); 698 Hi = DAG.getUNDEF(HiVT); 699 } 700 701 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, 702 SDValue &Hi) { 703 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); 704 EVT LoVT, HiVT; 705 DebugLoc dl = LD->getDebugLoc(); 706 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); 707 708 ISD::LoadExtType ExtType = LD->getExtensionType(); 709 SDValue Ch = LD->getChain(); 710 SDValue Ptr = LD->getBasePtr(); 711 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 712 EVT MemoryVT = LD->getMemoryVT(); 713 unsigned Alignment = LD->getOriginalAlignment(); 714 bool isVolatile = LD->isVolatile(); 715 bool isNonTemporal = LD->isNonTemporal(); 716 717 EVT LoMemVT, HiMemVT; 718 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 719 720 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, 721 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal, 722 Alignment); 723 724 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 725 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 726 DAG.getIntPtrConstant(IncrementSize)); 727 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, 728 LD->getPointerInfo().getWithOffset(IncrementSize), 729 HiMemVT, isVolatile, isNonTemporal, Alignment); 730 731 // Build a factor node to remember that this load is independent of the 732 // other one. 733 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 734 Hi.getValue(1)); 735 736 // Legalized the chain result - switch anything that used the old chain to 737 // use the new one. 738 ReplaceValueWith(SDValue(LD, 1), Ch); 739 } 740 741 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) { 742 assert(N->getValueType(0).isVector() && 743 N->getOperand(0).getValueType().isVector() && 744 "Operand types must be vectors"); 745 746 EVT LoVT, HiVT; 747 DebugLoc DL = N->getDebugLoc(); 748 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 749 750 // Split the input. 751 EVT InVT = N->getOperand(0).getValueType(); 752 SDValue LL, LH, RL, RH; 753 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 754 LoVT.getVectorNumElements()); 755 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 756 DAG.getIntPtrConstant(0)); 757 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), 758 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 759 760 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 761 DAG.getIntPtrConstant(0)); 762 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), 763 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 764 765 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2)); 766 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2)); 767 } 768 769 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, 770 SDValue &Hi) { 771 // Get the dest types - they may not match the input types, e.g. int_to_fp. 772 EVT LoVT, HiVT; 773 DebugLoc dl = N->getDebugLoc(); 774 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); 775 776 // Split the input. 777 EVT InVT = N->getOperand(0).getValueType(); 778 switch (getTypeAction(InVT)) { 779 default: llvm_unreachable("Unexpected type action!"); 780 case TargetLowering::TypeLegal: { 781 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 782 LoVT.getVectorNumElements()); 783 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 784 DAG.getIntPtrConstant(0)); 785 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), 786 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 787 break; 788 } 789 case TargetLowering::TypePromoteInteger: { 790 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 791 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), 792 InOp.getValueType().getVectorElementType(), 793 LoVT.getVectorNumElements()); 794 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 795 DAG.getIntPtrConstant(0)); 796 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 797 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 798 break; 799 } 800 case TargetLowering::TypeSplitVector: 801 GetSplitVector(N->getOperand(0), Lo, Hi); 802 break; 803 case TargetLowering::TypeWidenVector: { 804 // If the result needs to be split and the input needs to be widened, 805 // the two types must have different lengths. Use the widened result 806 // and extract from it to do the split. 807 SDValue InOp = GetWidenedVector(N->getOperand(0)); 808 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), 809 LoVT.getVectorNumElements()); 810 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 811 DAG.getIntPtrConstant(0)); 812 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, 813 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 814 break; 815 } 816 } 817 818 if (N->getOpcode() == ISD::FP_ROUND) { 819 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1)); 820 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1)); 821 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) { 822 SDValue DTyOpLo = DAG.getValueType(LoVT); 823 SDValue DTyOpHi = DAG.getValueType(HiVT); 824 SDValue STyOpLo = DAG.getValueType(Lo.getValueType()); 825 SDValue STyOpHi = DAG.getValueType(Hi.getValueType()); 826 SDValue RndOp = N->getOperand(3); 827 SDValue SatOp = N->getOperand(4); 828 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 829 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp, 830 CvtCode); 831 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp, 832 CvtCode); 833 } else { 834 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo); 835 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi); 836 } 837 } 838 839 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, 840 SDValue &Lo, SDValue &Hi) { 841 // The low and high parts of the original input give four input vectors. 842 SDValue Inputs[4]; 843 DebugLoc dl = N->getDebugLoc(); 844 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); 845 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); 846 EVT NewVT = Inputs[0].getValueType(); 847 unsigned NewElts = NewVT.getVectorNumElements(); 848 849 // If Lo or Hi uses elements from at most two of the four input vectors, then 850 // express it as a vector shuffle of those two inputs. Otherwise extract the 851 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 852 SmallVector<int, 16> Ops; 853 for (unsigned High = 0; High < 2; ++High) { 854 SDValue &Output = High ? Hi : Lo; 855 856 // Build a shuffle mask for the output, discovering on the fly which 857 // input vectors to use as shuffle operands (recorded in InputUsed). 858 // If building a suitable shuffle vector proves too hard, then bail 859 // out with useBuildVector set. 860 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered. 861 unsigned FirstMaskIdx = High * NewElts; 862 bool useBuildVector = false; 863 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 864 // The mask element. This indexes into the input. 865 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 866 867 // The input vector this mask element indexes into. 868 unsigned Input = (unsigned)Idx / NewElts; 869 870 if (Input >= array_lengthof(Inputs)) { 871 // The mask element does not index into any input vector. 872 Ops.push_back(-1); 873 continue; 874 } 875 876 // Turn the index into an offset from the start of the input vector. 877 Idx -= Input * NewElts; 878 879 // Find or create a shuffle vector operand to hold this input. 880 unsigned OpNo; 881 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 882 if (InputUsed[OpNo] == Input) { 883 // This input vector is already an operand. 884 break; 885 } else if (InputUsed[OpNo] == -1U) { 886 // Create a new operand for this input vector. 887 InputUsed[OpNo] = Input; 888 break; 889 } 890 } 891 892 if (OpNo >= array_lengthof(InputUsed)) { 893 // More than two input vectors used! Give up on trying to create a 894 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 895 useBuildVector = true; 896 break; 897 } 898 899 // Add the mask index for the new shuffle vector. 900 Ops.push_back(Idx + OpNo * NewElts); 901 } 902 903 if (useBuildVector) { 904 EVT EltVT = NewVT.getVectorElementType(); 905 SmallVector<SDValue, 16> SVOps; 906 907 // Extract the input elements by hand. 908 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 909 // The mask element. This indexes into the input. 910 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset); 911 912 // The input vector this mask element indexes into. 913 unsigned Input = (unsigned)Idx / NewElts; 914 915 if (Input >= array_lengthof(Inputs)) { 916 // The mask element is "undef" or indexes off the end of the input. 917 SVOps.push_back(DAG.getUNDEF(EltVT)); 918 continue; 919 } 920 921 // Turn the index into an offset from the start of the input vector. 922 Idx -= Input * NewElts; 923 924 // Extract the vector element by hand. 925 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 926 Inputs[Input], DAG.getIntPtrConstant(Idx))); 927 } 928 929 // Construct the Lo/Hi output using a BUILD_VECTOR. 930 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size()); 931 } else if (InputUsed[0] == -1U) { 932 // No input vectors were used! The result is undefined. 933 Output = DAG.getUNDEF(NewVT); 934 } else { 935 SDValue Op0 = Inputs[InputUsed[0]]; 936 // If only one input was used, use an undefined vector for the other. 937 SDValue Op1 = InputUsed[1] == -1U ? 938 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]]; 939 // At least one input vector was used. Create a new shuffle vector. 940 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]); 941 } 942 943 Ops.clear(); 944 } 945 } 946 947 948 //===----------------------------------------------------------------------===// 949 // Operand Vector Splitting 950 //===----------------------------------------------------------------------===// 951 952 /// SplitVectorOperand - This method is called when the specified operand of the 953 /// specified node is found to need vector splitting. At this point, all of the 954 /// result types of the node are known to be legal, but other operands of the 955 /// node may need legalization as well as the specified one. 956 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { 957 DEBUG(dbgs() << "Split node operand: "; 958 N->dump(&DAG); 959 dbgs() << "\n"); 960 SDValue Res = SDValue(); 961 962 if (Res.getNode() == 0) { 963 switch (N->getOpcode()) { 964 default: 965 #ifndef NDEBUG 966 dbgs() << "SplitVectorOperand Op #" << OpNo << ": "; 967 N->dump(&DAG); 968 dbgs() << "\n"; 969 #endif 970 llvm_unreachable("Do not know how to split this operator's operand!"); 971 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break; 972 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break; 973 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; 974 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; 975 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; 976 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; 977 case ISD::STORE: 978 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); 979 break; 980 981 case ISD::CTTZ: 982 case ISD::CTLZ: 983 case ISD::CTPOP: 984 case ISD::FP_EXTEND: 985 case ISD::FP_TO_SINT: 986 case ISD::FP_TO_UINT: 987 case ISD::SINT_TO_FP: 988 case ISD::UINT_TO_FP: 989 case ISD::FTRUNC: 990 case ISD::TRUNCATE: 991 case ISD::SIGN_EXTEND: 992 case ISD::ZERO_EXTEND: 993 case ISD::ANY_EXTEND: 994 Res = SplitVecOp_UnaryOp(N); 995 break; 996 } 997 } 998 999 // If the result is null, the sub-method took care of registering results etc. 1000 if (!Res.getNode()) return false; 1001 1002 // If the result is N, the sub-method updated N in place. Tell the legalizer 1003 // core about this. 1004 if (Res.getNode() == N) 1005 return true; 1006 1007 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1008 "Invalid operand expansion"); 1009 1010 ReplaceValueWith(SDValue(N, 0), Res); 1011 return false; 1012 } 1013 1014 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) { 1015 // The result has a legal vector type, but the input needs splitting. 1016 EVT ResVT = N->getValueType(0); 1017 SDValue Lo, Hi; 1018 DebugLoc dl = N->getDebugLoc(); 1019 GetSplitVector(N->getOperand(0), Lo, Hi); 1020 EVT InVT = Lo.getValueType(); 1021 1022 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1023 InVT.getVectorNumElements()); 1024 1025 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); 1026 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); 1027 1028 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); 1029 } 1030 1031 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) { 1032 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will 1033 // end up being split all the way down to individual components. Convert the 1034 // split pieces into integers and reassemble. 1035 SDValue Lo, Hi; 1036 GetSplitVector(N->getOperand(0), Lo, Hi); 1037 Lo = BitConvertToInteger(Lo); 1038 Hi = BitConvertToInteger(Hi); 1039 1040 if (TLI.isBigEndian()) 1041 std::swap(Lo, Hi); 1042 1043 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0), 1044 JoinIntegers(Lo, Hi)); 1045 } 1046 1047 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 1048 // We know that the extracted result type is legal. 1049 EVT SubVT = N->getValueType(0); 1050 SDValue Idx = N->getOperand(1); 1051 DebugLoc dl = N->getDebugLoc(); 1052 SDValue Lo, Hi; 1053 GetSplitVector(N->getOperand(0), Lo, Hi); 1054 1055 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1056 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1057 1058 if (IdxVal < LoElts) { 1059 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts && 1060 "Extracted subvector crosses vector split!"); 1061 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); 1062 } else { 1063 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, 1064 DAG.getConstant(IdxVal - LoElts, Idx.getValueType())); 1065 } 1066 } 1067 1068 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 1069 SDValue Vec = N->getOperand(0); 1070 SDValue Idx = N->getOperand(1); 1071 EVT VecVT = Vec.getValueType(); 1072 1073 if (isa<ConstantSDNode>(Idx)) { 1074 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1075 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"); 1076 1077 SDValue Lo, Hi; 1078 GetSplitVector(Vec, Lo, Hi); 1079 1080 uint64_t LoElts = Lo.getValueType().getVectorNumElements(); 1081 1082 if (IdxVal < LoElts) 1083 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0); 1084 return SDValue(DAG.UpdateNodeOperands(N, Hi, 1085 DAG.getConstant(IdxVal - LoElts, 1086 Idx.getValueType())), 0); 1087 } 1088 1089 // Store the vector to the stack. 1090 EVT EltVT = VecVT.getVectorElementType(); 1091 DebugLoc dl = N->getDebugLoc(); 1092 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 1093 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1094 MachinePointerInfo(), false, false, 0); 1095 1096 // Load back the required element. 1097 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); 1098 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, 1099 MachinePointerInfo(), EltVT, false, false, 0); 1100 } 1101 1102 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { 1103 assert(N->isUnindexed() && "Indexed store of vector?"); 1104 assert(OpNo == 1 && "Can only split the stored value"); 1105 DebugLoc DL = N->getDebugLoc(); 1106 1107 bool isTruncating = N->isTruncatingStore(); 1108 SDValue Ch = N->getChain(); 1109 SDValue Ptr = N->getBasePtr(); 1110 EVT MemoryVT = N->getMemoryVT(); 1111 unsigned Alignment = N->getOriginalAlignment(); 1112 bool isVol = N->isVolatile(); 1113 bool isNT = N->isNonTemporal(); 1114 SDValue Lo, Hi; 1115 GetSplitVector(N->getOperand(1), Lo, Hi); 1116 1117 EVT LoMemVT, HiMemVT; 1118 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); 1119 1120 unsigned IncrementSize = LoMemVT.getSizeInBits()/8; 1121 1122 if (isTruncating) 1123 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1124 LoMemVT, isVol, isNT, Alignment); 1125 else 1126 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), 1127 isVol, isNT, Alignment); 1128 1129 // Increment the pointer to the other half. 1130 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, 1131 DAG.getIntPtrConstant(IncrementSize)); 1132 1133 if (isTruncating) 1134 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr, 1135 N->getPointerInfo().getWithOffset(IncrementSize), 1136 HiMemVT, isVol, isNT, Alignment); 1137 else 1138 Hi = DAG.getStore(Ch, DL, Hi, Ptr, 1139 N->getPointerInfo().getWithOffset(IncrementSize), 1140 isVol, isNT, Alignment); 1141 1142 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); 1143 } 1144 1145 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) { 1146 DebugLoc DL = N->getDebugLoc(); 1147 1148 // The input operands all must have the same type, and we know the result the 1149 // result type is valid. Convert this to a buildvector which extracts all the 1150 // input elements. 1151 // TODO: If the input elements are power-two vectors, we could convert this to 1152 // a new CONCAT_VECTORS node with elements that are half-wide. 1153 SmallVector<SDValue, 32> Elts; 1154 EVT EltVT = N->getValueType(0).getVectorElementType(); 1155 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1156 SDValue Op = N->getOperand(op); 1157 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements(); 1158 i != e; ++i) { 1159 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, 1160 Op, DAG.getIntPtrConstant(i))); 1161 1162 } 1163 } 1164 1165 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), 1166 &Elts[0], Elts.size()); 1167 } 1168 1169 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) { 1170 assert(N->getValueType(0).isVector() && 1171 N->getOperand(0).getValueType().isVector() && 1172 "Operand types must be vectors"); 1173 // The result has a legal vector type, but the input needs splitting. 1174 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes; 1175 DebugLoc DL = N->getDebugLoc(); 1176 GetSplitVector(N->getOperand(0), Lo0, Hi0); 1177 GetSplitVector(N->getOperand(1), Lo1, Hi1); 1178 unsigned PartElements = Lo0.getValueType().getVectorNumElements(); 1179 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements); 1180 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements); 1181 1182 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2)); 1183 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2)); 1184 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes); 1185 return PromoteTargetBoolean(Con, N->getValueType(0)); 1186 } 1187 1188 1189 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) { 1190 // The result has a legal vector type, but the input needs splitting. 1191 EVT ResVT = N->getValueType(0); 1192 SDValue Lo, Hi; 1193 DebugLoc DL = N->getDebugLoc(); 1194 GetSplitVector(N->getOperand(0), Lo, Hi); 1195 EVT InVT = Lo.getValueType(); 1196 1197 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(), 1198 InVT.getVectorNumElements()); 1199 1200 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1)); 1201 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1)); 1202 1203 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); 1204 } 1205 1206 1207 1208 //===----------------------------------------------------------------------===// 1209 // Result Vector Widening 1210 //===----------------------------------------------------------------------===// 1211 1212 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { 1213 DEBUG(dbgs() << "Widen node result " << ResNo << ": "; 1214 N->dump(&DAG); 1215 dbgs() << "\n"); 1216 1217 // See if the target wants to custom widen this node. 1218 if (CustomWidenLowerNode(N, N->getValueType(ResNo))) 1219 return; 1220 1221 SDValue Res = SDValue(); 1222 switch (N->getOpcode()) { 1223 default: 1224 #ifndef NDEBUG 1225 dbgs() << "WidenVectorResult #" << ResNo << ": "; 1226 N->dump(&DAG); 1227 dbgs() << "\n"; 1228 #endif 1229 llvm_unreachable("Do not know how to widen the result of this operator!"); 1230 1231 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break; 1232 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break; 1233 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; 1234 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; 1235 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break; 1236 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; 1237 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break; 1238 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; 1239 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break; 1240 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break; 1241 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break; 1242 case ISD::VSELECT: 1243 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break; 1244 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; 1245 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break; 1246 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break; 1247 case ISD::VECTOR_SHUFFLE: 1248 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); 1249 break; 1250 case ISD::ADD: 1251 case ISD::AND: 1252 case ISD::BSWAP: 1253 case ISD::FADD: 1254 case ISD::FCOPYSIGN: 1255 case ISD::FDIV: 1256 case ISD::FMUL: 1257 case ISD::FPOW: 1258 case ISD::FREM: 1259 case ISD::FSUB: 1260 case ISD::MUL: 1261 case ISD::MULHS: 1262 case ISD::MULHU: 1263 case ISD::OR: 1264 case ISD::SDIV: 1265 case ISD::SREM: 1266 case ISD::UDIV: 1267 case ISD::UREM: 1268 case ISD::SUB: 1269 case ISD::XOR: 1270 Res = WidenVecRes_Binary(N); 1271 break; 1272 1273 case ISD::FPOWI: 1274 Res = WidenVecRes_POWI(N); 1275 break; 1276 1277 case ISD::SHL: 1278 case ISD::SRA: 1279 case ISD::SRL: 1280 Res = WidenVecRes_Shift(N); 1281 break; 1282 1283 case ISD::ANY_EXTEND: 1284 case ISD::FP_EXTEND: 1285 case ISD::FP_ROUND: 1286 case ISD::FP_TO_SINT: 1287 case ISD::FP_TO_UINT: 1288 case ISD::SIGN_EXTEND: 1289 case ISD::SINT_TO_FP: 1290 case ISD::TRUNCATE: 1291 case ISD::UINT_TO_FP: 1292 case ISD::ZERO_EXTEND: 1293 Res = WidenVecRes_Convert(N); 1294 break; 1295 1296 case ISD::CTLZ: 1297 case ISD::CTPOP: 1298 case ISD::CTTZ: 1299 case ISD::FABS: 1300 case ISD::FCEIL: 1301 case ISD::FCOS: 1302 case ISD::FEXP: 1303 case ISD::FEXP2: 1304 case ISD::FFLOOR: 1305 case ISD::FLOG: 1306 case ISD::FLOG10: 1307 case ISD::FLOG2: 1308 case ISD::FNEARBYINT: 1309 case ISD::FNEG: 1310 case ISD::FRINT: 1311 case ISD::FSIN: 1312 case ISD::FSQRT: 1313 case ISD::FTRUNC: 1314 Res = WidenVecRes_Unary(N); 1315 break; 1316 } 1317 1318 // If Res is null, the sub-method took care of registering the result. 1319 if (Res.getNode()) 1320 SetWidenedVector(SDValue(N, ResNo), Res); 1321 } 1322 1323 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) { 1324 // Binary op widening. 1325 unsigned Opcode = N->getOpcode(); 1326 DebugLoc dl = N->getDebugLoc(); 1327 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1328 EVT WidenEltVT = WidenVT.getVectorElementType(); 1329 EVT VT = WidenVT; 1330 unsigned NumElts = VT.getVectorNumElements(); 1331 while (!TLI.isTypeLegal(VT) && NumElts != 1) { 1332 NumElts = NumElts / 2; 1333 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1334 } 1335 1336 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) { 1337 // Operation doesn't trap so just widen as normal. 1338 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1339 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1340 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2); 1341 } 1342 1343 // No legal vector version so unroll the vector operation and then widen. 1344 if (NumElts == 1) 1345 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()); 1346 1347 // Since the operation can trap, apply operation on the original vector. 1348 EVT MaxVT = VT; 1349 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1350 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1351 unsigned CurNumElts = N->getValueType(0).getVectorNumElements(); 1352 1353 SmallVector<SDValue, 16> ConcatOps(CurNumElts); 1354 unsigned ConcatEnd = 0; // Current ConcatOps index. 1355 int Idx = 0; // Current Idx into input vectors. 1356 1357 // NumElts := greatest legal vector size (at most WidenVT) 1358 // while (orig. vector has unhandled elements) { 1359 // take munches of size NumElts from the beginning and add to ConcatOps 1360 // NumElts := next smaller supported vector size or 1 1361 // } 1362 while (CurNumElts != 0) { 1363 while (CurNumElts >= NumElts) { 1364 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, 1365 DAG.getIntPtrConstant(Idx)); 1366 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, 1367 DAG.getIntPtrConstant(Idx)); 1368 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2); 1369 Idx += NumElts; 1370 CurNumElts -= NumElts; 1371 } 1372 do { 1373 NumElts = NumElts / 2; 1374 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); 1375 } while (!TLI.isTypeLegal(VT) && NumElts != 1); 1376 1377 if (NumElts == 1) { 1378 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) { 1379 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1380 InOp1, DAG.getIntPtrConstant(Idx)); 1381 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, 1382 InOp2, DAG.getIntPtrConstant(Idx)); 1383 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, 1384 EOp1, EOp2); 1385 } 1386 CurNumElts = 0; 1387 } 1388 } 1389 1390 // Check to see if we have a single operation with the widen type. 1391 if (ConcatEnd == 1) { 1392 VT = ConcatOps[0].getValueType(); 1393 if (VT == WidenVT) 1394 return ConcatOps[0]; 1395 } 1396 1397 // while (Some element of ConcatOps is not of type MaxVT) { 1398 // From the end of ConcatOps, collect elements of the same type and put 1399 // them into an op of the next larger supported type 1400 // } 1401 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) { 1402 Idx = ConcatEnd - 1; 1403 VT = ConcatOps[Idx--].getValueType(); 1404 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT) 1405 Idx--; 1406 1407 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1; 1408 EVT NextVT; 1409 do { 1410 NextSize *= 2; 1411 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); 1412 } while (!TLI.isTypeLegal(NextVT)); 1413 1414 if (!VT.isVector()) { 1415 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT 1416 SDValue VecOp = DAG.getUNDEF(NextVT); 1417 unsigned NumToInsert = ConcatEnd - Idx - 1; 1418 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { 1419 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, 1420 ConcatOps[OpIdx], DAG.getIntPtrConstant(i)); 1421 } 1422 ConcatOps[Idx+1] = VecOp; 1423 ConcatEnd = Idx + 2; 1424 } else { 1425 // Vector type, create a CONCAT_VECTORS of type NextVT 1426 SDValue undefVec = DAG.getUNDEF(VT); 1427 unsigned OpsToConcat = NextSize/VT.getVectorNumElements(); 1428 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat); 1429 unsigned RealVals = ConcatEnd - Idx - 1; 1430 unsigned SubConcatEnd = 0; 1431 unsigned SubConcatIdx = Idx + 1; 1432 while (SubConcatEnd < RealVals) 1433 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx]; 1434 while (SubConcatEnd < OpsToConcat) 1435 SubConcatOps[SubConcatEnd++] = undefVec; 1436 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1437 NextVT, &SubConcatOps[0], 1438 OpsToConcat); 1439 ConcatEnd = SubConcatIdx + 1; 1440 } 1441 } 1442 1443 // Check to see if we have a single operation with the widen type. 1444 if (ConcatEnd == 1) { 1445 VT = ConcatOps[0].getValueType(); 1446 if (VT == WidenVT) 1447 return ConcatOps[0]; 1448 } 1449 1450 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT 1451 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements(); 1452 if (NumOps != ConcatEnd ) { 1453 SDValue UndefVal = DAG.getUNDEF(MaxVT); 1454 for (unsigned j = ConcatEnd; j < NumOps; ++j) 1455 ConcatOps[j] = UndefVal; 1456 } 1457 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps); 1458 } 1459 1460 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { 1461 SDValue InOp = N->getOperand(0); 1462 DebugLoc DL = N->getDebugLoc(); 1463 1464 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1465 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1466 1467 EVT InVT = InOp.getValueType(); 1468 EVT InEltVT = InVT.getVectorElementType(); 1469 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1470 1471 unsigned Opcode = N->getOpcode(); 1472 unsigned InVTNumElts = InVT.getVectorNumElements(); 1473 1474 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1475 InOp = GetWidenedVector(N->getOperand(0)); 1476 InVT = InOp.getValueType(); 1477 InVTNumElts = InVT.getVectorNumElements(); 1478 if (InVTNumElts == WidenNumElts) { 1479 if (N->getNumOperands() == 1) 1480 return DAG.getNode(Opcode, DL, WidenVT, InOp); 1481 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1)); 1482 } 1483 } 1484 1485 if (TLI.isTypeLegal(InWidenVT)) { 1486 // Because the result and the input are different vector types, widening 1487 // the result could create a legal type but widening the input might make 1488 // it an illegal type that might lead to repeatedly splitting the input 1489 // and then widening it. To avoid this, we widen the input only if 1490 // it results in a legal type. 1491 if (WidenNumElts % InVTNumElts == 0) { 1492 // Widen the input and call convert on the widened input vector. 1493 unsigned NumConcat = WidenNumElts/InVTNumElts; 1494 SmallVector<SDValue, 16> Ops(NumConcat); 1495 Ops[0] = InOp; 1496 SDValue UndefVal = DAG.getUNDEF(InVT); 1497 for (unsigned i = 1; i != NumConcat; ++i) 1498 Ops[i] = UndefVal; 1499 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, 1500 &Ops[0], NumConcat); 1501 if (N->getNumOperands() == 1) 1502 return DAG.getNode(Opcode, DL, WidenVT, InVec); 1503 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1)); 1504 } 1505 1506 if (InVTNumElts % WidenNumElts == 0) { 1507 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, 1508 InOp, DAG.getIntPtrConstant(0)); 1509 // Extract the input and convert the shorten input vector. 1510 if (N->getNumOperands() == 1) 1511 return DAG.getNode(Opcode, DL, WidenVT, InVal); 1512 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1)); 1513 } 1514 } 1515 1516 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1517 SmallVector<SDValue, 16> Ops(WidenNumElts); 1518 EVT EltVT = WidenVT.getVectorElementType(); 1519 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1520 unsigned i; 1521 for (i=0; i < MinElts; ++i) { 1522 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp, 1523 DAG.getIntPtrConstant(i)); 1524 if (N->getNumOperands() == 1) 1525 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val); 1526 else 1527 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1)); 1528 } 1529 1530 SDValue UndefVal = DAG.getUNDEF(EltVT); 1531 for (; i < WidenNumElts; ++i) 1532 Ops[i] = UndefVal; 1533 1534 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts); 1535 } 1536 1537 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) { 1538 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1539 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1540 SDValue ShOp = N->getOperand(1); 1541 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1542 } 1543 1544 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) { 1545 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1546 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1547 SDValue ShOp = N->getOperand(1); 1548 1549 EVT ShVT = ShOp.getValueType(); 1550 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) { 1551 ShOp = GetWidenedVector(ShOp); 1552 ShVT = ShOp.getValueType(); 1553 } 1554 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(), 1555 ShVT.getVectorElementType(), 1556 WidenVT.getVectorNumElements()); 1557 if (ShVT != ShWidenVT) 1558 ShOp = ModifyToType(ShOp, ShWidenVT); 1559 1560 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); 1561 } 1562 1563 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) { 1564 // Unary op widening. 1565 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1566 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1567 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp); 1568 } 1569 1570 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) { 1571 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1572 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), 1573 cast<VTSDNode>(N->getOperand(1))->getVT() 1574 .getVectorElementType(), 1575 WidenVT.getVectorNumElements()); 1576 SDValue WidenLHS = GetWidenedVector(N->getOperand(0)); 1577 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 1578 WidenVT, WidenLHS, DAG.getValueType(ExtVT)); 1579 } 1580 1581 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) { 1582 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo); 1583 return GetWidenedVector(WidenVec); 1584 } 1585 1586 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) { 1587 SDValue InOp = N->getOperand(0); 1588 EVT InVT = InOp.getValueType(); 1589 EVT VT = N->getValueType(0); 1590 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1591 DebugLoc dl = N->getDebugLoc(); 1592 1593 switch (getTypeAction(InVT)) { 1594 default: 1595 assert(false && "Unknown type action!"); 1596 break; 1597 case TargetLowering::TypeLegal: 1598 break; 1599 case TargetLowering::TypePromoteInteger: 1600 // If the InOp is promoted to the same size, convert it. Otherwise, 1601 // fall out of the switch and widen the promoted input. 1602 InOp = GetPromotedInteger(InOp); 1603 InVT = InOp.getValueType(); 1604 if (WidenVT.bitsEq(InVT)) 1605 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1606 break; 1607 case TargetLowering::TypeSoftenFloat: 1608 case TargetLowering::TypeExpandInteger: 1609 case TargetLowering::TypeExpandFloat: 1610 case TargetLowering::TypeScalarizeVector: 1611 case TargetLowering::TypeSplitVector: 1612 break; 1613 case TargetLowering::TypeWidenVector: 1614 // If the InOp is widened to the same size, convert it. Otherwise, fall 1615 // out of the switch and widen the widened input. 1616 InOp = GetWidenedVector(InOp); 1617 InVT = InOp.getValueType(); 1618 if (WidenVT.bitsEq(InVT)) 1619 // The input widens to the same size. Convert to the widen value. 1620 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); 1621 break; 1622 } 1623 1624 unsigned WidenSize = WidenVT.getSizeInBits(); 1625 unsigned InSize = InVT.getSizeInBits(); 1626 // x86mmx is not an acceptable vector element type, so don't try. 1627 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) { 1628 // Determine new input vector type. The new input vector type will use 1629 // the same element type (if its a vector) or use the input type as a 1630 // vector. It is the same size as the type to widen to. 1631 EVT NewInVT; 1632 unsigned NewNumElts = WidenSize / InSize; 1633 if (InVT.isVector()) { 1634 EVT InEltVT = InVT.getVectorElementType(); 1635 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, 1636 WidenSize / InEltVT.getSizeInBits()); 1637 } else { 1638 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts); 1639 } 1640 1641 if (TLI.isTypeLegal(NewInVT)) { 1642 // Because the result and the input are different vector types, widening 1643 // the result could create a legal type but widening the input might make 1644 // it an illegal type that might lead to repeatedly splitting the input 1645 // and then widening it. To avoid this, we widen the input only if 1646 // it results in a legal type. 1647 SmallVector<SDValue, 16> Ops(NewNumElts); 1648 SDValue UndefVal = DAG.getUNDEF(InVT); 1649 Ops[0] = InOp; 1650 for (unsigned i = 1; i < NewNumElts; ++i) 1651 Ops[i] = UndefVal; 1652 1653 SDValue NewVec; 1654 if (InVT.isVector()) 1655 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, 1656 NewInVT, &Ops[0], NewNumElts); 1657 else 1658 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, 1659 NewInVT, &Ops[0], NewNumElts); 1660 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec); 1661 } 1662 } 1663 1664 return CreateStackStoreLoad(InOp, WidenVT); 1665 } 1666 1667 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { 1668 DebugLoc dl = N->getDebugLoc(); 1669 // Build a vector with undefined for the new nodes. 1670 EVT VT = N->getValueType(0); 1671 EVT EltVT = VT.getVectorElementType(); 1672 unsigned NumElts = VT.getVectorNumElements(); 1673 1674 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1675 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1676 1677 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end()); 1678 NewOps.reserve(WidenNumElts); 1679 for (unsigned i = NumElts; i < WidenNumElts; ++i) 1680 NewOps.push_back(DAG.getUNDEF(EltVT)); 1681 1682 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size()); 1683 } 1684 1685 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) { 1686 EVT InVT = N->getOperand(0).getValueType(); 1687 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1688 DebugLoc dl = N->getDebugLoc(); 1689 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1690 unsigned NumInElts = InVT.getVectorNumElements(); 1691 unsigned NumOperands = N->getNumOperands(); 1692 1693 bool InputWidened = false; // Indicates we need to widen the input. 1694 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) { 1695 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) { 1696 // Add undef vectors to widen to correct length. 1697 unsigned NumConcat = WidenVT.getVectorNumElements() / 1698 InVT.getVectorNumElements(); 1699 SDValue UndefVal = DAG.getUNDEF(InVT); 1700 SmallVector<SDValue, 16> Ops(NumConcat); 1701 for (unsigned i=0; i < NumOperands; ++i) 1702 Ops[i] = N->getOperand(i); 1703 for (unsigned i = NumOperands; i != NumConcat; ++i) 1704 Ops[i] = UndefVal; 1705 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat); 1706 } 1707 } else { 1708 InputWidened = true; 1709 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) { 1710 // The inputs and the result are widen to the same value. 1711 unsigned i; 1712 for (i=1; i < NumOperands; ++i) 1713 if (N->getOperand(i).getOpcode() != ISD::UNDEF) 1714 break; 1715 1716 if (i == NumOperands) 1717 // Everything but the first operand is an UNDEF so just return the 1718 // widened first operand. 1719 return GetWidenedVector(N->getOperand(0)); 1720 1721 if (NumOperands == 2) { 1722 // Replace concat of two operands with a shuffle. 1723 SmallVector<int, 16> MaskOps(WidenNumElts, -1); 1724 for (unsigned i = 0; i < NumInElts; ++i) { 1725 MaskOps[i] = i; 1726 MaskOps[i + NumInElts] = i + WidenNumElts; 1727 } 1728 return DAG.getVectorShuffle(WidenVT, dl, 1729 GetWidenedVector(N->getOperand(0)), 1730 GetWidenedVector(N->getOperand(1)), 1731 &MaskOps[0]); 1732 } 1733 } 1734 } 1735 1736 // Fall back to use extracts and build vector. 1737 EVT EltVT = WidenVT.getVectorElementType(); 1738 SmallVector<SDValue, 16> Ops(WidenNumElts); 1739 unsigned Idx = 0; 1740 for (unsigned i=0; i < NumOperands; ++i) { 1741 SDValue InOp = N->getOperand(i); 1742 if (InputWidened) 1743 InOp = GetWidenedVector(InOp); 1744 for (unsigned j=0; j < NumInElts; ++j) 1745 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1746 DAG.getIntPtrConstant(j)); 1747 } 1748 SDValue UndefVal = DAG.getUNDEF(EltVT); 1749 for (; Idx < WidenNumElts; ++Idx) 1750 Ops[Idx] = UndefVal; 1751 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1752 } 1753 1754 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { 1755 DebugLoc dl = N->getDebugLoc(); 1756 SDValue InOp = N->getOperand(0); 1757 SDValue RndOp = N->getOperand(3); 1758 SDValue SatOp = N->getOperand(4); 1759 1760 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1761 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1762 1763 EVT InVT = InOp.getValueType(); 1764 EVT InEltVT = InVT.getVectorElementType(); 1765 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts); 1766 1767 SDValue DTyOp = DAG.getValueType(WidenVT); 1768 SDValue STyOp = DAG.getValueType(InWidenVT); 1769 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 1770 1771 unsigned InVTNumElts = InVT.getVectorNumElements(); 1772 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { 1773 InOp = GetWidenedVector(InOp); 1774 InVT = InOp.getValueType(); 1775 InVTNumElts = InVT.getVectorNumElements(); 1776 if (InVTNumElts == WidenNumElts) 1777 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1778 SatOp, CvtCode); 1779 } 1780 1781 if (TLI.isTypeLegal(InWidenVT)) { 1782 // Because the result and the input are different vector types, widening 1783 // the result could create a legal type but widening the input might make 1784 // it an illegal type that might lead to repeatedly splitting the input 1785 // and then widening it. To avoid this, we widen the input only if 1786 // it results in a legal type. 1787 if (WidenNumElts % InVTNumElts == 0) { 1788 // Widen the input and call convert on the widened input vector. 1789 unsigned NumConcat = WidenNumElts/InVTNumElts; 1790 SmallVector<SDValue, 16> Ops(NumConcat); 1791 Ops[0] = InOp; 1792 SDValue UndefVal = DAG.getUNDEF(InVT); 1793 for (unsigned i = 1; i != NumConcat; ++i) 1794 Ops[i] = UndefVal; 1795 1796 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat); 1797 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1798 SatOp, CvtCode); 1799 } 1800 1801 if (InVTNumElts % WidenNumElts == 0) { 1802 // Extract the input and convert the shorten input vector. 1803 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp, 1804 DAG.getIntPtrConstant(0)); 1805 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp, 1806 SatOp, CvtCode); 1807 } 1808 } 1809 1810 // Otherwise unroll into some nasty scalar code and rebuild the vector. 1811 SmallVector<SDValue, 16> Ops(WidenNumElts); 1812 EVT EltVT = WidenVT.getVectorElementType(); 1813 DTyOp = DAG.getValueType(EltVT); 1814 STyOp = DAG.getValueType(InEltVT); 1815 1816 unsigned MinElts = std::min(InVTNumElts, WidenNumElts); 1817 unsigned i; 1818 for (i=0; i < MinElts; ++i) { 1819 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 1820 DAG.getIntPtrConstant(i)); 1821 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp, 1822 SatOp, CvtCode); 1823 } 1824 1825 SDValue UndefVal = DAG.getUNDEF(EltVT); 1826 for (; i < WidenNumElts; ++i) 1827 Ops[i] = UndefVal; 1828 1829 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1830 } 1831 1832 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { 1833 EVT VT = N->getValueType(0); 1834 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1835 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1836 SDValue InOp = N->getOperand(0); 1837 SDValue Idx = N->getOperand(1); 1838 DebugLoc dl = N->getDebugLoc(); 1839 1840 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 1841 InOp = GetWidenedVector(InOp); 1842 1843 EVT InVT = InOp.getValueType(); 1844 1845 // Check if we can just return the input vector after widening. 1846 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 1847 if (IdxVal == 0 && InVT == WidenVT) 1848 return InOp; 1849 1850 // Check if we can extract from the vector. 1851 unsigned InNumElts = InVT.getVectorNumElements(); 1852 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts) 1853 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx); 1854 1855 // We could try widening the input to the right length but for now, extract 1856 // the original elements, fill the rest with undefs and build a vector. 1857 SmallVector<SDValue, 16> Ops(WidenNumElts); 1858 EVT EltVT = VT.getVectorElementType(); 1859 unsigned NumElts = VT.getVectorNumElements(); 1860 unsigned i; 1861 for (i=0; i < NumElts; ++i) 1862 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 1863 DAG.getIntPtrConstant(IdxVal+i)); 1864 1865 SDValue UndefVal = DAG.getUNDEF(EltVT); 1866 for (; i < WidenNumElts; ++i) 1867 Ops[i] = UndefVal; 1868 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts); 1869 } 1870 1871 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) { 1872 SDValue InOp = GetWidenedVector(N->getOperand(0)); 1873 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(), 1874 InOp.getValueType(), InOp, 1875 N->getOperand(1), N->getOperand(2)); 1876 } 1877 1878 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { 1879 LoadSDNode *LD = cast<LoadSDNode>(N); 1880 ISD::LoadExtType ExtType = LD->getExtensionType(); 1881 1882 SDValue Result; 1883 SmallVector<SDValue, 16> LdChain; // Chain for the series of load 1884 if (ExtType != ISD::NON_EXTLOAD) 1885 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); 1886 else 1887 Result = GenWidenVectorLoads(LdChain, LD); 1888 1889 // If we generate a single load, we can use that for the chain. Otherwise, 1890 // build a factor node to remember the multiple loads are independent and 1891 // chain to that. 1892 SDValue NewChain; 1893 if (LdChain.size() == 1) 1894 NewChain = LdChain[0]; 1895 else 1896 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other, 1897 &LdChain[0], LdChain.size()); 1898 1899 // Modified the chain - switch anything that used the old chain to use 1900 // the new one. 1901 ReplaceValueWith(SDValue(N, 1), NewChain); 1902 1903 return Result; 1904 } 1905 1906 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) { 1907 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1908 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(), 1909 WidenVT, N->getOperand(0)); 1910 } 1911 1912 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) { 1913 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1914 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1915 1916 SDValue Cond1 = N->getOperand(0); 1917 EVT CondVT = Cond1.getValueType(); 1918 if (CondVT.isVector()) { 1919 EVT CondEltVT = CondVT.getVectorElementType(); 1920 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), 1921 CondEltVT, WidenNumElts); 1922 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector) 1923 Cond1 = GetWidenedVector(Cond1); 1924 1925 if (Cond1.getValueType() != CondWidenVT) 1926 Cond1 = ModifyToType(Cond1, CondWidenVT); 1927 } 1928 1929 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 1930 SDValue InOp2 = GetWidenedVector(N->getOperand(2)); 1931 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT); 1932 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 1933 WidenVT, Cond1, InOp1, InOp2); 1934 } 1935 1936 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) { 1937 SDValue InOp1 = GetWidenedVector(N->getOperand(2)); 1938 SDValue InOp2 = GetWidenedVector(N->getOperand(3)); 1939 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 1940 InOp1.getValueType(), N->getOperand(0), 1941 N->getOperand(1), InOp1, InOp2, N->getOperand(4)); 1942 } 1943 1944 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) { 1945 assert(N->getValueType(0).isVector() == 1946 N->getOperand(0).getValueType().isVector() && 1947 "Scalar/Vector type mismatch"); 1948 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N); 1949 1950 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1951 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1952 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1953 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT, 1954 InOp1, InOp2, N->getOperand(2)); 1955 } 1956 1957 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) { 1958 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1959 return DAG.getUNDEF(WidenVT); 1960 } 1961 1962 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) { 1963 EVT VT = N->getValueType(0); 1964 DebugLoc dl = N->getDebugLoc(); 1965 1966 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1967 unsigned NumElts = VT.getVectorNumElements(); 1968 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1969 1970 SDValue InOp1 = GetWidenedVector(N->getOperand(0)); 1971 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 1972 1973 // Adjust mask based on new input vector length. 1974 SmallVector<int, 16> NewMask; 1975 for (unsigned i = 0; i != NumElts; ++i) { 1976 int Idx = N->getMaskElt(i); 1977 if (Idx < (int)NumElts) 1978 NewMask.push_back(Idx); 1979 else 1980 NewMask.push_back(Idx - NumElts + WidenNumElts); 1981 } 1982 for (unsigned i = NumElts; i != WidenNumElts; ++i) 1983 NewMask.push_back(-1); 1984 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]); 1985 } 1986 1987 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) { 1988 assert(N->getValueType(0).isVector() && 1989 N->getOperand(0).getValueType().isVector() && 1990 "Operands must be vectors"); 1991 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1992 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 1993 1994 SDValue InOp1 = N->getOperand(0); 1995 EVT InVT = InOp1.getValueType(); 1996 assert(InVT.isVector() && "can not widen non vector type"); 1997 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(), 1998 InVT.getVectorElementType(), WidenNumElts); 1999 InOp1 = GetWidenedVector(InOp1); 2000 SDValue InOp2 = GetWidenedVector(N->getOperand(1)); 2001 2002 // Assume that the input and output will be widen appropriately. If not, 2003 // we will have to unroll it at some point. 2004 assert(InOp1.getValueType() == WidenInVT && 2005 InOp2.getValueType() == WidenInVT && 2006 "Input not widened to expected type!"); 2007 (void)WidenInVT; 2008 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), 2009 WidenVT, InOp1, InOp2, N->getOperand(2)); 2010 } 2011 2012 2013 //===----------------------------------------------------------------------===// 2014 // Widen Vector Operand 2015 //===----------------------------------------------------------------------===// 2016 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) { 2017 DEBUG(dbgs() << "Widen node operand " << ResNo << ": "; 2018 N->dump(&DAG); 2019 dbgs() << "\n"); 2020 SDValue Res = SDValue(); 2021 2022 switch (N->getOpcode()) { 2023 default: 2024 #ifndef NDEBUG 2025 dbgs() << "WidenVectorOperand op #" << ResNo << ": "; 2026 N->dump(&DAG); 2027 dbgs() << "\n"; 2028 #endif 2029 llvm_unreachable("Do not know how to widen this operator's operand!"); 2030 2031 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break; 2032 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break; 2033 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break; 2034 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break; 2035 case ISD::STORE: Res = WidenVecOp_STORE(N); break; 2036 case ISD::SETCC: Res = WidenVecOp_SETCC(N, ResNo); break; 2037 2038 case ISD::FP_EXTEND: 2039 case ISD::FP_TO_SINT: 2040 case ISD::FP_TO_UINT: 2041 case ISD::SINT_TO_FP: 2042 case ISD::UINT_TO_FP: 2043 case ISD::TRUNCATE: 2044 case ISD::SIGN_EXTEND: 2045 case ISD::ZERO_EXTEND: 2046 case ISD::ANY_EXTEND: 2047 Res = WidenVecOp_Convert(N); 2048 break; 2049 } 2050 2051 // If Res is null, the sub-method took care of registering the result. 2052 if (!Res.getNode()) return false; 2053 2054 // If the result is N, the sub-method updated N in place. Tell the legalizer 2055 // core about this. 2056 if (Res.getNode() == N) 2057 return true; 2058 2059 2060 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2061 "Invalid operand expansion"); 2062 2063 ReplaceValueWith(SDValue(N, 0), Res); 2064 return false; 2065 } 2066 2067 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) { 2068 // Since the result is legal and the input is illegal, it is unlikely 2069 // that we can fix the input to a legal type so unroll the convert 2070 // into some scalar code and create a nasty build vector. 2071 EVT VT = N->getValueType(0); 2072 EVT EltVT = VT.getVectorElementType(); 2073 DebugLoc dl = N->getDebugLoc(); 2074 unsigned NumElts = VT.getVectorNumElements(); 2075 SDValue InOp = N->getOperand(0); 2076 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2077 InOp = GetWidenedVector(InOp); 2078 EVT InVT = InOp.getValueType(); 2079 EVT InEltVT = InVT.getVectorElementType(); 2080 2081 unsigned Opcode = N->getOpcode(); 2082 SmallVector<SDValue, 16> Ops(NumElts); 2083 for (unsigned i=0; i < NumElts; ++i) 2084 Ops[i] = DAG.getNode(Opcode, dl, EltVT, 2085 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp, 2086 DAG.getIntPtrConstant(i))); 2087 2088 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2089 } 2090 2091 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) { 2092 EVT VT = N->getValueType(0); 2093 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2094 EVT InWidenVT = InOp.getValueType(); 2095 DebugLoc dl = N->getDebugLoc(); 2096 2097 // Check if we can convert between two legal vector types and extract. 2098 unsigned InWidenSize = InWidenVT.getSizeInBits(); 2099 unsigned Size = VT.getSizeInBits(); 2100 // x86mmx is not an acceptable vector element type, so don't try. 2101 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) { 2102 unsigned NewNumElts = InWidenSize / Size; 2103 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); 2104 if (TLI.isTypeLegal(NewVT)) { 2105 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp); 2106 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, 2107 DAG.getIntPtrConstant(0)); 2108 } 2109 } 2110 2111 return CreateStackStoreLoad(InOp, VT); 2112 } 2113 2114 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) { 2115 // If the input vector is not legal, it is likely that we will not find a 2116 // legal vector of the same size. Replace the concatenate vector with a 2117 // nasty build vector. 2118 EVT VT = N->getValueType(0); 2119 EVT EltVT = VT.getVectorElementType(); 2120 DebugLoc dl = N->getDebugLoc(); 2121 unsigned NumElts = VT.getVectorNumElements(); 2122 SmallVector<SDValue, 16> Ops(NumElts); 2123 2124 EVT InVT = N->getOperand(0).getValueType(); 2125 unsigned NumInElts = InVT.getVectorNumElements(); 2126 2127 unsigned Idx = 0; 2128 unsigned NumOperands = N->getNumOperands(); 2129 for (unsigned i=0; i < NumOperands; ++i) { 2130 SDValue InOp = N->getOperand(i); 2131 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) 2132 InOp = GetWidenedVector(InOp); 2133 for (unsigned j=0; j < NumInElts; ++j) 2134 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2135 DAG.getIntPtrConstant(j)); 2136 } 2137 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); 2138 } 2139 2140 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) { 2141 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2142 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), 2143 N->getValueType(0), InOp, N->getOperand(1)); 2144 } 2145 2146 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { 2147 SDValue InOp = GetWidenedVector(N->getOperand(0)); 2148 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), 2149 N->getValueType(0), InOp, N->getOperand(1)); 2150 } 2151 2152 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { 2153 // We have to widen the value but we want only to store the original 2154 // vector type. 2155 StoreSDNode *ST = cast<StoreSDNode>(N); 2156 2157 SmallVector<SDValue, 16> StChain; 2158 if (ST->isTruncatingStore()) 2159 GenWidenVectorTruncStores(StChain, ST); 2160 else 2161 GenWidenVectorStores(StChain, ST); 2162 2163 if (StChain.size() == 1) 2164 return StChain[0]; 2165 else 2166 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(), 2167 MVT::Other,&StChain[0],StChain.size()); 2168 } 2169 2170 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N, unsigned ResNo) { 2171 assert(ResNo < 2 && "Invalid res num to widen"); 2172 SDValue InOp0 = GetWidenedVector(N->getOperand(0)); 2173 SDValue InOp1 = GetWidenedVector(N->getOperand(1)); 2174 EVT VT = InOp0.getValueType(); 2175 DebugLoc dl = N->getDebugLoc(); 2176 2177 // WARNING: In this code we widen the compare instruction with garbage. 2178 // This garbage may contain denormal floats which may be slow. Is this a real 2179 // concern ? Should we zero the unused lanes if this is a float compare ? 2180 2181 SDValue Zero = DAG.getIntPtrConstant(0); 2182 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), 2183 N->getValueType(0).getVectorElementType(), 2184 VT.getVectorNumElements()); 2185 2186 SDValue WideSETCC = DAG.getNode(ISD::SETCC, N->getDebugLoc(), 2187 ResVT, InOp0, InOp1, N->getOperand(2)); 2188 2189 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, N->getValueType(0), 2190 WideSETCC, Zero); 2191 } 2192 2193 2194 //===----------------------------------------------------------------------===// 2195 // Vector Widening Utilities 2196 //===----------------------------------------------------------------------===// 2197 2198 // Utility function to find the type to chop up a widen vector for load/store 2199 // TLI: Target lowering used to determine legal types. 2200 // Width: Width left need to load/store. 2201 // WidenVT: The widen vector type to load to/store from 2202 // Align: If 0, don't allow use of a wider type 2203 // WidenEx: If Align is not 0, the amount additional we can load/store from. 2204 2205 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, 2206 unsigned Width, EVT WidenVT, 2207 unsigned Align = 0, unsigned WidenEx = 0) { 2208 EVT WidenEltVT = WidenVT.getVectorElementType(); 2209 unsigned WidenWidth = WidenVT.getSizeInBits(); 2210 unsigned WidenEltWidth = WidenEltVT.getSizeInBits(); 2211 unsigned AlignInBits = Align*8; 2212 2213 // If we have one element to load/store, return it. 2214 EVT RetVT = WidenEltVT; 2215 if (Width == WidenEltWidth) 2216 return RetVT; 2217 2218 // See if there is larger legal integer than the element type to load/store 2219 unsigned VT; 2220 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE; 2221 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) { 2222 EVT MemVT((MVT::SimpleValueType) VT); 2223 unsigned MemVTWidth = MemVT.getSizeInBits(); 2224 if (MemVT.getSizeInBits() <= WidenEltWidth) 2225 break; 2226 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 && 2227 isPowerOf2_32(WidenWidth / MemVTWidth) && 2228 (MemVTWidth <= Width || 2229 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2230 RetVT = MemVT; 2231 break; 2232 } 2233 } 2234 2235 // See if there is a larger vector type to load/store that has the same vector 2236 // element type and is evenly divisible with the WidenVT. 2237 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 2238 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) { 2239 EVT MemVT = (MVT::SimpleValueType) VT; 2240 unsigned MemVTWidth = MemVT.getSizeInBits(); 2241 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() && 2242 (WidenWidth % MemVTWidth) == 0 && 2243 isPowerOf2_32(WidenWidth / MemVTWidth) && 2244 (MemVTWidth <= Width || 2245 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { 2246 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT) 2247 return MemVT; 2248 } 2249 } 2250 2251 return RetVT; 2252 } 2253 2254 // Builds a vector type from scalar loads 2255 // VecTy: Resulting Vector type 2256 // LDOps: Load operators to build a vector type 2257 // [Start,End) the list of loads to use. 2258 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, 2259 SmallVector<SDValue, 16>& LdOps, 2260 unsigned Start, unsigned End) { 2261 DebugLoc dl = LdOps[Start].getDebugLoc(); 2262 EVT LdTy = LdOps[Start].getValueType(); 2263 unsigned Width = VecTy.getSizeInBits(); 2264 unsigned NumElts = Width / LdTy.getSizeInBits(); 2265 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts); 2266 2267 unsigned Idx = 1; 2268 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]); 2269 2270 for (unsigned i = Start + 1; i != End; ++i) { 2271 EVT NewLdTy = LdOps[i].getValueType(); 2272 if (NewLdTy != LdTy) { 2273 NumElts = Width / NewLdTy.getSizeInBits(); 2274 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts); 2275 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp); 2276 // Readjust position and vector position based on new load type 2277 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits(); 2278 LdTy = NewLdTy; 2279 } 2280 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], 2281 DAG.getIntPtrConstant(Idx++)); 2282 } 2283 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp); 2284 } 2285 2286 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain, 2287 LoadSDNode *LD) { 2288 // The strategy assumes that we can efficiently load powers of two widths. 2289 // The routines chops the vector into the largest vector loads with the same 2290 // element type or scalar loads and then recombines it to the widen vector 2291 // type. 2292 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2293 unsigned WidenWidth = WidenVT.getSizeInBits(); 2294 EVT LdVT = LD->getMemoryVT(); 2295 DebugLoc dl = LD->getDebugLoc(); 2296 assert(LdVT.isVector() && WidenVT.isVector()); 2297 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType()); 2298 2299 // Load information 2300 SDValue Chain = LD->getChain(); 2301 SDValue BasePtr = LD->getBasePtr(); 2302 unsigned Align = LD->getAlignment(); 2303 bool isVolatile = LD->isVolatile(); 2304 bool isNonTemporal = LD->isNonTemporal(); 2305 2306 int LdWidth = LdVT.getSizeInBits(); 2307 int WidthDiff = WidenWidth - LdWidth; // Difference 2308 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads 2309 2310 // Find the vector type that can load from. 2311 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2312 int NewVTWidth = NewVT.getSizeInBits(); 2313 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(), 2314 isVolatile, isNonTemporal, Align); 2315 LdChain.push_back(LdOp.getValue(1)); 2316 2317 // Check if we can load the element with one instruction 2318 if (LdWidth <= NewVTWidth) { 2319 if (!NewVT.isVector()) { 2320 unsigned NumElts = WidenWidth / NewVTWidth; 2321 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2322 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp); 2323 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp); 2324 } 2325 if (NewVT == WidenVT) 2326 return LdOp; 2327 2328 assert(WidenWidth % NewVTWidth == 0); 2329 unsigned NumConcat = WidenWidth / NewVTWidth; 2330 SmallVector<SDValue, 16> ConcatOps(NumConcat); 2331 SDValue UndefVal = DAG.getUNDEF(NewVT); 2332 ConcatOps[0] = LdOp; 2333 for (unsigned i = 1; i != NumConcat; ++i) 2334 ConcatOps[i] = UndefVal; 2335 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], 2336 NumConcat); 2337 } 2338 2339 // Load vector by using multiple loads from largest vector to scalar 2340 SmallVector<SDValue, 16> LdOps; 2341 LdOps.push_back(LdOp); 2342 2343 LdWidth -= NewVTWidth; 2344 unsigned Offset = 0; 2345 2346 while (LdWidth > 0) { 2347 unsigned Increment = NewVTWidth / 8; 2348 Offset += Increment; 2349 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2350 DAG.getIntPtrConstant(Increment)); 2351 2352 if (LdWidth < NewVTWidth) { 2353 // Our current type we are using is too large, find a better size 2354 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff); 2355 NewVTWidth = NewVT.getSizeInBits(); 2356 } 2357 2358 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, 2359 LD->getPointerInfo().getWithOffset(Offset), 2360 isVolatile, 2361 isNonTemporal, MinAlign(Align, Increment)); 2362 LdChain.push_back(LdOp.getValue(1)); 2363 LdOps.push_back(LdOp); 2364 2365 LdWidth -= NewVTWidth; 2366 } 2367 2368 // Build the vector from the loads operations 2369 unsigned End = LdOps.size(); 2370 if (!LdOps[0].getValueType().isVector()) 2371 // All the loads are scalar loads. 2372 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End); 2373 2374 // If the load contains vectors, build the vector using concat vector. 2375 // All of the vectors used to loads are power of 2 and the scalars load 2376 // can be combined to make a power of 2 vector. 2377 SmallVector<SDValue, 16> ConcatOps(End); 2378 int i = End - 1; 2379 int Idx = End; 2380 EVT LdTy = LdOps[i].getValueType(); 2381 // First combine the scalar loads to a vector 2382 if (!LdTy.isVector()) { 2383 for (--i; i >= 0; --i) { 2384 LdTy = LdOps[i].getValueType(); 2385 if (LdTy.isVector()) 2386 break; 2387 } 2388 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End); 2389 } 2390 ConcatOps[--Idx] = LdOps[i]; 2391 for (--i; i >= 0; --i) { 2392 EVT NewLdTy = LdOps[i].getValueType(); 2393 if (NewLdTy != LdTy) { 2394 // Create a larger vector 2395 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy, 2396 &ConcatOps[Idx], End - Idx); 2397 Idx = End - 1; 2398 LdTy = NewLdTy; 2399 } 2400 ConcatOps[--Idx] = LdOps[i]; 2401 } 2402 2403 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx)) 2404 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 2405 &ConcatOps[Idx], End - Idx); 2406 2407 // We need to fill the rest with undefs to build the vector 2408 unsigned NumOps = WidenWidth / LdTy.getSizeInBits(); 2409 SmallVector<SDValue, 16> WidenOps(NumOps); 2410 SDValue UndefVal = DAG.getUNDEF(LdTy); 2411 { 2412 unsigned i = 0; 2413 for (; i != End-Idx; ++i) 2414 WidenOps[i] = ConcatOps[Idx+i]; 2415 for (; i != NumOps; ++i) 2416 WidenOps[i] = UndefVal; 2417 } 2418 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps); 2419 } 2420 2421 SDValue 2422 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain, 2423 LoadSDNode * LD, 2424 ISD::LoadExtType ExtType) { 2425 // For extension loads, it may not be more efficient to chop up the vector 2426 // and then extended it. Instead, we unroll the load and build a new vector. 2427 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0)); 2428 EVT LdVT = LD->getMemoryVT(); 2429 DebugLoc dl = LD->getDebugLoc(); 2430 assert(LdVT.isVector() && WidenVT.isVector()); 2431 2432 // Load information 2433 SDValue Chain = LD->getChain(); 2434 SDValue BasePtr = LD->getBasePtr(); 2435 unsigned Align = LD->getAlignment(); 2436 bool isVolatile = LD->isVolatile(); 2437 bool isNonTemporal = LD->isNonTemporal(); 2438 2439 EVT EltVT = WidenVT.getVectorElementType(); 2440 EVT LdEltVT = LdVT.getVectorElementType(); 2441 unsigned NumElts = LdVT.getVectorNumElements(); 2442 2443 // Load each element and widen 2444 unsigned WidenNumElts = WidenVT.getVectorNumElements(); 2445 SmallVector<SDValue, 16> Ops(WidenNumElts); 2446 unsigned Increment = LdEltVT.getSizeInBits() / 8; 2447 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, 2448 LD->getPointerInfo(), 2449 LdEltVT, isVolatile, isNonTemporal, Align); 2450 LdChain.push_back(Ops[0].getValue(1)); 2451 unsigned i = 0, Offset = Increment; 2452 for (i=1; i < NumElts; ++i, Offset += Increment) { 2453 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2454 BasePtr, DAG.getIntPtrConstant(Offset)); 2455 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, 2456 LD->getPointerInfo().getWithOffset(Offset), LdEltVT, 2457 isVolatile, isNonTemporal, Align); 2458 LdChain.push_back(Ops[i].getValue(1)); 2459 } 2460 2461 // Fill the rest with undefs 2462 SDValue UndefVal = DAG.getUNDEF(EltVT); 2463 for (; i != WidenNumElts; ++i) 2464 Ops[i] = UndefVal; 2465 2466 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size()); 2467 } 2468 2469 2470 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, 2471 StoreSDNode *ST) { 2472 // The strategy assumes that we can efficiently store powers of two widths. 2473 // The routines chops the vector into the largest vector stores with the same 2474 // element type or scalar stores. 2475 SDValue Chain = ST->getChain(); 2476 SDValue BasePtr = ST->getBasePtr(); 2477 unsigned Align = ST->getAlignment(); 2478 bool isVolatile = ST->isVolatile(); 2479 bool isNonTemporal = ST->isNonTemporal(); 2480 SDValue ValOp = GetWidenedVector(ST->getValue()); 2481 DebugLoc dl = ST->getDebugLoc(); 2482 2483 EVT StVT = ST->getMemoryVT(); 2484 unsigned StWidth = StVT.getSizeInBits(); 2485 EVT ValVT = ValOp.getValueType(); 2486 unsigned ValWidth = ValVT.getSizeInBits(); 2487 EVT ValEltVT = ValVT.getVectorElementType(); 2488 unsigned ValEltWidth = ValEltVT.getSizeInBits(); 2489 assert(StVT.getVectorElementType() == ValEltVT); 2490 2491 int Idx = 0; // current index to store 2492 unsigned Offset = 0; // offset from base to store 2493 while (StWidth != 0) { 2494 // Find the largest vector type we can store with 2495 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT); 2496 unsigned NewVTWidth = NewVT.getSizeInBits(); 2497 unsigned Increment = NewVTWidth / 8; 2498 if (NewVT.isVector()) { 2499 unsigned NumVTElts = NewVT.getVectorNumElements(); 2500 do { 2501 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, 2502 DAG.getIntPtrConstant(Idx)); 2503 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2504 ST->getPointerInfo().getWithOffset(Offset), 2505 isVolatile, isNonTemporal, 2506 MinAlign(Align, Offset))); 2507 StWidth -= NewVTWidth; 2508 Offset += Increment; 2509 Idx += NumVTElts; 2510 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2511 DAG.getIntPtrConstant(Increment)); 2512 } while (StWidth != 0 && StWidth >= NewVTWidth); 2513 } else { 2514 // Cast the vector to the scalar type we can store 2515 unsigned NumElts = ValWidth / NewVTWidth; 2516 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts); 2517 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp); 2518 // Readjust index position based on new vector type 2519 Idx = Idx * ValEltWidth / NewVTWidth; 2520 do { 2521 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp, 2522 DAG.getIntPtrConstant(Idx++)); 2523 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, 2524 ST->getPointerInfo().getWithOffset(Offset), 2525 isVolatile, isNonTemporal, 2526 MinAlign(Align, Offset))); 2527 StWidth -= NewVTWidth; 2528 Offset += Increment; 2529 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2530 DAG.getIntPtrConstant(Increment)); 2531 } while (StWidth != 0 && StWidth >= NewVTWidth); 2532 // Restore index back to be relative to the original widen element type 2533 Idx = Idx * NewVTWidth / ValEltWidth; 2534 } 2535 } 2536 } 2537 2538 void 2539 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain, 2540 StoreSDNode *ST) { 2541 // For extension loads, it may not be more efficient to truncate the vector 2542 // and then store it. Instead, we extract each element and then store it. 2543 SDValue Chain = ST->getChain(); 2544 SDValue BasePtr = ST->getBasePtr(); 2545 unsigned Align = ST->getAlignment(); 2546 bool isVolatile = ST->isVolatile(); 2547 bool isNonTemporal = ST->isNonTemporal(); 2548 SDValue ValOp = GetWidenedVector(ST->getValue()); 2549 DebugLoc dl = ST->getDebugLoc(); 2550 2551 EVT StVT = ST->getMemoryVT(); 2552 EVT ValVT = ValOp.getValueType(); 2553 2554 // It must be true that we the widen vector type is bigger than where 2555 // we need to store. 2556 assert(StVT.isVector() && ValOp.getValueType().isVector()); 2557 assert(StVT.bitsLT(ValOp.getValueType())); 2558 2559 // For truncating stores, we can not play the tricks of chopping legal 2560 // vector types and bit cast it to the right type. Instead, we unroll 2561 // the store. 2562 EVT StEltVT = StVT.getVectorElementType(); 2563 EVT ValEltVT = ValVT.getVectorElementType(); 2564 unsigned Increment = ValEltVT.getSizeInBits() / 8; 2565 unsigned NumElts = StVT.getVectorNumElements(); 2566 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2567 DAG.getIntPtrConstant(0)); 2568 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, 2569 ST->getPointerInfo(), StEltVT, 2570 isVolatile, isNonTemporal, Align)); 2571 unsigned Offset = Increment; 2572 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) { 2573 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2574 BasePtr, DAG.getIntPtrConstant(Offset)); 2575 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, 2576 DAG.getIntPtrConstant(0)); 2577 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, 2578 ST->getPointerInfo().getWithOffset(Offset), 2579 StEltVT, isVolatile, isNonTemporal, 2580 MinAlign(Align, Offset))); 2581 } 2582 } 2583 2584 /// Modifies a vector input (widen or narrows) to a vector of NVT. The 2585 /// input vector must have the same element type as NVT. 2586 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) { 2587 // Note that InOp might have been widened so it might already have 2588 // the right width or it might need be narrowed. 2589 EVT InVT = InOp.getValueType(); 2590 assert(InVT.getVectorElementType() == NVT.getVectorElementType() && 2591 "input and widen element type must match"); 2592 DebugLoc dl = InOp.getDebugLoc(); 2593 2594 // Check if InOp already has the right width. 2595 if (InVT == NVT) 2596 return InOp; 2597 2598 unsigned InNumElts = InVT.getVectorNumElements(); 2599 unsigned WidenNumElts = NVT.getVectorNumElements(); 2600 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) { 2601 unsigned NumConcat = WidenNumElts / InNumElts; 2602 SmallVector<SDValue, 16> Ops(NumConcat); 2603 SDValue UndefVal = DAG.getUNDEF(InVT); 2604 Ops[0] = InOp; 2605 for (unsigned i = 1; i != NumConcat; ++i) 2606 Ops[i] = UndefVal; 2607 2608 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat); 2609 } 2610 2611 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts) 2612 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp, 2613 DAG.getIntPtrConstant(0)); 2614 2615 // Fall back to extract and build. 2616 SmallVector<SDValue, 16> Ops(WidenNumElts); 2617 EVT EltVT = NVT.getVectorElementType(); 2618 unsigned MinNumElts = std::min(WidenNumElts, InNumElts); 2619 unsigned Idx; 2620 for (Idx = 0; Idx < MinNumElts; ++Idx) 2621 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, 2622 DAG.getIntPtrConstant(Idx)); 2623 2624 SDValue UndefVal = DAG.getUNDEF(EltVT); 2625 for ( ; Idx < WidenNumElts; ++Idx) 2626 Ops[Idx] = UndefVal; 2627 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts); 2628 } 2629