| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 92 /// it into "(A op B) op' (A op C)". Here "op" is given by Opcode and "op'" is
96 static Value *ExpandBinOp(unsigned Opcode, Value *LHS, Value *RHS,
110 if (Value *L = SimplifyBinOp(Opcode, A, C, TD, DT, MaxRecurse))
111 if (Value *R = SimplifyBinOp(Opcode, B, C, TD, DT, MaxRecurse)) {
134 if (Value *L = SimplifyBinOp(Opcode, A, B, TD, DT, MaxRecurse))
135 if (Value *R = SimplifyBinOp(Opcode, A, C, TD, DT, MaxRecurse)) {
155 /// FactorizeBinOp - Simplify "LHS Opcode RHS" by factorizing out a common term
156 /// using the operation OpCodeToExtract. For example, when Opcode is Add and
159 static Value *FactorizeBinOp(unsigned Opcode, Value *LHS, Value *RHS,
185 if (Value *V = SimplifyBinOp(Opcode, B, DD, TD, DT, MaxRecurse))
[all...] |
| ValueTracking.cpp | 601 unsigned Opcode = LU->getOpcode();
605 if (Opcode == Instruction::Add ||
606 Opcode == Instruction::Sub ||
607 Opcode == Instruction::And ||
608 Opcode == Instruction::Or ||
609 Opcode == Instruction::Mul) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 360 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
375 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
376 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
646 unsigned Opcode = MI.getOpcode();
651 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
656 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
[all...] |
| Thumb2SizeReduction.cpp | 42 unsigned WideOpc; // Wide opcode
43 unsigned NarrowOpc1; // Narrow opcode to transform to
44 unsigned NarrowOpc2; // Narrow opcode when it's two-address
106 // FIXME: Clean this up after splitting each Thumb load / store opcode
146 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
267 /// Old opcode has an optional def of CPSR.
270 // If old opcode does not implicitly define CPSR, then it's not ok since
332 llvm_unreachable("Unexpected Thumb2 load / store opcode!");
568 // source insn opcode. So for now, we hack a local entry record to use.
829 unsigned Opcode = MI->getOpcode()
[all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 55 unsigned MLxOpc; // MLA / MLS opcode
56 unsigned MulOpc; // Expanded multiplication opcode
57 unsigned AddSubOpc; // Expanded add / sub opcode
[all...] |
| ARMCodeEmitter.cpp | 280 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ?
354 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
413 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
863 unsigned Opcode = MI.getDesc().Opcode;
872 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
879 switch (Opcode) {
[all...] |
| ARMConstantIslandPass.cpp | 140 /// opcode.
[all...] |
| ARMFastISel.cpp | 712 unsigned Opcode = Instruction::UserOp1;
718 Opcode = I->getOpcode();
722 Opcode = C->getOpcode();
732 switch (Opcode) {
[all...] |
| ARMISelDAGToDAG.cpp | 209 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
217 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
225 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
232 /// should be 2, 3 or 4. The opcode array specifies the instructions used
305 // opcode and that it has a immediate integer right operand.
357 unsigned Opcode = MCID.getOpcode();
358 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
373 return TII->isFpMLxInstruction(Opcode);
726 unsigned Opcode = Op->getOpcode()
[all...] |
| ARMLoadStoreOptimizer.cpp | 91 int Offset, unsigned Base, bool BaseKill, int Opcode,
102 int Opcode,
109 int Opcode, unsigned Size,
132 static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
133 switch (Opcode) {
134 default: llvm_unreachable("Unhandled opcode!");
213 AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
214 switch (Opcode) {
215 default: llvm_unreachable("Unhandled opcode!");
292 int Opcode, ARMCC::CondCodes Pred
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 45 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
46 return getInstructionName(Opcode);
55 unsigned Opcode = MI->getOpcode();
58 if (Opcode == ARM::MOVsr) {
78 if (Opcode == ARM::MOVsi) {
103 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
107 if (Opcode == ARM::t2STMDB_UPD)
114 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
124 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 43 const char *MBlazeTargetLowering::getTargetNodeName(unsigned Opcode) const {
44 switch (Opcode) {
354 // true/false values to select between, and a branch opcode to use.
490 unsigned opcode = 0; local
493 case MBlaze::LAA32: opcode = MBlaze::ADDIK; break;
494 case MBlaze::LAS32: opcode = MBlaze::RSUBIK; break;
495 case MBlaze::LAD32: opcode = MBlaze::AND; break;
496 case MBlaze::LAO32: opcode = MBlaze::OR; break;
497 case MBlaze::LAX32: opcode = MBlaze::XOR; break;
498 case MBlaze::LAN32: opcode = MBlaze::AND; break
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 86 /// rotate and mask opcode and mask operation.
143 /// Reg in an asm, because the load or store opcode would have to change.
303 // opcode and that it has a immediate integer right operand.
341 unsigned Opcode = N->getOpcode();
346 if (Opcode == ISD::SHL) {
351 } else if (Opcode == ISD::SRL) {
358 } else if (Opcode == ISD::ROTL) {
[all...] |
| /external/llvm/examples/Kaleidoscope/Chapter6/ |
| toy.cpp | 129 char Opcode;
132 UnaryExprAST(char opcode, ExprAST *operand)
133 : Opcode(opcode), Operand(operand) {}
562 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
|
| /external/llvm/examples/Kaleidoscope/Chapter7/ |
| toy.cpp | 134 char Opcode;
137 UnaryExprAST(char opcode, ExprAST *operand)
138 : Opcode(opcode), Operand(operand) {}
640 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineLICM.cpp | 97 // For each opcode, keep a list of potential CSE instructions.
[all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | 35 // First special line opcode - leave room for the standard opcodes.
40 // Minimum line offset in a special line info. opcode. This value
44 // Range of line offsets in a special line info. opcode.
249 // Standard opcode lengths
346 uint64_t Temp, Opcode;
371 // If the line increment is out of range of a special opcode, we must encode
385 // Use DW_LNS_copy instead of a "line +0, addr +0" special opcode.
391 // Bias the opcode by the special opcode base.
396 // Try using a special opcode
[all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcher.h | 59 CheckOpcode, // Fail if not opcode.
60 SwitchOpcode, // Dispatch based on opcode.
447 /// specified opcode, if not it fails to match.
449 const SDNodeInfo &Opcode;
451 CheckOpcodeMatcher(const SDNodeInfo &opcode)
452 : Matcher(CheckOpcode), Opcode(opcode) {}
454 const SDNodeInfo &getOpcode() const { return Opcode; }
469 /// SwitchOpcodeMatcher - Switch based on the current node's opcode, dispatching
470 /// to one matcher per opcode. If the opcode doesn't match any of the cases
[all...] |
| /sdk/emulator/qtools/ |
| opcode.h | 9 // the opflags[] array in opcode.cpp.
10 enum Opcode {
113 // Define bit flags for the opcode categories
132 inline bool isALU(Opcode op) { return (opcode_flags[op] & kCatAlu) != 0; }
133 inline bool isBranch(Opcode op) { return (opcode_flags[op] & kCatBranch) != 0; }
134 inline bool isBranchLink(Opcode op) {
137 inline bool isBranchExch(Opcode op) {
140 inline bool isLoad(Opcode op) { return (opcode_flags[op] & kCatLoad) != 0; }
141 inline bool isLoadMultiple(Opcode op) {
144 inline bool isStoreMultiple(Opcode op)
[all...] |
| /external/javassist/src/main/javassist/bytecode/ |
| Opcode.java | 26 public interface Opcode {
440 0, // wide, 196 depends on the following opcode
|
| /external/llvm/lib/MC/MCParser/ |
| AsmParser.cpp | 828 MCBinaryExpr::Opcode &Kind) {
911 MCBinaryExpr::Opcode Kind = MCBinaryExpr::Add;
927 MCBinaryExpr::Opcode Dummy;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 178 // Get opcode and regclass of the output for the given load instruction.
236 // Get opcode and regclass of the output for the given store instruction.
320 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
339 unsigned Opcode = Instruction::UserOp1;
346 Opcode = I->getOpcode();
350 Opcode = C->getOpcode();
360 switch (Opcode) {
599 unsigned Opcode = Instruction::UserOp1;
601 Opcode = I->getOpcode();
604 Opcode = C->getOpcode()
[all...] |
| X86ISelDAGToDAG.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
