1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that X86 uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef X86ISELLOWERING_H 16 #define X86ISELLOWERING_H 17 18 #include "X86Subtarget.h" 19 #include "X86RegisterInfo.h" 20 #include "X86MachineFunctionInfo.h" 21 #include "llvm/Target/TargetLowering.h" 22 #include "llvm/Target/TargetOptions.h" 23 #include "llvm/CodeGen/FastISel.h" 24 #include "llvm/CodeGen/SelectionDAG.h" 25 #include "llvm/CodeGen/CallingConvLower.h" 26 27 namespace llvm { 28 namespace X86ISD { 29 // X86 Specific DAG Nodes 30 enum NodeType { 31 // Start the numbering where the builtin ops leave off. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 /// BSF - Bit scan forward. 35 /// BSR - Bit scan reverse. 36 BSF, 37 BSR, 38 39 /// SHLD, SHRD - Double shift instructions. These correspond to 40 /// X86::SHLDxx and X86::SHRDxx instructions. 41 SHLD, 42 SHRD, 43 44 /// FAND - Bitwise logical AND of floating point values. This corresponds 45 /// to X86::ANDPS or X86::ANDPD. 46 FAND, 47 48 /// FOR - Bitwise logical OR of floating point values. This corresponds 49 /// to X86::ORPS or X86::ORPD. 50 FOR, 51 52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds 53 /// to X86::XORPS or X86::XORPD. 54 FXOR, 55 56 /// FSRL - Bitwise logical right shift of floating point values. These 57 /// corresponds to X86::PSRLDQ. 58 FSRL, 59 60 /// CALL - These operations represent an abstract X86 call 61 /// instruction, which includes a bunch of information. In particular the 62 /// operands of these node are: 63 /// 64 /// #0 - The incoming token chain 65 /// #1 - The callee 66 /// #2 - The number of arg bytes the caller pushes on the stack. 67 /// #3 - The number of arg bytes the callee pops off the stack. 68 /// #4 - The value to pass in AL/AX/EAX (optional) 69 /// #5 - The value to pass in DL/DX/EDX (optional) 70 /// 71 /// The result values of these nodes are: 72 /// 73 /// #0 - The outgoing token chain 74 /// #1 - The first register result value (optional) 75 /// #2 - The second register result value (optional) 76 /// 77 CALL, 78 79 /// RDTSC_DAG - This operation implements the lowering for 80 /// readcyclecounter 81 RDTSC_DAG, 82 83 /// X86 compare and logical compare instructions. 84 CMP, COMI, UCOMI, 85 86 /// X86 bit-test instructions. 87 BT, 88 89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS 90 /// operand, usually produced by a CMP instruction. 91 SETCC, 92 93 // Same as SETCC except it's materialized with a sbb and the value is all 94 // one's or all zero's. 95 SETCC_CARRY, // R = carry_bit ? ~0 : 0 96 97 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. 98 /// Operands are two FP values to compare; result is a mask of 99 /// 0s or 1s. Generally DTRT for C/C++ with NaNs. 100 FSETCCss, FSETCCsd, 101 102 /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, 103 /// result in an integer GPR. Needs masking for scalar result. 104 FGETSIGNx86, 105 106 /// X86 conditional moves. Operand 0 and operand 1 are the two values 107 /// to select from. Operand 2 is the condition code, and operand 3 is the 108 /// flag operand produced by a CMP or TEST instruction. It also writes a 109 /// flag result. 110 CMOV, 111 112 /// X86 conditional branches. Operand 0 is the chain operand, operand 1 113 /// is the block to branch if condition is true, operand 2 is the 114 /// condition code, and operand 3 is the flag operand produced by a CMP 115 /// or TEST instruction. 116 BRCOND, 117 118 /// Return with a flag operand. Operand 0 is the chain operand, operand 119 /// 1 is the number of bytes of stack to pop. 120 RET_FLAG, 121 122 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 123 REP_STOS, 124 125 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 126 REP_MOVS, 127 128 /// GlobalBaseReg - On Darwin, this node represents the result of the popl 129 /// at function entry, used for PIC code. 130 GlobalBaseReg, 131 132 /// Wrapper - A wrapper node for TargetConstantPool, 133 /// TargetExternalSymbol, and TargetGlobalAddress. 134 Wrapper, 135 136 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 137 /// relative displacements. 138 WrapperRIP, 139 140 /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word 141 /// of an XMM vector, with the high word zero filled. 142 MOVQ2DQ, 143 144 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector 145 /// to an MMX vector. If you think this is too close to the previous 146 /// mnemonic, so do I; blame Intel. 147 MOVDQ2Q, 148 149 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 150 /// i32, corresponds to X86::PEXTRB. 151 PEXTRB, 152 153 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 154 /// i32, corresponds to X86::PEXTRW. 155 PEXTRW, 156 157 /// INSERTPS - Insert any element of a 4 x float vector into any element 158 /// of a destination 4 x floatvector. 159 INSERTPS, 160 161 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 162 /// corresponds to X86::PINSRB. 163 PINSRB, 164 165 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 166 /// corresponds to X86::PINSRW. 167 PINSRW, MMX_PINSRW, 168 169 /// PSHUFB - Shuffle 16 8-bit values within a vector. 170 PSHUFB, 171 172 /// ANDNP - Bitwise Logical AND NOT of Packed FP values. 173 ANDNP, 174 175 /// PSIGN - Copy integer sign. 176 PSIGN, 177 178 /// BLENDV - Blend where the selector is an XMM. 179 BLENDV, 180 181 /// BLENDxx - Blend where the selector is an immediate. 182 BLENDPW, 183 BLENDPS, 184 BLENDPD, 185 186 /// HADD - Integer horizontal add. 187 HADD, 188 189 /// HSUB - Integer horizontal sub. 190 HSUB, 191 192 /// FHADD - Floating point horizontal add. 193 FHADD, 194 195 /// FHSUB - Floating point horizontal sub. 196 FHSUB, 197 198 /// FMAX, FMIN - Floating point max and min. 199 /// 200 FMAX, FMIN, 201 202 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 203 /// approximation. Note that these typically require refinement 204 /// in order to obtain suitable precision. 205 FRSQRT, FRCP, 206 207 // TLSADDR - Thread Local Storage. 208 TLSADDR, 209 210 // TLSCALL - Thread Local Storage. When calling to an OS provided 211 // thunk at the address from an earlier relocation. 212 TLSCALL, 213 214 // EH_RETURN - Exception Handling helpers. 215 EH_RETURN, 216 217 /// TC_RETURN - Tail call return. 218 /// operand #0 chain 219 /// operand #1 callee (register or absolute) 220 /// operand #2 stack adjustment 221 /// operand #3 optional in flag 222 TC_RETURN, 223 224 // VZEXT_MOVL - Vector move low and zero extend. 225 VZEXT_MOVL, 226 227 // VSEXT_MOVL - Vector move low and sign extend. 228 VSEXT_MOVL, 229 230 // VSHL, VSRL - 128-bit vector logical left / right shift 231 VSHLDQ, VSRLDQ, 232 233 // VSHL, VSRL, VSRA - Vector shift elements 234 VSHL, VSRL, VSRA, 235 236 // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate 237 VSHLI, VSRLI, VSRAI, 238 239 // CMPP - Vector packed double/float comparison. 240 CMPP, 241 242 // PCMP* - Vector integer comparisons. 243 PCMPEQ, PCMPGT, 244 245 // VPCOM, VPCOMU - XOP Vector integer comparisons. 246 VPCOM, VPCOMU, 247 248 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results. 249 ADD, SUB, ADC, SBB, SMUL, 250 INC, DEC, OR, XOR, AND, 251 252 ANDN, // ANDN - Bitwise AND NOT with FLAGS results. 253 254 BLSI, // BLSI - Extract lowest set isolated bit 255 BLSMSK, // BLSMSK - Get mask up to lowest set bit 256 BLSR, // BLSR - Reset lowest set bit 257 258 UMUL, // LOW, HI, FLAGS = umul LHS, RHS 259 260 // MUL_IMM - X86 specific multiply by immediate. 261 MUL_IMM, 262 263 // PTEST - Vector bitwise comparisons 264 PTEST, 265 266 // TESTP - Vector packed fp sign bitwise comparisons 267 TESTP, 268 269 // Several flavors of instructions with vector shuffle behaviors. 270 PALIGN, 271 PSHUFD, 272 PSHUFHW, 273 PSHUFLW, 274 SHUFP, 275 MOVDDUP, 276 MOVSHDUP, 277 MOVSLDUP, 278 MOVLHPS, 279 MOVLHPD, 280 MOVHLPS, 281 MOVLPS, 282 MOVLPD, 283 MOVSD, 284 MOVSS, 285 UNPCKL, 286 UNPCKH, 287 VPERMILP, 288 VPERMV, 289 VPERMI, 290 VPERM2X128, 291 VBROADCAST, 292 293 // PMULUDQ - Vector multiply packed unsigned doubleword integers 294 PMULUDQ, 295 296 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 297 // according to %al. An operator is needed so that this can be expanded 298 // with control flow. 299 VASTART_SAVE_XMM_REGS, 300 301 // WIN_ALLOCA - Windows's _chkstk call to do stack probing. 302 WIN_ALLOCA, 303 304 // SEG_ALLOCA - For allocating variable amounts of stack space when using 305 // segmented stacks. Check if the current stacklet has enough space, and 306 // falls back to heap allocation if not. 307 SEG_ALLOCA, 308 309 // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui. 310 WIN_FTOL, 311 312 // Memory barrier 313 MEMBARRIER, 314 MFENCE, 315 SFENCE, 316 LFENCE, 317 318 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 319 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 320 // Atomic 64-bit binary operations. 321 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 322 ATOMSUB64_DAG, 323 ATOMOR64_DAG, 324 ATOMXOR64_DAG, 325 ATOMAND64_DAG, 326 ATOMNAND64_DAG, 327 ATOMSWAP64_DAG, 328 329 // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap. 330 LCMPXCHG_DAG, 331 LCMPXCHG8_DAG, 332 LCMPXCHG16_DAG, 333 334 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 335 VZEXT_LOAD, 336 337 // FNSTCW16m - Store FP control world into i16 memory. 338 FNSTCW16m, 339 340 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 341 /// integer destination in memory and a FP reg source. This corresponds 342 /// to the X86::FIST*m instructions and the rounding mode change stuff. It 343 /// has two inputs (token chain and address) and two outputs (int value 344 /// and token chain). 345 FP_TO_INT16_IN_MEM, 346 FP_TO_INT32_IN_MEM, 347 FP_TO_INT64_IN_MEM, 348 349 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 350 /// integer source in memory and FP reg result. This corresponds to the 351 /// X86::FILD*m instructions. It has three inputs (token chain, address, 352 /// and source type) and two outputs (FP value and token chain). FILD_FLAG 353 /// also produces a flag). 354 FILD, 355 FILD_FLAG, 356 357 /// FLD - This instruction implements an extending load to FP stack slots. 358 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 359 /// operand, ptr to load from, and a ValueType node indicating the type 360 /// to load to. 361 FLD, 362 363 /// FST - This instruction implements a truncating store to FP stack 364 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 365 /// chain operand, value to store, address, and a ValueType to store it 366 /// as. 367 FST, 368 369 /// VAARG_64 - This instruction grabs the address of the next argument 370 /// from a va_list. (reads and modifies the va_list in memory) 371 VAARG_64 372 373 // WARNING: Do not add anything in the end unless you want the node to 374 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be 375 // thought as target memory ops! 376 }; 377 } 378 379 /// Define some predicates that are used for node matching. 380 namespace X86 { 381 /// isVEXTRACTF128Index - Return true if the specified 382 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is 383 /// suitable for input to VEXTRACTF128. 384 bool isVEXTRACTF128Index(SDNode *N); 385 386 /// isVINSERTF128Index - Return true if the specified 387 /// INSERT_SUBVECTOR operand specifies a subvector insert that is 388 /// suitable for input to VINSERTF128. 389 bool isVINSERTF128Index(SDNode *N); 390 391 /// getExtractVEXTRACTF128Immediate - Return the appropriate 392 /// immediate to extract the specified EXTRACT_SUBVECTOR index 393 /// with VEXTRACTF128 instructions. 394 unsigned getExtractVEXTRACTF128Immediate(SDNode *N); 395 396 /// getInsertVINSERTF128Immediate - Return the appropriate 397 /// immediate to insert at the specified INSERT_SUBVECTOR index 398 /// with VINSERTF128 instructions. 399 unsigned getInsertVINSERTF128Immediate(SDNode *N); 400 401 /// isZeroNode - Returns true if Elt is a constant zero or a floating point 402 /// constant +0.0. 403 bool isZeroNode(SDValue Elt); 404 405 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 406 /// fit into displacement field of the instruction. 407 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 408 bool hasSymbolicDisplacement = true); 409 410 411 /// isCalleePop - Determines whether the callee is required to pop its 412 /// own arguments. Callee pop is necessary to support tail calls. 413 bool isCalleePop(CallingConv::ID CallingConv, 414 bool is64Bit, bool IsVarArg, bool TailCallOpt); 415 } 416 417 //===--------------------------------------------------------------------===// 418 // X86TargetLowering - X86 Implementation of the TargetLowering interface 419 class X86TargetLowering : public TargetLowering { 420 public: 421 explicit X86TargetLowering(X86TargetMachine &TM); 422 423 virtual unsigned getJumpTableEncoding() const; 424 425 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; } 426 427 virtual const MCExpr * 428 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 429 const MachineBasicBlock *MBB, unsigned uid, 430 MCContext &Ctx) const; 431 432 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 433 /// jumptable. 434 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 435 SelectionDAG &DAG) const; 436 virtual const MCExpr * 437 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 438 unsigned JTI, MCContext &Ctx) const; 439 440 /// getStackPtrReg - Return the stack pointer register we are using: either 441 /// ESP or RSP. 442 unsigned getStackPtrReg() const { return X86StackPtr; } 443 444 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 445 /// function arguments in the caller parameter area. For X86, aggregates 446 /// that contains are placed at 16-byte boundaries while the rest are at 447 /// 4-byte boundaries. 448 virtual unsigned getByValTypeAlignment(Type *Ty) const; 449 450 /// getOptimalMemOpType - Returns the target specific optimal type for load 451 /// and store operations as a result of memset, memcpy, and memmove 452 /// lowering. If DstAlign is zero that means it's safe to destination 453 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 454 /// means there isn't a need to check it against alignment requirement, 455 /// probably because the source does not need to be loaded. If 456 /// 'IsZeroVal' is true, that means it's safe to return a 457 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 458 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 459 /// constant so it does not need to be loaded. 460 /// It returns EVT::Other if the type should be determined using generic 461 /// target-independent logic. 462 virtual EVT 463 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 464 bool IsZeroVal, bool MemcpyStrSrc, 465 MachineFunction &MF) const; 466 467 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 468 /// unaligned memory accesses. of the specified type. 469 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 470 return true; 471 } 472 473 /// LowerOperation - Provide custom lowering hooks for some operations. 474 /// 475 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 476 477 /// ReplaceNodeResults - Replace the results of node with an illegal result 478 /// type with new values built out of custom code. 479 /// 480 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 481 SelectionDAG &DAG) const; 482 483 484 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 485 486 /// isTypeDesirableForOp - Return true if the target has native support for 487 /// the specified value type and it is 'desirable' to use the type for the 488 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 489 /// instruction encodings are longer and some i16 instructions are slow. 490 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const; 491 492 /// isTypeDesirable - Return true if the target has native support for the 493 /// specified value type and it is 'desirable' to use the type. e.g. On x86 494 /// i16 is legal, but undesirable since i16 instruction encodings are longer 495 /// and some i16 instructions are slow. 496 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const; 497 498 virtual MachineBasicBlock * 499 EmitInstrWithCustomInserter(MachineInstr *MI, 500 MachineBasicBlock *MBB) const; 501 502 503 /// getTargetNodeName - This method returns the name of a target specific 504 /// DAG node. 505 virtual const char *getTargetNodeName(unsigned Opcode) const; 506 507 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 508 virtual EVT getSetCCResultType(EVT VT) const; 509 510 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 511 /// in Mask are known to be either zero or one and return them in the 512 /// KnownZero/KnownOne bitsets. 513 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 514 APInt &KnownZero, 515 APInt &KnownOne, 516 const SelectionDAG &DAG, 517 unsigned Depth = 0) const; 518 519 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the 520 // operation that are sign bits. 521 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 522 unsigned Depth) const; 523 524 virtual bool 525 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 526 527 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 528 529 virtual bool ExpandInlineAsm(CallInst *CI) const; 530 531 ConstraintType getConstraintType(const std::string &Constraint) const; 532 533 /// Examine constraint string and operand type and determine a weight value. 534 /// The operand object must already have been set up with the operand type. 535 virtual ConstraintWeight getSingleConstraintMatchWeight( 536 AsmOperandInfo &info, const char *constraint) const; 537 538 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 539 540 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 541 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 542 /// true it means one of the asm constraint of the inline asm instruction 543 /// being processed is 'm'. 544 virtual void LowerAsmOperandForConstraint(SDValue Op, 545 std::string &Constraint, 546 std::vector<SDValue> &Ops, 547 SelectionDAG &DAG) const; 548 549 /// getRegForInlineAsmConstraint - Given a physical register constraint 550 /// (e.g. {edx}), return the register number and the register class for the 551 /// register. This should only be used for C_Register constraints. On 552 /// error, this returns a register number of 0. 553 std::pair<unsigned, const TargetRegisterClass*> 554 getRegForInlineAsmConstraint(const std::string &Constraint, 555 EVT VT) const; 556 557 /// isLegalAddressingMode - Return true if the addressing mode represented 558 /// by AM is legal for this target, for a load/store of the specified type. 559 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 560 561 /// isTruncateFree - Return true if it's free to truncate a value of 562 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 563 /// register EAX to i16 by referencing its sub-register AX. 564 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; 565 virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 566 567 /// isZExtFree - Return true if any actual instruction that defines a 568 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 569 /// register. This does not necessarily include registers defined in 570 /// unknown ways, such as incoming arguments, or copies from unknown 571 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 572 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 573 /// all instructions that define 32-bit values implicit zero-extend the 574 /// result out to 64 bits. 575 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const; 576 virtual bool isZExtFree(EVT VT1, EVT VT2) const; 577 578 /// isNarrowingProfitable - Return true if it's profitable to narrow 579 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 580 /// from i32 to i8 but not from i32 to i16. 581 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 582 583 /// isFPImmLegal - Returns true if the target can instruction select the 584 /// specified FP immediate natively. If false, the legalizer will 585 /// materialize the FP immediate as a load from a constant pool. 586 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 587 588 /// isShuffleMaskLegal - Targets can use this to indicate that they only 589 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 590 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 591 /// values are assumed to be legal. 592 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 593 EVT VT) const; 594 595 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 596 /// used by Targets can use this to indicate if there is a suitable 597 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 598 /// pool entry. 599 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 600 EVT VT) const; 601 602 /// ShouldShrinkFPConstant - If true, then instruction selection should 603 /// seek to shrink the FP constant of the specified type to a smaller type 604 /// in order to save space and / or reduce runtime. 605 virtual bool ShouldShrinkFPConstant(EVT VT) const { 606 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 607 // expensive than a straight movsd. On the other hand, it's important to 608 // shrink long double fp constant since fldt is very slow. 609 return !X86ScalarSSEf64 || VT == MVT::f80; 610 } 611 612 const X86Subtarget* getSubtarget() const { 613 return Subtarget; 614 } 615 616 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 617 /// computed in an SSE register, not on the X87 floating point stack. 618 bool isScalarFPTypeInSSEReg(EVT VT) const { 619 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 620 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 621 } 622 623 /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine 624 /// for fptoui. 625 bool isTargetFTOL() const { 626 return Subtarget->isTargetWindows() && !Subtarget->is64Bit(); 627 } 628 629 /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be 630 /// used for fptoui to the given type. 631 bool isIntegerTypeFTOL(EVT VT) const { 632 return isTargetFTOL() && VT == MVT::i64; 633 } 634 635 /// createFastISel - This method returns a target specific FastISel object, 636 /// or null if the target does not support "fast" ISel. 637 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const; 638 639 /// getStackCookieLocation - Return true if the target stores stack 640 /// protector cookies at a fixed offset in some non-standard address 641 /// space, and populates the address space and offset as 642 /// appropriate. 643 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const; 644 645 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 646 SelectionDAG &DAG) const; 647 648 protected: 649 std::pair<const TargetRegisterClass*, uint8_t> 650 findRepresentativeClass(EVT VT) const; 651 652 private: 653 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 654 /// make the right decision when generating code for different targets. 655 const X86Subtarget *Subtarget; 656 const X86RegisterInfo *RegInfo; 657 const TargetData *TD; 658 659 /// X86StackPtr - X86 physical register used as stack ptr. 660 unsigned X86StackPtr; 661 662 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 663 /// floating point ops. 664 /// When SSE is available, use it for f32 operations. 665 /// When SSE2 is available, use it for f64 operations. 666 bool X86ScalarSSEf32; 667 bool X86ScalarSSEf64; 668 669 /// LegalFPImmediates - A list of legal fp immediates. 670 std::vector<APFloat> LegalFPImmediates; 671 672 /// addLegalFPImmediate - Indicate that this x86 target can instruction 673 /// select the specified FP immediate natively. 674 void addLegalFPImmediate(const APFloat& Imm) { 675 LegalFPImmediates.push_back(Imm); 676 } 677 678 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 679 CallingConv::ID CallConv, bool isVarArg, 680 const SmallVectorImpl<ISD::InputArg> &Ins, 681 DebugLoc dl, SelectionDAG &DAG, 682 SmallVectorImpl<SDValue> &InVals) const; 683 SDValue LowerMemArgument(SDValue Chain, 684 CallingConv::ID CallConv, 685 const SmallVectorImpl<ISD::InputArg> &ArgInfo, 686 DebugLoc dl, SelectionDAG &DAG, 687 const CCValAssign &VA, MachineFrameInfo *MFI, 688 unsigned i) const; 689 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 690 DebugLoc dl, SelectionDAG &DAG, 691 const CCValAssign &VA, 692 ISD::ArgFlagsTy Flags) const; 693 694 // Call lowering helpers. 695 696 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 697 /// for tail call optimization. Targets which want to do tail call 698 /// optimization should implement this function. 699 bool IsEligibleForTailCallOptimization(SDValue Callee, 700 CallingConv::ID CalleeCC, 701 bool isVarArg, 702 bool isCalleeStructRet, 703 bool isCallerStructRet, 704 const SmallVectorImpl<ISD::OutputArg> &Outs, 705 const SmallVectorImpl<SDValue> &OutVals, 706 const SmallVectorImpl<ISD::InputArg> &Ins, 707 SelectionDAG& DAG) const; 708 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const; 709 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 710 SDValue Chain, bool IsTailCall, bool Is64Bit, 711 int FPDiff, DebugLoc dl) const; 712 713 unsigned GetAlignedArgumentStackSize(unsigned StackSize, 714 SelectionDAG &DAG) const; 715 716 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 717 bool isSigned, 718 bool isReplace) const; 719 720 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 721 SelectionDAG &DAG) const; 722 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 723 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 724 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 725 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 726 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 727 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 728 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 729 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 730 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 731 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 732 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 733 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 734 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 735 int64_t Offset, SelectionDAG &DAG) const; 736 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 737 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 738 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 739 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const; 740 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const; 741 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 742 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 743 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const; 744 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const; 745 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 746 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const; 747 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; 748 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const; 749 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 750 SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const; 751 SDValue LowerToBT(SDValue And, ISD::CondCode CC, 752 DebugLoc dl, SelectionDAG &DAG) const; 753 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 754 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; 755 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 756 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 757 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const; 758 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 759 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 760 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 761 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 762 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 763 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 764 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 765 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 766 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const; 767 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 768 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 769 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 770 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 771 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const; 772 SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const; 773 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const; 774 SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const; 775 SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const; 776 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 777 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const; 778 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const; 779 780 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 781 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 782 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const; 783 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const; 784 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 785 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 786 SDValue PerformTruncateCombine(SDNode* N, SelectionDAG &DAG, DAGCombinerInfo &DCI) const; 787 788 // Utility functions to help LowerVECTOR_SHUFFLE 789 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const; 790 SDValue LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const; 791 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const; 792 793 virtual SDValue 794 LowerFormalArguments(SDValue Chain, 795 CallingConv::ID CallConv, bool isVarArg, 796 const SmallVectorImpl<ISD::InputArg> &Ins, 797 DebugLoc dl, SelectionDAG &DAG, 798 SmallVectorImpl<SDValue> &InVals) const; 799 virtual SDValue 800 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, 801 bool isVarArg, bool doesNotRet, bool &isTailCall, 802 const SmallVectorImpl<ISD::OutputArg> &Outs, 803 const SmallVectorImpl<SDValue> &OutVals, 804 const SmallVectorImpl<ISD::InputArg> &Ins, 805 DebugLoc dl, SelectionDAG &DAG, 806 SmallVectorImpl<SDValue> &InVals) const; 807 808 virtual SDValue 809 LowerReturn(SDValue Chain, 810 CallingConv::ID CallConv, bool isVarArg, 811 const SmallVectorImpl<ISD::OutputArg> &Outs, 812 const SmallVectorImpl<SDValue> &OutVals, 813 DebugLoc dl, SelectionDAG &DAG) const; 814 815 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const; 816 817 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const; 818 819 virtual EVT 820 getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 821 ISD::NodeType ExtendKind) const; 822 823 virtual bool 824 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 825 bool isVarArg, 826 const SmallVectorImpl<ISD::OutputArg> &Outs, 827 LLVMContext &Context) const; 828 829 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results, 830 SelectionDAG &DAG, unsigned NewOp) const; 831 832 /// Utility function to emit string processing sse4.2 instructions 833 /// that return in xmm0. 834 /// This takes the instruction to expand, the associated machine basic 835 /// block, the number of args, and whether or not the second arg is 836 /// in memory or not. 837 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, 838 unsigned argNum, bool inMem) const; 839 840 /// Utility functions to emit monitor and mwait instructions. These 841 /// need to make sure that the arguments to the intrinsic are in the 842 /// correct registers. 843 MachineBasicBlock *EmitMonitor(MachineInstr *MI, 844 MachineBasicBlock *BB) const; 845 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const; 846 847 /// Utility function to emit atomic bitwise operations (and, or, xor). 848 /// It takes the bitwise instruction to expand, the associated machine basic 849 /// block, and the associated X86 opcodes for reg/reg and reg/imm. 850 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter( 851 MachineInstr *BInstr, 852 MachineBasicBlock *BB, 853 unsigned regOpc, 854 unsigned immOpc, 855 unsigned loadOpc, 856 unsigned cxchgOpc, 857 unsigned notOpc, 858 unsigned EAXreg, 859 const TargetRegisterClass *RC, 860 bool Invert = false) const; 861 862 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter( 863 MachineInstr *BInstr, 864 MachineBasicBlock *BB, 865 unsigned regOpcL, 866 unsigned regOpcH, 867 unsigned immOpcL, 868 unsigned immOpcH, 869 bool Invert = false) const; 870 871 /// Utility function to emit atomic min and max. It takes the min/max 872 /// instruction to expand, the associated basic block, and the associated 873 /// cmov opcode for moving the min or max value. 874 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, 875 MachineBasicBlock *BB, 876 unsigned cmovOpc) const; 877 878 // Utility function to emit the low-level va_arg code for X86-64. 879 MachineBasicBlock *EmitVAARG64WithCustomInserter( 880 MachineInstr *MI, 881 MachineBasicBlock *MBB) const; 882 883 /// Utility function to emit the xmm reg save portion of va_start. 884 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 885 MachineInstr *BInstr, 886 MachineBasicBlock *BB) const; 887 888 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 889 MachineBasicBlock *BB) const; 890 891 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI, 892 MachineBasicBlock *BB) const; 893 894 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI, 895 MachineBasicBlock *BB, 896 bool Is64Bit) const; 897 898 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, 899 MachineBasicBlock *BB) const; 900 901 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI, 902 MachineBasicBlock *BB) const; 903 904 /// Emit nodes that will be selected as "test Op0,Op0", or something 905 /// equivalent, for use with the given x86 condition code. 906 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const; 907 908 /// Emit nodes that will be selected as "cmp Op0,Op1", or something 909 /// equivalent, for use with the given x86 condition code. 910 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 911 SelectionDAG &DAG) const; 912 }; 913 914 namespace X86 { 915 FastISel *createFastISel(FunctionLoweringInfo &funcInfo); 916 } 917 } 918 919 #endif // X86ISELLOWERING_H 920
