| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 27 case ISD::SRL: return ARM_AM::lsr;
|
| /external/openssl/crypto/sha/asm/ |
| sha512-mips.pl | 84 $SRL="dsrl"; # shift right logical
98 $SRL="srl"; # shift right logical
127 srl $tmp0,@X[0],24 # byte swap($i)
128 srl $tmp1,@X[0],8
159 $SRL $h,$e,@Sigma1[0]
163 $SRL $tmp0,$e,@Sigma1[1]
167 $SRL $tmp0,$e,@Sigma1[2]
174 $SRL $h,$a,@Sigma0[0]
179 $SRL $tmp0,$a,@Sigma0[1
[all...] |
| sha512-sparcv9.pl | 59 $SRL="srlx"; # shift right logical
85 $SRL="srl"; # shift right logical
222 $SRL $e,@Sigma1[0],$h !! $i
226 $SRL $e,@Sigma1[1],$tmp0
230 $SRL $e,@Sigma1[2],$tmp0
237 $SRL $a,@Sigma0[0],$h
242 $SRL $a,@Sigma0[1],$tmp0
246 $SRL $a,@Sigma0[2],$tmp0
276 srl $xi,@sigma0[0],$T1 !! Xupdate($i
[all...] |
| /external/libffi/src/mips/ |
| ffitarget.h | 128 # define SRL srl
135 # define SRL dsrl
|
| n32.S | 119 SRL t4, t6, 1*FFI_FLAG_BITS
132 SRL t4, t6, 2*FFI_FLAG_BITS
145 SRL t4, t6, 3*FFI_FLAG_BITS
158 SRL t4, t6, 4*FFI_FLAG_BITS
171 SRL t4, t6, 5*FFI_FLAG_BITS
184 SRL t4, t6, 6*FFI_FLAG_BITS
197 SRL t4, t6, 7*FFI_FLAG_BITS
219 SRL t6, 8*FFI_FLAG_BITS
|
| o32.S | 80 SRL t2, t0, 4 # shift our arg info
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 310 SHL, SRA, SRL, ROTL, ROTR,
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| MSP430ISelLowering.cpp | 97 setOperationAction(ISD::SRL, MVT::i8, Custom);
100 setOperationAction(ISD::SRL, MVT::i16, Custom);
184 case ISD::SRL:
603 case ISD::SRL:
604 return DAG.getNode(MSP430ISD::SRL, dl,
615 if (Opc == ISD::SRL && ShiftAmount) {
617 // srl A, 1 => clrc; rrc A
819 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
[all...] |
| /external/v8/src/mips/ |
| constants-mips.cc | 244 case SRL:
|
| constants-mips.h | 305 SRL = ((0 << 3) + 2),
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 350 } else if (Opcode == ISD::SRL) {
397 Op0.getOperand(0).getOpcode() == ISD::SRL) {
399 Op1.getOperand(0).getOpcode() != ISD::SRL) {
405 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
407 Op1.getOperand(0).getOpcode() != ISD::SRL) {
418 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
425 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
[all...] |
| PPCISelLowering.h | 91 SRL, SRA, SHL,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
567 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
667 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
[all...] |
| LegalizeVectorOps.cpp | 185 case ISD::SRL:
428 // Make sure that the SINT_TO_FP and SRL instructions are available.
430 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
450 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
|
| TargetLowering.cpp | [all...] |
| LegalizeDAG.cpp | 393 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
[all...] |
| DAGCombiner.cpp | [all...] |
| FastISel.cpp | [all...] |
| /external/openssl/crypto/bn/asm/ |
| mips.pl | 62 $SRL="dsrl";
77 $SRL="srl";
903 $SRL $at,$a1,$t1
917 $SRL $DH,$a2,4*$BNSZ # bits
925 $SRL $HH,$a0,4*$BNSZ # bits
926 $SRL $QT,4*$BNSZ # q=0xffffffff
933 $SRL $at,$a1,4*$BNSZ # bits
958 $SRL $HH,$a0,4*$BNSZ # bits
959 $SRL $QT,4*$BNSZ # q=0xfffffff
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 241 setOperationAction(ISD::SRL, MVT::i8, Custom);
246 setOperationAction(ISD::SRL, MVT::i64, Legal);
[all...] |
| SPUISelDAGToDAG.cpp | 230 //! Emit the instruction sequence for i64 srl
743 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
746 // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
765 if (Op0.getOpcode() == ISD::SRL)
779 } else if (Opc == ISD::SRL) {
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsMCInstLower.cpp | 300 Instr2.setOpcode(Mips::SRL);
|
| MipsISelLowering.cpp | 616 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
625 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 472 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
[all...] |
