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    Searched defs:Op0 (Results 1 - 25 of 34) sorted by null

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  /external/llvm/lib/Target/Sparc/
SparcISelDAGToDAG.cpp 192 SDValue Op0, Op1;
196 if (!SelectADDRrr(Op, Op0, Op1))
197 SelectADDRri(Op, Op0, Op1);
201 OutOps.push_back(Op0);
  /external/llvm/lib/Transforms/Scalar/
CorrelatedValuePropagation.cpp 144 Value *Op0 = C->getOperand(0);
145 if (isa<Instruction>(Op0) &&
146 cast<Instruction>(Op0)->getParent() == C->getParent())
  /external/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp 224 MachineOperand &Op0 = MI->getOperand(0);
225 unsigned Reg0 = Op0.getReg();
228 // Handle instructions that have a prediate register in op0
HexagonISelDAGToDAG.cpp 750 SDValue OP0;
760 OP0 = Sext0;
771 OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
807 OP0, OP1);
    [all...]
  /external/llvm/lib/VMCore/
AutoUpgrade.cpp 271 Value *Op0 = CI->getArgOperand(0);
292 Rep = Builder.CreateShuffleVector(Op0, Op0, ConstantVector::get(Idxs));
  /external/llvm/lib/Target/MSP430/
MSP430ISelDAGToDAG.cpp 288 SDValue Op0, Op1;
292 if (!SelectAddr(Op, Op0, Op1))
297 OutOps.push_back(Op0);
  /external/llvm/lib/Target/NVPTX/
NVPTXISelDAGToDAG.cpp 643 SDValue Op0, Op1;
647 if (SelectDirectAddr(Op, Op0)) {
648 OutOps.push_back(Op0);
652 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
653 OutOps.push_back(Op0);
  /external/llvm/lib/Transforms/InstCombine/
InstCombineAddSub.cpp 496 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
498 if (Value *V = SimplifySubInst(Op0, Op1, I.hasNoSignedWrap(),
508 BinaryOperator *Res = BinaryOperator::CreateAdd(Op0, V);
515 return BinaryOperator::CreateXor(Op0, Op1);
518 if (match(Op0, m_AllOnes()))
521 if (ConstantInt *C = dyn_cast<ConstantInt>(Op0)) {
559 if (match(Op1, m_Add(m_Specific(Op0), m_Value(Y))) ||
560 match(Op1, m_Add(m_Value(Y), m_Specific(Op0))))
564 if (match(Op0, m_Sub(m_Specific(Op1), m_Value(Y))))
575 return BinaryOperator::CreateAdd(Op0,
    [all...]
InstCombineShifts.cpp 24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
31 if (isa<Constant>(Op0))
37 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I))
312 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1,
320 CanEvaluateShifted(Op0, Op1->getZExtValue(), isLeftShift, *this)) {
322 " to eliminate shift:\n IN: " << *Op0 << "\n SH: " << I <<"\n");
325 GetShiftedValue(Op0, Op1->getZExtValue(), isLeftShift, *this));
331 uint32_t TypeBits = Op0->getType()->getScalarSizeInBits();
338 return ReplaceInstUsesWith(I, Constant::getNullValue(Op0->getType()));
345 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op0))
    [all...]
InstCombineMulDivRem.cpp 101 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
103 if (Value *V = SimplifyMulInst(Op0, Op1, TD))
110 return BinaryOperator::CreateNeg(Op0, I.getName());
115 if (BinaryOperator *SI = dyn_cast<BinaryOperator>(Op0))
123 Constant *NewCst = ConstantInt::get(Op0->getType(), Val.logBase2());
124 BinaryOperator *Shl = BinaryOperator::CreateShl(Op0, NewCst);
132 if (Op0->hasOneUse() &&
133 match(Op0, m_Add(m_Value(X), m_ConstantInt(C1)))) {
147 if (Op0->hasOneUse()) {
150 if (match(Op0, m_Sub(m_Value(Y), m_Value(X)))
    [all...]
InstCombineCalls.cpp 567 Value *Op0 = Builder->CreateBitCast(II->getArgOperand(0),
571 Value *Result = UndefValue::get(Op0->getType());
586 Builder->CreateExtractElement(Idx < 16 ? Op0 : Op1,
    [all...]
InstCombineCasts.cpp     [all...]
InstCombineAndOrXor.cpp 720 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1);
723 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder);
    [all...]
InstCombineCompares.cpp     [all...]
InstructionCombining.cpp 192 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(I.getOperand(0));
197 if (Op0 && Op0->getOpcode() == Opcode) {
198 Value *A = Op0->getOperand(0);
199 Value *B = Op0->getOperand(1);
210 (!Op0 || (isa<BinaryOperator>(Op0) && Op0->hasNoSignedWrap()))) {
212 // the operands to Op0.
248 if (Op0 && Op0->getOpcode() == Opcode)
    [all...]
  /external/llvm/lib/ExecutionEngine/
ExecutionEngine.cpp 554 Constant *Op0 = CE->getOperand(0);
558 GenericValue Result = getConstantValue(Op0);
560 uint64_t Offset = TD->getIndexedOffset(Op0->getType(), Indices);
567 GenericValue GV = getConstantValue(Op0);
573 GenericValue GV = getConstantValue(Op0);
579 GenericValue GV = getConstantValue(Op0);
586 GenericValue GV = getConstantValue(Op0);
592 GenericValue GV = getConstantValue(Op0);
597 GenericValue GV = getConstantValue(Op0);
612 GenericValue GV = getConstantValue(Op0);
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 392 SDValue Op0 = N->getOperand(0);
397 CurDAG->ComputeMaskedBits(Op0, LKZ, LKO);
404 unsigned Op0Opc = Op0.getOpcode();
413 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
414 Op0.getOperand(0).getOpcode() == ISD::SRL) {
417 std::swap(Op0, Op1);
425 std::swap(Op0, Op1);
452 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
    [all...]
  /external/llvm/lib/Analysis/
ValueTracking.cpp 46 static void ComputeMaskedBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW,
51 if (ConstantInt *CLHS = dyn_cast<ConstantInt>(Op0)) {
81 llvm::ComputeMaskedBits(Op0, LHSKnownZero, LHSKnownOne, TD, Depth+1);
132 static void ComputeMaskedBitsMul(Value *Op0, Value *Op1, bool NSW,
138 ComputeMaskedBits(Op0, KnownZero2, KnownOne2, TD, Depth+1);
146 if (Op0 == Op1) {
161 isKnownNonZero(Op0, TD, Depth)) ||
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp 381 unsigned Op0 = getRegForValue(I->getOperand(0));
382 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail.
406 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
418 ISDOpcode, Op0, Op0IsKill, CF);
436 Op0, Op0IsKill,
749 unsigned Op0 = getRegForValue(I->getOperand(0));
750 if (Op0 == 0)
765 ResultReg).addReg(Op0);
772 ISD::BITCAST, Op0, Op0IsKill);
913 const Value *Op0 = EVI->getOperand(0)
    [all...]
TargetLowering.cpp     [all...]
  /external/llvm/lib/Target/CellSPU/
SPUISelDAGToDAG.cpp 266 SDValue Op0, Op1;
270 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
271 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
272 SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
275 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
276 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
277 Op0 = Op;
285 SelectAddrIdxOnly(Op, Op, Op0, Op1);
290 OutOps.push_back(Op0);
343 SDValue Op0 = N.getOperand(0)
    [all...]
  /external/llvm/lib/Target/ARM/
ARMFastISel.cpp 108 unsigned Op0, bool Op0IsKill);
111 unsigned Op0, bool Op0IsKill,
115 unsigned Op0, bool Op0IsKill,
120 unsigned Op0, bool Op0IsKill,
124 unsigned Op0, bool Op0IsKill,
128 unsigned Op0, bool Op0IsKill,
139 unsigned Op0, bool Op0IsKill,
301 unsigned Op0, bool Op0IsKill) {
307 .addReg(Op0, Op0IsKill * RegState::Kill));
310 .addReg(Op0, Op0IsKill * RegState::Kill))
    [all...]
ARMLoadStoreOptimizer.cpp     [all...]
  /external/llvm/lib/Target/X86/
X86FastISel.cpp 877 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1,
879 unsigned Op0Reg = getRegForValue(Op0);
884 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
919 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
    [all...]
X86ISelDAGToDAG.cpp     [all...]

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