| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 192 SDValue Op0, Op1;
196 if (!SelectADDRrr(Op, Op0, Op1))
197 SelectADDRri(Op, Op0, Op1);
202 OutOps.push_back(Op1);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 275 MachineOperand Op1 = MI->getOperand(S1);
278 ChangeOpInto(MI->getOperand(S2), Op1);
|
| HexagonISelDAGToDAG.cpp | 751 SDValue OP1;
786 OP1 = Sext1;
797 OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
807 OP0, OP1);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 288 SDValue Op0, Op1;
292 if (!SelectAddr(Op, Op0, Op1))
298 OutOps.push_back(Op1);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 643 SDValue Op0, Op1;
652 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
654 OutOps.push_back(Op1);
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 496 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
498 if (Value *V = SimplifySubInst(Op0, Op1, I.hasNoSignedWrap(),
507 if (Value *V = dyn_castNegVal(Op1)) {
515 return BinaryOperator::CreateXor(Op0, Op1);
519 return BinaryOperator::CreateNot(Op1);
524 if (match(Op1, m_Not(m_Value(X))))
531 if (match(Op1, m_LShr(m_Value(X), m_ConstantInt(CI))) &&
536 if (match(Op1, m_AShr(m_Value(X), m_ConstantInt(CI))) &&
543 if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
549 if (match(Op1, m_Add(m_Value(X), m_ConstantInt(C2)))
[all...] |
| InstCombineShifts.cpp | 24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
32 if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
36 if (ConstantInt *CUI = dyn_cast<ConstantInt>(Op1))
44 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) {
48 Op1->getName());
312 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1,
320 CanEvaluateShifted(Op0, Op1->getZExtValue(), isLeftShift, *this)) {
325 GetShiftedValue(Op0, Op1->getZExtValue(), isLeftShift, *this));
336 if (Op1->uge(TypeBits))
[all...] |
| InstCombineMulDivRem.cpp | 101 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
103 if (Value *V = SimplifyMulInst(Op0, Op1, TD))
109 if (match(Op1, m_AllOnes())) // X * -1 == 0 - X
112 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
164 if (isa<Constant>(Op1)) {
176 if (Value *Op1v = dyn_castNegVal(Op1))
182 Value *Op1C = Op1;
188 BO = dyn_cast<BinaryOperator>(Op1);
220 return BinaryOperator::CreateAnd(Op0, Op1);
227 return BinaryOperator::CreateShl(Op1, Y)
[all...] |
| InstCombineCalls.cpp | 569 Value *Op1 = Builder->CreateBitCast(II->getArgOperand(1),
586 Builder->CreateExtractElement(Idx < 16 ? Op0 : Op1,
[all...] |
| InstCombineCasts.cpp | [all...] |
| InstCombineAndOrXor.cpp | 720 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1);
723 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder);
[all...] |
| InstCombineCompares.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 450 SDValue Op1 = Op.getOperand(1);
454 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
472 assert(MaskTy.getSizeInBits() == Op1.getValueType().getSizeInBits()
489 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
496 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
498 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
509 SDValue Op1 = Op.getOperand(1);
526 assert(VT.getSizeInBits() == Op1.getValueType().getSizeInBits(
[all...] |
| FastISel.cpp | 365 unsigned Op1 = getRegForValue(I->getOperand(1));
366 if (Op1 == 0) return false;
370 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
426 unsigned Op1 = getRegForValue(I->getOperand(1));
427 if (Op1 == 0)
437 Op1, Op1IsKill);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 393 SDValue Op1 = N->getOperand(1);
398 CurDAG->ComputeMaskedBits(Op1, RKZ, RKO);
405 unsigned Op1Opc = Op1.getOpcode();
415 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
416 Op1.getOperand(0).getOpcode() != ISD::SRL) {
417 std::swap(Op0, Op1);
423 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
424 Op1.getOperand(0).getOpcode() != ISD::SRL) {
425 std::swap(Op0, Op1);
436 isInt32Immediate(Op1.getOperand(1), Value))
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 160 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS))
161 if (Op1->getOpcode() == OpcodeToExpand) {
163 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1);
198 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS);
201 !Op1 || Op1->getOpcode() != OpcodeToExtract)
206 Value *C = Op1->getOperand(0), *D = Op1->getOperand(1);
269 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)
[all...] |
| ValueTracking.cpp | 46 static void ComputeMaskedBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW,
60 llvm::ComputeMaskedBits(Op1, KnownZero2, KnownOne2, TD, Depth+1);
86 llvm::ComputeMaskedBits(Op1, KnownZero2, KnownOne2, TD, Depth+1);
132 static void ComputeMaskedBitsMul(Value *Op0, Value *Op1, bool NSW,
137 ComputeMaskedBits(Op1, KnownZero, KnownOne, TD, Depth+1);
146 if (Op0 == Op1) {
163 isKnownNonZero(Op1, TD, Depth));
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.cpp | 574 unsigned Op1, Op2, NewDstIdx;
575 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
577 if (Op1 == UseOpIdx)
580 NewDstIdx = Op1;
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 266 SDValue Op0, Op1;
270 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
271 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
272 SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
275 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
276 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
278 Op1 = getSmallIPtrImm(0);
285 SelectAddrIdxOnly(Op, Op, Op0, Op1);
291 OutOps.push_back(Op1);
418 const SDValue Op1 = N.getOperand(1)
[all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 112 unsigned Op1, bool Op1IsKill);
116 unsigned Op1, bool Op1IsKill,
129 unsigned Op1, bool Op1IsKill,
321 unsigned Op1, bool Op1IsKill) {
328 .addReg(Op1, Op1IsKill * RegState::Kill));
332 .addReg(Op1, Op1IsKill * RegState::Kill));
343 unsigned Op1, bool Op1IsKill,
351 .addReg(Op1, Op1IsKill * RegState::Kill)
356 .addReg(Op1, Op1IsKill * RegState::Kill)
412 unsigned Op1, bool Op1IsKill
[all...] |
| ARMLoadStoreOptimizer.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 877 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1,
883 if (isa<ConstantPointerNull>(Op1))
884 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
889 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
901 unsigned Op1Reg = getRegForValue(Op1);
919 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
[all...] |
| X86ISelDAGToDAG.cpp | 323 SDValue Op1 = U->getOperand(1);
335 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
349 if (Op1.getOpcode() == X86ISD::Wrapper) {
350 SDValue Val = Op1.getOperand(0);
[all...] |
