| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2,
76 SDValue Op1, SDValue Op2,
92 SDValue Op1, SDValue Op2,
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 101 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
103 if (Value *V = SimplifyMulInst(Op0, Op1, TD))
109 if (match(Op1, m_AllOnes())) // X * -1 == 0 - X
112 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
164 if (isa<Constant>(Op1)) {
176 if (Value *Op1v = dyn_castNegVal(Op1))
182 Value *Op1C = Op1;
188 BO = dyn_cast<BinaryOperator>(Op1);
220 return BinaryOperator::CreateAnd(Op0, Op1);
227 return BinaryOperator::CreateShl(Op1, Y)
[all...] |
| InstCombineShifts.cpp | 24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
32 if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
36 if (ConstantInt *CUI = dyn_cast<ConstantInt>(Op1))
44 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) {
48 Op1->getName());
312 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1,
320 CanEvaluateShifted(Op0, Op1->getZExtValue(), isLeftShift, *this)) {
325 GetShiftedValue(Op0, Op1->getZExtValue(), isLeftShift, *this));
336 if (Op1->uge(TypeBits))
[all...] |
| InstCombineAddSub.cpp | 496 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
498 if (Value *V = SimplifySubInst(Op0, Op1, I.hasNoSignedWrap(),
507 if (Value *V = dyn_castNegVal(Op1)) {
515 return BinaryOperator::CreateXor(Op0, Op1);
519 return BinaryOperator::CreateNot(Op1);
524 if (match(Op1, m_Not(m_Value(X))))
531 if (match(Op1, m_LShr(m_Value(X), m_ConstantInt(CI))) &&
536 if (match(Op1, m_AShr(m_Value(X), m_ConstantInt(CI))) &&
543 if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
549 if (match(Op1, m_Add(m_Value(X), m_ConstantInt(C2)))
[all...] |
| InstCombineAndOrXor.cpp | 720 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1);
723 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder);
[all...] |
| InstCombineCompares.cpp | [all...] |
| InstructionCombining.cpp | 193 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(I.getOperand(1));
226 if (Op1 && Op1->getOpcode() == Opcode) {
228 Value *B = Op1->getOperand(0);
229 Value *C = Op1->getOperand(1);
268 if (Op1 && Op1->getOpcode() == Opcode) {
270 Value *B = Op1->getOperand(0);
271 Value *C = Op1->getOperand(1);
289 if (Op0 && Op1 &
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 160 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS))
161 if (Op1->getOpcode() == OpcodeToExpand) {
163 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1);
198 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS);
201 !Op1 || Op1->getOpcode() != OpcodeToExtract)
206 Value *C = Op1->getOperand(0), *D = Op1->getOperand(1);
269 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)
[all...] |
| ConstantFolding.cpp | 541 /// SymbolicallyEvaluateBinop - One of Op0/Op1 is a constant expression.
546 Constant *Op1, const TargetData *TD){
561 if (IsConstantOffsetFromGlobal(Op1, GV2, Offs2, *TD) &&
[all...] |
| ValueTracking.cpp | 46 static void ComputeMaskedBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW,
60 llvm::ComputeMaskedBits(Op1, KnownZero2, KnownOne2, TD, Depth+1);
86 llvm::ComputeMaskedBits(Op1, KnownZero2, KnownOne2, TD, Depth+1);
132 static void ComputeMaskedBitsMul(Value *Op0, Value *Op1, bool NSW,
137 ComputeMaskedBits(Op1, KnownZero, KnownOne, TD, Depth+1);
146 if (Op0 == Op1) {
163 isKnownNonZero(Op1, TD, Depth));
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 60 SDValue Op1, SDValue Op2,
|
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 184 unsigned Op1, bool Op1IsKill);
214 unsigned Op1, bool Op1IsKill,
261 unsigned Op1, bool Op1IsKill);
269 unsigned Op1, bool Op1IsKill,
302 unsigned Op1, bool Op1IsKill,
311 unsigned Op1, bool Op1IsKill,
|
| SelectionDAG.h | 527 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
532 Ops.push_back(Op1);
752 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
753 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2
[all...] |
| ISDOpcodes.h | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 266 SDValue Op0, Op1;
270 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
271 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
272 SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
275 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
276 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
278 Op1 = getSmallIPtrImm(0);
285 SelectAddrIdxOnly(Op, Op, Op0, Op1);
291 OutOps.push_back(Op1);
418 const SDValue Op1 = N.getOperand(1)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 192 SDValue Op0, Op1;
196 if (!SelectADDRrr(Op, Op0, Op1))
197 SelectADDRri(Op, Op0, Op1);
202 OutOps.push_back(Op1);
|
| /external/llvm/lib/Transforms/Scalar/ |
| CorrelatedValuePropagation.cpp | 149 Constant *Op1 = dyn_cast<Constant>(C->getOperand(1));
150 if (!Op1) return false;
156 C->getOperand(0), Op1, *PI, C->getParent());
162 C->getOperand(0), Op1, *PI, C->getParent());
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 450 SDValue Op1 = Op.getOperand(1);
454 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
472 assert(MaskTy.getSizeInBits() == Op1.getValueType().getSizeInBits()
489 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
496 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
498 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
509 SDValue Op1 = Op.getOperand(1);
526 assert(VT.getSizeInBits() == Op1.getValueType().getSizeInBits(
[all...] |
| FastISel.cpp | 365 unsigned Op1 = getRegForValue(I->getOperand(1));
366 if (Op1 == 0) return false;
370 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
426 unsigned Op1 = getRegForValue(I->getOperand(1));
427 if (Op1 == 0)
437 Op1, Op1IsKill);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 393 SDValue Op1 = N->getOperand(1);
398 CurDAG->ComputeMaskedBits(Op1, RKZ, RKO);
405 unsigned Op1Opc = Op1.getOpcode();
415 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
416 Op1.getOperand(0).getOpcode() != ISD::SRL) {
417 std::swap(Op0, Op1);
423 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
424 Op1.getOperand(0).getOpcode() != ISD::SRL) {
425 std::swap(Op0, Op1);
436 isInt32Immediate(Op1.getOperand(1), Value))
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| InstructionSimplify.h | 90 Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW,
97 Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact,
104 Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact,
|
| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FloatingPoint.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 275 MachineOperand Op1 = MI->getOperand(S1);
278 ChangeOpInto(MI->getOperand(S2), Op1);
|
