| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.h | 38 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
40 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
42 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
46 /// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicates
49 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
52 /// and punpckh*. VT indicates the type of the vector allowing it to handle
54 void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
57 /// and punpckl*. VT indicates the type of the vector allowing it to handle
59 void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
62 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm
[all...] |
| X86ShuffleDecode.cpp | 64 void DecodePALIGNRMask(MVT VT, unsigned Imm,
66 unsigned NumElts = VT.getVectorNumElements();
67 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8);
69 unsigned NumLanes = VT.getSizeInBits() / 128;
83 /// VT indicates the type of the vector allowing it to handle different
85 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
86 unsigned NumElts = VT.getVectorNumElements();
88 unsigned NumLanes = VT.getSizeInBits() / 128;
101 void DecodePSHUFHWMask(MVT VT, unsigned Imm,
103 unsigned NumElts = VT.getVectorNumElements()
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 161 virtual bool shouldSplitVectorElementType(EVT VT) const { return false; }
196 virtual EVT getSetCCResultType(EVT VT) const;
231 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
232 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
242 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
243 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
249 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
250 return RepRegClassCostForVT[VT.SimpleTy];
256 bool isTypeLegal(EVT VT) const {
257 assert(!VT.isSimple() |
[all...] |
| TargetCallingConv.h | 113 MVT VT;
124 InputArg() : VT(MVT::Other), Used(false) {}
125 InputArg(ArgFlagsTy flags, EVT vt, bool used,
128 VT = vt.getSimpleVT();
138 MVT VT;
152 OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed,
156 VT = vt.getSimpleVT();
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 116 EVT VT = Op.getValueType();
123 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
127 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
129 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
132 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
135 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
138 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
141 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
144 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
147 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1))
[all...] |
| SIRegisterInfo.cpp | 43 MVT VT) const {
44 switch(VT.SimpleTy) {
|
| R600RegisterInfo.h | 45 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
|
| SIRegisterInfo.h | 42 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
|
| AMDILISelLowering.cpp | 96 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
100 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
101 setOperationAction(ISD::SUBE, VT, Expand);
102 setOperationAction(ISD::SUBC, VT, Expand);
103 setOperationAction(ISD::ADDE, VT, Expand);
104 setOperationAction(ISD::ADDC, VT, Expand);
105 setOperationAction(ISD::BRCOND, VT, Custom);
106 setOperationAction(ISD::BR_JT, VT, Expand);
107 setOperationAction(ISD::BRIND, VT, Expand);
109 setOperationAction(ISD::SREM, VT, Expand)
[all...] |
| AMDGPURegisterInfo.h | 50 virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
|
| /libcore/luni/src/main/java/java/util/ |
| EnumMap.java | 51 private static class Entry<KT extends Enum<KT>, VT> extends
52 MapEntry<KT, VT> {
53 private final EnumMap<KT, VT> enumMap;
57 Entry(KT theKey, VT theValue, EnumMap<KT, VT> em) {
71 Map.Entry<KT, VT> entry = (Map.Entry<KT, VT>) object;
102 public VT getValue() {
104 return (VT) enumMap.values[ordinal];
109 public VT setValue(VT value)
[all...] |
| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 72 MVT ArgVT = Ins[i].VT;
90 MVT VT = Outs[i].VT;
92 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
104 MVT VT = Outs[i].VT;
106 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
109 << EVT(VT).getEVTString() << '\n'
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 353 SDVTList getVTList(EVT VT);
362 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false);
363 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false);
364 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false);
366 SDValue getTargetConstant(uint64_t Val, EVT VT) {
367 return getConstant(Val, VT, true);
369 SDValue getTargetConstant(const APInt &Val, EVT VT) {
370 return getConstant(Val, VT, true);
372 SDValue getTargetConstant(const ConstantInt &Val, EVT VT) {
373 return getConstant(Val, VT, true)
[all...] |
| ValueTypes.h | 421 /// Return true if this has more bits than VT.
422 bool bitsGT(MVT VT) const {
423 return getSizeInBits() > VT.getSizeInBits();
426 /// Return true if this has no less bits than VT.
427 bool bitsGE(MVT VT) const {
428 return getSizeInBits() >= VT.getSizeInBits();
431 /// Return true if this has less bits than VT.
432 bool bitsLT(MVT VT) const {
433 return getSizeInBits() < VT.getSizeInBits();
436 /// Return true if this has no more bits than VT
[all...] |
| FastISel.h | 177 virtual unsigned FastEmit_(MVT VT,
185 virtual unsigned FastEmit_r(MVT VT,
194 virtual unsigned FastEmit_rr(MVT VT,
204 virtual unsigned FastEmit_ri(MVT VT,
214 virtual unsigned FastEmit_rf(MVT VT,
224 virtual unsigned FastEmit_rri(MVT VT,
235 unsigned FastEmit_ri_(MVT VT,
243 virtual unsigned FastEmit_i(MVT VT,
251 virtual unsigned FastEmit_f(MVT VT,
347 unsigned FastEmitZExtFromI1(MVT VT,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | 79 bool ConstantFPSDNode::isValueValidForType(EVT VT,
81 assert(VT.isFloatingPoint() && "Can only convert between FP types");
86 (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT),
673 EVT VT = cast<VTSDNode>(N)->getVT();
674 if (VT.isExtended()) {
675 Erased = ExtendedValueTypeNodes.erase(VT);
677 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0;
678 ValueTypeNodes[VT.getSimpleVT().SimpleTy] = 0;
793 EVT VT = N->getValueType(0);
795 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) &
[all...] |
| DAGCombiner.cpp | 259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
263 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
333 /// legalization or if the specified VT is legal.
334 bool isTypeLegal(const EVT &VT) {
336 return TLI.isTypeLegal(VT);
578 EVT VT = N0.getValueType();
583 DAG.FoldConstantArithmetic(Opc, VT,
586 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
590 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
593 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1))
[all...] |
| LegalizeVectorOps.cpp | 319 MVT VT = Op.getSimpleValueType();
322 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
335 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
341 EVT VT = Op.getOperand(0).getValueType();
352 unsigned NumElts = VT.getVectorNumElements();
353 EVT EltVT = VT.getVectorElementType();
576 EVT VT = Op.getValueType();
583 assert(VT.isVector() && !Mask.getValueType().isVector()
586 unsigned NumElem = VT.getVectorNumElements();
593 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand |
[all...] |
| TargetLowering.cpp | 102 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
106 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
114 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
115 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
119 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
120 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
124 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
125 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128
[all...] |
| FastISel.cpp | 152 MVT VT = RealVT.getSimpleVT();
153 if (!TLI.isTypeLegal(VT)) {
155 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
156 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
177 Reg = materializeRegForValue(V, VT);
187 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
192 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue())
[all...] |
| LegalizeDAG.cpp | 90 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
94 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
184 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
187 unsigned NumMaskElts = VT.getVectorNumElements();
258 EVT VT = CFP->getValueType(0);
261 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
263 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
266 EVT OrigVT = VT;
267 EVT SVT = VT;
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 81 EVT ArgVT = Ins[i].VT;
117 EVT VT = Outs[i].VT;
119 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this, -1, -1, false)){
121 << VT.getEVTString() << "\n";
147 EVT ArgVT = Outs[i].VT;
185 EVT VT = Ins[i].VT;
187 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this, -1, -1, false))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
73 VT.getVectorNumElements()/Factor);
112 EVT VT = Vec.getValueType();
113 assert(VT.is128BitVector() && "Unexpected vector size!");
115 EVT ElVT = VT.getVectorElementType();
135 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.h | 88 bool isTypeSupportedInIntrinsic(MVT VT) const;
103 virtual EVT getSetCCResultType(EVT VT) const {
104 if (VT.isVector())
105 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
111 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
143 virtual bool shouldSplitVectorElementType(EVT VT) const;
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.h | 24 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
|
