1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the AArch64 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGET_AARCH64INSTRINFO_H 15 #define LLVM_TARGET_AARCH64INSTRINFO_H 16 17 #include "llvm/Target/TargetInstrInfo.h" 18 #include "AArch64RegisterInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #include "AArch64GenInstrInfo.inc" 22 23 namespace llvm { 24 25 class AArch64Subtarget; 26 27 class AArch64InstrInfo : public AArch64GenInstrInfo { 28 const AArch64RegisterInfo RI; 29 const AArch64Subtarget &Subtarget; 30 public: 31 explicit AArch64InstrInfo(const AArch64Subtarget &TM); 32 33 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 34 /// such, whenever a client has an instance of instruction info, it should 35 /// always be able to get register info as well (through this method). 36 /// 37 const TargetRegisterInfo &getRegisterInfo() const { return RI; } 38 39 const AArch64Subtarget &getSubTarget() const { return Subtarget; } 40 41 void copyPhysReg(MachineBasicBlock &MBB, 42 MachineBasicBlock::iterator I, DebugLoc DL, 43 unsigned DestReg, unsigned SrcReg, 44 bool KillSrc) const; 45 46 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, 47 uint64_t Offset, const MDNode *MDPtr, 48 DebugLoc DL) const; 49 50 void storeRegToStackSlot(MachineBasicBlock &MBB, 51 MachineBasicBlock::iterator MI, 52 unsigned SrcReg, bool isKill, int FrameIndex, 53 const TargetRegisterClass *RC, 54 const TargetRegisterInfo *TRI) const; 55 void loadRegFromStackSlot(MachineBasicBlock &MBB, 56 MachineBasicBlock::iterator MBBI, 57 unsigned DestReg, int FrameIdx, 58 const TargetRegisterClass *RC, 59 const TargetRegisterInfo *TRI) const; 60 61 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 62 MachineBasicBlock *&FBB, 63 SmallVectorImpl<MachineOperand> &Cond, 64 bool AllowModify = false) const; 65 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 66 MachineBasicBlock *FBB, 67 const SmallVectorImpl<MachineOperand> &Cond, 68 DebugLoc DL) const; 69 unsigned RemoveBranch(MachineBasicBlock &MBB) const; 70 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 71 72 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 73 74 /// Look through the instructions in this function and work out the largest 75 /// the stack frame can be while maintaining the ability to address local 76 /// slots with no complexities. 77 unsigned estimateRSStackLimit(MachineFunction &MF) const; 78 79 /// getAddressConstraints - For loads and stores (and PRFMs) taking an 80 /// immediate offset, this function determines the constraints required for 81 /// the immediate. It must satisfy: 82 /// + MinOffset <= imm <= MaxOffset 83 /// + imm % OffsetScale == 0 84 void getAddressConstraints(const MachineInstr &MI, int &AccessScale, 85 int &MinOffset, int &MaxOffset) const; 86 87 88 unsigned getInstSizeInBytes(const MachineInstr &MI) const; 89 90 unsigned getInstBundleLength(const MachineInstr &MI) const; 91 92 }; 93 94 bool rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 95 unsigned FrameReg, int &Offset, 96 const AArch64InstrInfo &TII); 97 98 99 void emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 100 DebugLoc dl, const TargetInstrInfo &TII, 101 unsigned DstReg, unsigned SrcReg, unsigned ScratchReg, 102 int64_t NumBytes, 103 MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags); 104 105 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 106 DebugLoc dl, const TargetInstrInfo &TII, 107 unsigned ScratchReg, int64_t NumBytes, 108 MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags); 109 110 } 111 112 #endif 113
