1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the pass that transforms the ARM machine instructions into 11 // relocatable machine code. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "jit" 16 #include "ARM.h" 17 #include "ARMBaseInstrInfo.h" 18 #include "ARMConstantPoolValue.h" 19 #include "ARMRelocations.h" 20 #include "ARMSubtarget.h" 21 #include "ARMTargetMachine.h" 22 #include "MCTargetDesc/ARMAddressingModes.h" 23 #include "llvm/ADT/Statistic.h" 24 #include "llvm/CodeGen/JITCodeEmitter.h" 25 #include "llvm/CodeGen/MachineConstantPool.h" 26 #include "llvm/CodeGen/MachineFunctionPass.h" 27 #include "llvm/CodeGen/MachineInstr.h" 28 #include "llvm/CodeGen/MachineJumpTableInfo.h" 29 #include "llvm/CodeGen/MachineModuleInfo.h" 30 #include "llvm/CodeGen/Passes.h" 31 #include "llvm/IR/Constants.h" 32 #include "llvm/IR/DerivedTypes.h" 33 #include "llvm/IR/Function.h" 34 #include "llvm/PassManager.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/raw_ostream.h" 38 #ifndef NDEBUG 39 #include <iomanip> 40 #endif 41 using namespace llvm; 42 43 STATISTIC(NumEmitted, "Number of machine instructions emitted"); 44 45 namespace { 46 47 class ARMCodeEmitter : public MachineFunctionPass { 48 ARMJITInfo *JTI; 49 const ARMBaseInstrInfo *II; 50 const DataLayout *TD; 51 const ARMSubtarget *Subtarget; 52 TargetMachine &TM; 53 JITCodeEmitter &MCE; 54 MachineModuleInfo *MMI; 55 const std::vector<MachineConstantPoolEntry> *MCPEs; 56 const std::vector<MachineJumpTableEntry> *MJTEs; 57 bool IsPIC; 58 bool IsThumb; 59 60 void getAnalysisUsage(AnalysisUsage &AU) const { 61 AU.addRequired<MachineModuleInfo>(); 62 MachineFunctionPass::getAnalysisUsage(AU); 63 } 64 65 static char ID; 66 public: 67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 68 : MachineFunctionPass(ID), JTI(0), 69 II((const ARMBaseInstrInfo *)tm.getInstrInfo()), 70 TD(tm.getDataLayout()), TM(tm), 71 MCE(mce), MCPEs(0), MJTEs(0), 72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {} 73 74 /// getBinaryCodeForInstr - This function, generated by the 75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 76 /// machine instructions. 77 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; 78 79 bool runOnMachineFunction(MachineFunction &MF); 80 81 virtual const char *getPassName() const { 82 return "ARM Machine Code Emitter"; 83 } 84 85 void emitInstruction(const MachineInstr &MI); 86 87 private: 88 89 void emitWordLE(unsigned Binary); 90 void emitDWordLE(uint64_t Binary); 91 void emitConstantToMemory(unsigned CPI, const Constant *CV); 92 void emitConstPoolInstruction(const MachineInstr &MI); 93 void emitMOVi32immInstruction(const MachineInstr &MI); 94 void emitMOVi2piecesInstruction(const MachineInstr &MI); 95 void emitLEApcrelInstruction(const MachineInstr &MI); 96 void emitLEApcrelJTInstruction(const MachineInstr &MI); 97 void emitPseudoMoveInstruction(const MachineInstr &MI); 98 void addPCLabel(unsigned LabelID); 99 void emitPseudoInstruction(const MachineInstr &MI); 100 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 101 const MCInstrDesc &MCID, 102 const MachineOperand &MO, 103 unsigned OpIdx); 104 105 unsigned getMachineSoImmOpValue(unsigned SoImm); 106 unsigned getAddrModeSBit(const MachineInstr &MI, 107 const MCInstrDesc &MCID) const; 108 109 void emitDataProcessingInstruction(const MachineInstr &MI, 110 unsigned ImplicitRd = 0, 111 unsigned ImplicitRn = 0); 112 113 void emitLoadStoreInstruction(const MachineInstr &MI, 114 unsigned ImplicitRd = 0, 115 unsigned ImplicitRn = 0); 116 117 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 118 unsigned ImplicitRn = 0); 119 120 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 121 122 void emitMulFrmInstruction(const MachineInstr &MI); 123 124 void emitExtendInstruction(const MachineInstr &MI); 125 126 void emitMiscArithInstruction(const MachineInstr &MI); 127 128 void emitSaturateInstruction(const MachineInstr &MI); 129 130 void emitBranchInstruction(const MachineInstr &MI); 131 132 void emitInlineJumpTable(unsigned JTIndex); 133 134 void emitMiscBranchInstruction(const MachineInstr &MI); 135 136 void emitVFPArithInstruction(const MachineInstr &MI); 137 138 void emitVFPConversionInstruction(const MachineInstr &MI); 139 140 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 141 142 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 143 144 void emitMiscInstruction(const MachineInstr &MI); 145 146 void emitNEONLaneInstruction(const MachineInstr &MI); 147 void emitNEONDupInstruction(const MachineInstr &MI); 148 void emitNEON1RegModImmInstruction(const MachineInstr &MI); 149 void emitNEON2RegInstruction(const MachineInstr &MI); 150 void emitNEON3RegInstruction(const MachineInstr &MI); 151 152 /// getMachineOpValue - Return binary encoding of operand. If the machine 153 /// operand requires relocation, record the relocation and return zero. 154 unsigned getMachineOpValue(const MachineInstr &MI, 155 const MachineOperand &MO) const; 156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 157 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 158 } 159 160 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the 161 // TableGen'erated getBinaryCodeForInstr() function to encode any 162 // operand values, instead querying getMachineOpValue() directly for 163 // each operand it needs to encode. Thus, any of the new encoder 164 // helper functions can simply return 0 as the values the return 165 // are already handled elsewhere. They are placeholders to allow this 166 // encoder to continue to function until the MC encoder is sufficiently 167 // far along that this one can be eliminated entirely. 168 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) 169 const { return 0; } 170 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) 171 const { return 0; } 172 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val) 173 const { return 0; } 174 unsigned NEONThumb2V8PostEncoder(const MachineInstr &MI,unsigned Val) 175 const { return 0; } 176 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val) 177 const { 178 if (IsThumb) { 179 Val &= 0x0FFFFFFF; 180 Val |= 0xE0000000; 181 } 182 return Val; 183 } 184 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 185 const { return 0; } 186 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 187 const { return 0; } 188 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op) 189 const { return 0; } 190 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op) 191 const { return 0; } 192 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op) 193 const { return 0; } 194 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op) 195 const { return 0; } 196 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op) 197 const { return 0; } 198 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 199 const { return 0; } 200 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI, 201 unsigned Op) const { return 0; } 202 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 203 const { return 0; } 204 unsigned getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op) 205 const { return 0; } 206 unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op) 207 const { return 0; } 208 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) 209 const { return 0; } 210 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) 211 const { return 0; } 212 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op) 213 const { return 0; } 214 unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op) 215 const { return 0; } 216 unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op) 217 const { return 0; } 218 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op) 219 const { return 0; } 220 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 221 const { return 0; } 222 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op) 223 const { return 0; } 224 unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op) 225 const { return 0; } 226 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op) 227 const { return 0; } 228 unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op) 229 const { return 0; } 230 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op) 231 const { return 0; } 232 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op) 233 const { return 0; } 234 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op) 235 const { return 0; } 236 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) 237 const { return 0; } 238 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op) 239 const { return 0; } 240 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) 241 const { return 0; } 242 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI, 243 unsigned Op) 244 const { return 0; } 245 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op) 246 const { return 0; } 247 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) 248 const { return 0; } 249 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, 250 unsigned Op) const { return 0; } 251 unsigned getSsatBitPosValue(const MachineInstr &MI, 252 unsigned Op) const { return 0; } 253 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) 254 const {return 0; } 255 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) 256 const { return 0; } 257 258 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 259 const { 260 // {17-13} = reg 261 // {12} = (U)nsigned (add == '1', sub == '0') 262 // {11-0} = imm12 263 const MachineOperand &MO = MI.getOperand(Op); 264 const MachineOperand &MO1 = MI.getOperand(Op + 1); 265 if (!MO.isReg()) { 266 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 267 return 0; 268 } 269 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg()); 270 int32_t Imm12 = MO1.getImm(); 271 uint32_t Binary; 272 Binary = Imm12 & 0xfff; 273 if (Imm12 >= 0) 274 Binary |= (1 << 12); 275 Binary |= (Reg << 13); 276 return Binary; 277 } 278 279 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) 280 const { 281 const MCInstrDesc &MCID = MI.getDesc(); 282 const MachineOperand &MO = MI.getOperand(Op); 283 284 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ? 285 ARM::reloc_arm_movw : ARM::reloc_arm_movt); 286 287 if (!MO.isImm()) { 288 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 289 return 0; 290 } 291 unsigned Imm16 = static_cast<unsigned>(MO.getImm()); 292 return Imm16; 293 } 294 295 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) 296 const { return 0;} 297 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 298 const { return 0;} 299 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx) 300 const { return 0;} 301 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 302 const { return 0;} 303 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) 304 const { return 0; } 305 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op) 306 const { return 0; } 307 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op) 308 const { return 0; } 309 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op) 310 const { return 0; } 311 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op) 312 const { return 0; } 313 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { 314 // {12-9} = reg 315 // {8} = (U)nsigned (add == '1', sub == '0') 316 // {7-0} = imm8 317 uint32_t Binary = 0; 318 const MachineOperand &MO = MI.getOperand(Op); 319 const MachineOperand &MO1 = MI.getOperand(Op + 1); 320 if (!MO.isReg()) { 321 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 322 return 0; 323 } 324 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg()); 325 int32_t Imm12 = MO1.getImm(); 326 327 // Special value for #-0 328 if (Imm12 == INT32_MIN) 329 Imm12 = 0; 330 331 // Immediate is always encoded as positive. The 'U' bit controls add vs 332 // sub. 333 bool isAdd = true; 334 if (Imm12 < 0) { 335 Imm12 = -Imm12; 336 isAdd = false; 337 } 338 339 // If immediate offset is omitted, default to +0. 340 Binary |= 1 << 8; 341 return Binary; 342 } 343 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) 344 const { return 0; } 345 346 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) 347 const { return 0; } 348 349 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op) 350 const { return 0; } 351 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op) 352 const { return 0; } 353 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op) 354 const { return 0; } 355 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op) 356 const { return 0; } 357 358 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 359 /// machine operand requires relocation, record the relocation and return 360 /// zero. 361 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, 362 unsigned Reloc); 363 364 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 365 /// 366 unsigned getShiftOp(unsigned Imm) const ; 367 368 /// Routines that handle operands which add machine relocations which are 369 /// fixed up by the relocation stage. 370 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 371 bool MayNeedFarStub, bool Indirect, 372 intptr_t ACPV = 0) const; 373 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const; 374 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const; 375 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const; 376 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 377 intptr_t JTBase = 0) const; 378 unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const; 379 unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) const; 380 unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) const; 381 unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) const; 382 unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) const; 383 unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) const; 384 }; 385 } 386 387 char ARMCodeEmitter::ID = 0; 388 389 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 390 /// code to the specified MCE object. 391 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 392 JITCodeEmitter &JCE) { 393 return new ARMCodeEmitter(TM, JCE); 394 } 395 396 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 397 TargetMachine &Target = const_cast<TargetMachine&>(MF.getTarget()); 398 399 assert((Target.getRelocationModel() != Reloc::Default || 400 Target.getRelocationModel() != Reloc::Static) && 401 "JIT relocation model must be set to static or default!"); 402 403 JTI = static_cast<ARMJITInfo*>(Target.getJITInfo()); 404 II = static_cast<const ARMBaseInstrInfo*>(Target.getInstrInfo()); 405 TD = Target.getDataLayout(); 406 407 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 408 MCPEs = &MF.getConstantPool()->getConstants(); 409 MJTEs = 0; 410 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 411 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 412 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction(); 413 JTI->Initialize(MF, IsPIC); 414 MMI = &getAnalysis<MachineModuleInfo>(); 415 MCE.setModuleInfo(MMI); 416 417 do { 418 DEBUG(errs() << "JITTing function '" 419 << MF.getName() << "'\n"); 420 MCE.startFunction(MF); 421 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 422 MBB != E; ++MBB) { 423 MCE.StartMachineBasicBlock(MBB); 424 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 425 I != E; ++I) 426 emitInstruction(*I); 427 } 428 } while (MCE.finishFunction(MF)); 429 430 return false; 431 } 432 433 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 434 /// 435 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 436 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 437 default: llvm_unreachable("Unknown shift opc!"); 438 case ARM_AM::asr: return 2; 439 case ARM_AM::lsl: return 0; 440 case ARM_AM::lsr: return 1; 441 case ARM_AM::ror: 442 case ARM_AM::rrx: return 3; 443 } 444 } 445 446 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 447 /// machine operand requires relocation, record the relocation and return zero. 448 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, 449 const MachineOperand &MO, 450 unsigned Reloc) { 451 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) 452 && "Relocation to this function should be for movt or movw"); 453 454 if (MO.isImm()) 455 return static_cast<unsigned>(MO.getImm()); 456 else if (MO.isGlobal()) 457 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 458 else if (MO.isSymbol()) 459 emitExternalSymbolAddress(MO.getSymbolName(), Reloc); 460 else if (MO.isMBB()) 461 emitMachineBasicBlock(MO.getMBB(), Reloc); 462 else { 463 #ifndef NDEBUG 464 errs() << MO; 465 #endif 466 llvm_unreachable("Unsupported operand type for movw/movt"); 467 } 468 return 0; 469 } 470 471 /// getMachineOpValue - Return binary encoding of operand. If the machine 472 /// operand requires relocation, record the relocation and return zero. 473 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 474 const MachineOperand &MO) const { 475 if (MO.isReg()) 476 return II->getRegisterInfo().getEncodingValue(MO.getReg()); 477 else if (MO.isImm()) 478 return static_cast<unsigned>(MO.getImm()); 479 else if (MO.isFPImm()) 480 return static_cast<unsigned>(MO.getFPImm()->getValueAPF() 481 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 482 else if (MO.isGlobal()) 483 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 484 else if (MO.isSymbol()) 485 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 486 else if (MO.isCPI()) { 487 const MCInstrDesc &MCID = MI.getDesc(); 488 // For VFP load, the immediate offset is multiplied by 4. 489 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 490 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 491 emitConstPoolAddress(MO.getIndex(), Reloc); 492 } else if (MO.isJTI()) 493 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 494 else if (MO.isMBB()) 495 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 496 else 497 llvm_unreachable("Unable to encode MachineOperand!"); 498 return 0; 499 } 500 501 /// emitGlobalAddress - Emit the specified address to the code stream. 502 /// 503 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 504 bool MayNeedFarStub, bool Indirect, 505 intptr_t ACPV) const { 506 MachineRelocation MR = Indirect 507 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 508 const_cast<GlobalValue *>(GV), 509 ACPV, MayNeedFarStub) 510 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 511 const_cast<GlobalValue *>(GV), ACPV, 512 MayNeedFarStub); 513 MCE.addRelocation(MR); 514 } 515 516 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to 517 /// be emitted to the current location in the function, and allow it to be PC 518 /// relative. 519 void ARMCodeEmitter:: 520 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { 521 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 522 Reloc, ES)); 523 } 524 525 /// emitConstPoolAddress - Arrange for the address of an constant pool 526 /// to be emitted to the current location in the function, and allow it to be PC 527 /// relative. 528 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const { 529 // Tell JIT emitter we'll resolve the address. 530 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 531 Reloc, CPI, 0, true)); 532 } 533 534 /// emitJumpTableAddress - Arrange for the address of a jump table to 535 /// be emitted to the current location in the function, and allow it to be PC 536 /// relative. 537 void ARMCodeEmitter:: 538 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const { 539 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 540 Reloc, JTIndex, 0, true)); 541 } 542 543 /// emitMachineBasicBlock - Emit the specified address basic block. 544 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, 545 unsigned Reloc, 546 intptr_t JTBase) const { 547 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 548 Reloc, BB, JTBase)); 549 } 550 551 void ARMCodeEmitter::emitWordLE(unsigned Binary) { 552 DEBUG(errs() << " 0x"; 553 errs().write_hex(Binary) << "\n"); 554 MCE.emitWordLE(Binary); 555 } 556 557 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { 558 DEBUG(errs() << " 0x"; 559 errs().write_hex(Binary) << "\n"); 560 MCE.emitDWordLE(Binary); 561 } 562 563 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { 564 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 565 566 MCE.processDebugLoc(MI.getDebugLoc(), true); 567 568 ++NumEmitted; // Keep track of the # of mi's emitted 569 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 570 default: { 571 llvm_unreachable("Unhandled instruction encoding format!"); 572 } 573 case ARMII::MiscFrm: 574 if (MI.getOpcode() == ARM::LEApcrelJT) { 575 // Materialize jumptable address. 576 emitLEApcrelJTInstruction(MI); 577 break; 578 } 579 llvm_unreachable("Unhandled instruction encoding!"); 580 case ARMII::Pseudo: 581 emitPseudoInstruction(MI); 582 break; 583 case ARMII::DPFrm: 584 case ARMII::DPSoRegFrm: 585 emitDataProcessingInstruction(MI); 586 break; 587 case ARMII::LdFrm: 588 case ARMII::StFrm: 589 emitLoadStoreInstruction(MI); 590 break; 591 case ARMII::LdMiscFrm: 592 case ARMII::StMiscFrm: 593 emitMiscLoadStoreInstruction(MI); 594 break; 595 case ARMII::LdStMulFrm: 596 emitLoadStoreMultipleInstruction(MI); 597 break; 598 case ARMII::MulFrm: 599 emitMulFrmInstruction(MI); 600 break; 601 case ARMII::ExtFrm: 602 emitExtendInstruction(MI); 603 break; 604 case ARMII::ArithMiscFrm: 605 emitMiscArithInstruction(MI); 606 break; 607 case ARMII::SatFrm: 608 emitSaturateInstruction(MI); 609 break; 610 case ARMII::BrFrm: 611 emitBranchInstruction(MI); 612 break; 613 case ARMII::BrMiscFrm: 614 emitMiscBranchInstruction(MI); 615 break; 616 // VFP instructions. 617 case ARMII::VFPUnaryFrm: 618 case ARMII::VFPBinaryFrm: 619 emitVFPArithInstruction(MI); 620 break; 621 case ARMII::VFPConv1Frm: 622 case ARMII::VFPConv2Frm: 623 case ARMII::VFPConv3Frm: 624 case ARMII::VFPConv4Frm: 625 case ARMII::VFPConv5Frm: 626 emitVFPConversionInstruction(MI); 627 break; 628 case ARMII::VFPLdStFrm: 629 emitVFPLoadStoreInstruction(MI); 630 break; 631 case ARMII::VFPLdStMulFrm: 632 emitVFPLoadStoreMultipleInstruction(MI); 633 break; 634 case ARMII::VFPMiscFrm: 635 emitMiscInstruction(MI); 636 break; 637 // NEON instructions. 638 case ARMII::NGetLnFrm: 639 case ARMII::NSetLnFrm: 640 emitNEONLaneInstruction(MI); 641 break; 642 case ARMII::NDupFrm: 643 emitNEONDupInstruction(MI); 644 break; 645 case ARMII::N1RegModImmFrm: 646 emitNEON1RegModImmInstruction(MI); 647 break; 648 case ARMII::N2RegFrm: 649 emitNEON2RegInstruction(MI); 650 break; 651 case ARMII::N3RegFrm: 652 emitNEON3RegInstruction(MI); 653 break; 654 } 655 MCE.processDebugLoc(MI.getDebugLoc(), false); 656 } 657 658 void ARMCodeEmitter::emitConstantToMemory(unsigned CPI, const Constant *C) { 659 DEBUG({ 660 errs() << " ** Constant pool #" << CPI << " @ " 661 << (void*)MCE.getCurrentPCValue() << " "; 662 if (const Function *F = dyn_cast<Function>(C)) 663 errs() << F->getName(); 664 else 665 errs() << *C; 666 errs() << '\n'; 667 }); 668 669 switch (C->getValueID()) { 670 default: { 671 llvm_unreachable("Unable to handle this constantpool entry!"); 672 break; 673 } 674 case Value::GlobalVariableVal: { 675 emitGlobalAddress(static_cast<const GlobalValue*>(C), 676 ARM::reloc_arm_absolute, isa<Function>(C), false); 677 emitWordLE(0); 678 break; 679 } 680 case Value::ConstantIntVal: { 681 const ConstantInt *CI = static_cast<const ConstantInt*>(C); 682 uint32_t Val = *(uint32_t*)CI->getValue().getRawData(); 683 emitWordLE(Val); 684 break; 685 } 686 case Value::ConstantFPVal: { 687 const ConstantFP *CFP = static_cast<const ConstantFP*>(C); 688 if (CFP->getType()->isFloatTy()) 689 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 690 else if (CFP->getType()->isDoubleTy()) 691 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 692 else { 693 llvm_unreachable("Unable to handle this constantpool entry!"); 694 } 695 break; 696 } 697 case Value::ConstantArrayVal: { 698 const ConstantArray *CA = static_cast<const ConstantArray*>(C); 699 for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i) 700 emitConstantToMemory(CPI, CA->getOperand(i)); 701 break; 702 } 703 } 704 705 return; 706 } 707 708 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { 709 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 710 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 711 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 712 713 // Remember the CONSTPOOL_ENTRY address for later relocation. 714 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 715 716 // Emit constpool island entry. In most cases, the actual values will be 717 // resolved and relocated after code emission. 718 if (MCPE.isMachineConstantPoolEntry()) { 719 ARMConstantPoolValue *ACPV = 720 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 721 722 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 723 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 724 725 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 726 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV(); 727 if (GV) { 728 Reloc::Model RelocM = TM.getRelocationModel(); 729 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 730 isa<Function>(GV), 731 Subtarget->GVIsIndirectSymbol(GV, RelocM), 732 (intptr_t)ACPV); 733 } else { 734 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(); 735 emitExternalSymbolAddress(Sym, ARM::reloc_arm_absolute); 736 } 737 emitWordLE(0); 738 } else { 739 emitConstantToMemory(CPI, MCPE.Val.ConstVal); 740 } 741 } 742 743 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) { 744 const MachineOperand &MO0 = MI.getOperand(0); 745 const MachineOperand &MO1 = MI.getOperand(1); 746 747 // Emit the 'movw' instruction. 748 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000 749 750 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF; 751 752 // Set the conditional execution predicate. 753 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 754 755 // Encode Rd. 756 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 757 758 // Encode imm16 as imm4:imm12 759 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12 760 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4 761 emitWordLE(Binary); 762 763 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16; 764 // Emit the 'movt' instruction. 765 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100 766 767 // Set the conditional execution predicate. 768 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 769 770 // Encode Rd. 771 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 772 773 // Encode imm16 as imm4:imm1, same as movw above. 774 Binary |= Hi16 & 0xFFF; 775 Binary |= ((Hi16 >> 12) & 0xF) << 16; 776 emitWordLE(Binary); 777 } 778 779 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { 780 const MachineOperand &MO0 = MI.getOperand(0); 781 const MachineOperand &MO1 = MI.getOperand(1); 782 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 783 "Not a valid so_imm value!"); 784 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 785 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 786 787 // Emit the 'mov' instruction. 788 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 789 790 // Set the conditional execution predicate. 791 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 792 793 // Encode Rd. 794 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 795 796 // Encode so_imm. 797 // Set bit I(25) to identify this is the immediate form of <shifter_op> 798 Binary |= 1 << ARMII::I_BitShift; 799 Binary |= getMachineSoImmOpValue(V1); 800 emitWordLE(Binary); 801 802 // Now the 'orr' instruction. 803 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 804 805 // Set the conditional execution predicate. 806 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 807 808 // Encode Rd. 809 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 810 811 // Encode Rn. 812 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 813 814 // Encode so_imm. 815 // Set bit I(25) to identify this is the immediate form of <shifter_op> 816 Binary |= 1 << ARMII::I_BitShift; 817 Binary |= getMachineSoImmOpValue(V2); 818 emitWordLE(Binary); 819 } 820 821 void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) { 822 // It's basically add r, pc, (LCPI - $+8) 823 const MCInstrDesc &MCID = MI.getDesc(); 824 825 unsigned Binary = 0; 826 827 // Set the conditional execution predicate 828 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 829 830 // Encode S bit if MI modifies CPSR. 831 Binary |= getAddrModeSBit(MI, MCID); 832 833 // Encode Rd. 834 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 835 836 // Encode Rn which is PC. 837 Binary |= II->getRegisterInfo().getEncodingValue(ARM::PC) << ARMII::RegRnShift; 838 839 // Encode the displacement which is a so_imm. 840 // Set bit I(25) to identify this is the immediate form of <shifter_op> 841 Binary |= 1 << ARMII::I_BitShift; 842 emitConstPoolAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_so_imm_cp_entry); 843 844 emitWordLE(Binary); 845 } 846 847 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { 848 // It's basically add r, pc, (LJTI - $+8) 849 850 const MCInstrDesc &MCID = MI.getDesc(); 851 852 // Emit the 'add' instruction. 853 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100 854 855 // Set the conditional execution predicate 856 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 857 858 // Encode S bit if MI modifies CPSR. 859 Binary |= getAddrModeSBit(MI, MCID); 860 861 // Encode Rd. 862 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 863 864 // Encode Rn which is PC. 865 Binary |= II->getRegisterInfo().getEncodingValue(ARM::PC) << ARMII::RegRnShift; 866 867 // Encode the displacement. 868 Binary |= 1 << ARMII::I_BitShift; 869 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 870 871 emitWordLE(Binary); 872 } 873 874 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { 875 unsigned Opcode = MI.getDesc().Opcode; 876 877 // Part of binary is determined by TableGn. 878 unsigned Binary = getBinaryCodeForInstr(MI); 879 880 // Set the conditional execution predicate 881 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 882 883 // Encode S bit if MI modifies CPSR. 884 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 885 Binary |= 1 << ARMII::S_BitShift; 886 887 // Encode register def if there is one. 888 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 889 890 // Encode the shift operation. 891 switch (Opcode) { 892 default: break; 893 case ARM::RRX: 894 // rrx 895 Binary |= 0x6 << 4; 896 break; 897 case ARM::MOVsrl_flag: 898 // lsr #1 899 Binary |= (0x2 << 4) | (1 << 7); 900 break; 901 case ARM::MOVsra_flag: 902 // asr #1 903 Binary |= (0x4 << 4) | (1 << 7); 904 break; 905 } 906 907 // Encode register Rm. 908 Binary |= getMachineOpValue(MI, 1); 909 910 emitWordLE(Binary); 911 } 912 913 void ARMCodeEmitter::addPCLabel(unsigned LabelID) { 914 DEBUG(errs() << " ** LPC" << LabelID << " @ " 915 << (void*)MCE.getCurrentPCValue() << '\n'); 916 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 917 } 918 919 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { 920 unsigned Opcode = MI.getDesc().Opcode; 921 switch (Opcode) { 922 default: 923 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 924 case ARM::B: 925 emitBranchInstruction(MI); 926 break; 927 case ARM::BR_JTr: 928 case ARM::BR_JTm: 929 case ARM::BR_JTadd: 930 emitMiscBranchInstruction(MI); 931 break; 932 case ARM::BX_CALL: 933 case ARM::BMOVPCRX_CALL: { 934 // First emit mov lr, pc 935 unsigned Binary = 0x01a0e00f; 936 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 937 emitWordLE(Binary); 938 939 // and then emit the branch. 940 emitMiscBranchInstruction(MI); 941 break; 942 } 943 case TargetOpcode::INLINEASM: { 944 // We allow inline assembler nodes with empty bodies - they can 945 // implicitly define registers, which is ok for JIT. 946 if (MI.getOperand(0).getSymbolName()[0]) { 947 report_fatal_error("JIT does not support inline asm!"); 948 } 949 break; 950 } 951 case TargetOpcode::PROLOG_LABEL: 952 case TargetOpcode::EH_LABEL: 953 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 954 break; 955 case TargetOpcode::IMPLICIT_DEF: 956 case TargetOpcode::KILL: 957 // Do nothing. 958 break; 959 case ARM::CONSTPOOL_ENTRY: 960 emitConstPoolInstruction(MI); 961 break; 962 case ARM::LDMIA_RET: 963 emitLoadStoreMultipleInstruction(MI); 964 break; 965 case ARM::PICADD: { 966 // Remember of the address of the PC label for relocation later. 967 addPCLabel(MI.getOperand(2).getImm()); 968 // PICADD is just an add instruction that implicitly read pc. 969 emitDataProcessingInstruction(MI, 0, ARM::PC); 970 break; 971 } 972 case ARM::PICLDR: 973 case ARM::PICLDRB: 974 case ARM::PICSTR: 975 case ARM::PICSTRB: { 976 // Remember of the address of the PC label for relocation later. 977 addPCLabel(MI.getOperand(2).getImm()); 978 // These are just load / store instructions that implicitly read pc. 979 emitLoadStoreInstruction(MI, 0, ARM::PC); 980 break; 981 } 982 case ARM::PICLDRH: 983 case ARM::PICLDRSH: 984 case ARM::PICLDRSB: 985 case ARM::PICSTRH: { 986 // Remember of the address of the PC label for relocation later. 987 addPCLabel(MI.getOperand(2).getImm()); 988 // These are just load / store instructions that implicitly read pc. 989 emitMiscLoadStoreInstruction(MI, ARM::PC); 990 break; 991 } 992 993 case ARM::MOVi32imm: 994 // Two instructions to materialize a constant. 995 if (Subtarget->hasV6T2Ops()) 996 emitMOVi32immInstruction(MI); 997 else 998 emitMOVi2piecesInstruction(MI); 999 break; 1000 case ARM::LEApcrel: 1001 // Materialize constantpool index address. 1002 emitLEApcrelInstruction(MI); 1003 break; 1004 case ARM::LEApcrelJT: 1005 // Materialize jumptable address. 1006 emitLEApcrelJTInstruction(MI); 1007 break; 1008 case ARM::RRX: 1009 case ARM::MOVsrl_flag: 1010 case ARM::MOVsra_flag: 1011 emitPseudoMoveInstruction(MI); 1012 break; 1013 } 1014 } 1015 1016 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, 1017 const MCInstrDesc &MCID, 1018 const MachineOperand &MO, 1019 unsigned OpIdx) { 1020 unsigned Binary = getMachineOpValue(MI, MO); 1021 1022 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 1023 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 1024 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 1025 1026 // Encode the shift opcode. 1027 unsigned SBits = 0; 1028 unsigned Rs = MO1.getReg(); 1029 if (Rs) { 1030 // Set shift operand (bit[7:4]). 1031 // LSL - 0001 1032 // LSR - 0011 1033 // ASR - 0101 1034 // ROR - 0111 1035 // RRX - 0110 and bit[11:8] clear. 1036 switch (SOpc) { 1037 default: llvm_unreachable("Unknown shift opc!"); 1038 case ARM_AM::lsl: SBits = 0x1; break; 1039 case ARM_AM::lsr: SBits = 0x3; break; 1040 case ARM_AM::asr: SBits = 0x5; break; 1041 case ARM_AM::ror: SBits = 0x7; break; 1042 case ARM_AM::rrx: SBits = 0x6; break; 1043 } 1044 } else { 1045 // Set shift operand (bit[6:4]). 1046 // LSL - 000 1047 // LSR - 010 1048 // ASR - 100 1049 // ROR - 110 1050 switch (SOpc) { 1051 default: llvm_unreachable("Unknown shift opc!"); 1052 case ARM_AM::lsl: SBits = 0x0; break; 1053 case ARM_AM::lsr: SBits = 0x2; break; 1054 case ARM_AM::asr: SBits = 0x4; break; 1055 case ARM_AM::ror: SBits = 0x6; break; 1056 } 1057 } 1058 Binary |= SBits << 4; 1059 if (SOpc == ARM_AM::rrx) 1060 return Binary; 1061 1062 // Encode the shift operation Rs or shift_imm (except rrx). 1063 if (Rs) { 1064 // Encode Rs bit[11:8]. 1065 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 1066 return Binary | (II->getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift); 1067 } 1068 1069 // Encode shift_imm bit[11:7]. 1070 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 1071 } 1072 1073 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { 1074 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 1075 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 1076 1077 // Encode rotate_imm. 1078 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 1079 << ARMII::SoRotImmShift; 1080 1081 // Encode immed_8. 1082 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 1083 return Binary; 1084 } 1085 1086 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, 1087 const MCInstrDesc &MCID) const { 1088 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){ 1089 const MachineOperand &MO = MI.getOperand(i-1); 1090 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 1091 return 1 << ARMII::S_BitShift; 1092 } 1093 return 0; 1094 } 1095 1096 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, 1097 unsigned ImplicitRd, 1098 unsigned ImplicitRn) { 1099 const MCInstrDesc &MCID = MI.getDesc(); 1100 1101 // Part of binary is determined by TableGn. 1102 unsigned Binary = getBinaryCodeForInstr(MI); 1103 1104 if (MCID.Opcode == ARM::MOVi16 || MCID.Opcode == ARM::MOVTi16) { 1105 emitWordLE(Binary); 1106 return; 1107 } 1108 1109 // Set the conditional execution predicate 1110 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1111 1112 // Encode S bit if MI modifies CPSR. 1113 Binary |= getAddrModeSBit(MI, MCID); 1114 1115 // Encode register def if there is one. 1116 unsigned NumDefs = MCID.getNumDefs(); 1117 unsigned OpIdx = 0; 1118 if (NumDefs) 1119 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1120 else if (ImplicitRd) 1121 // Special handling for implicit use (e.g. PC). 1122 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift); 1123 1124 if (MCID.Opcode == ARM::MOVi16) { 1125 // Get immediate from MI. 1126 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), 1127 ARM::reloc_arm_movw); 1128 // Encode imm which is the same as in emitMOVi32immInstruction(). 1129 Binary |= Lo16 & 0xFFF; 1130 Binary |= ((Lo16 >> 12) & 0xF) << 16; 1131 emitWordLE(Binary); 1132 return; 1133 } else if(MCID.Opcode == ARM::MOVTi16) { 1134 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), 1135 ARM::reloc_arm_movt) >> 16); 1136 Binary |= Hi16 & 0xFFF; 1137 Binary |= ((Hi16 >> 12) & 0xF) << 16; 1138 emitWordLE(Binary); 1139 return; 1140 } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) { 1141 uint32_t v = ~MI.getOperand(2).getImm(); 1142 int32_t lsb = countTrailingZeros(v); 1143 int32_t msb = (32 - countLeadingZeros(v)) - 1; 1144 // Instr{20-16} = msb, Instr{11-7} = lsb 1145 Binary |= (msb & 0x1F) << 16; 1146 Binary |= (lsb & 0x1F) << 7; 1147 emitWordLE(Binary); 1148 return; 1149 } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) { 1150 // Encode Rn in Instr{0-3} 1151 Binary |= getMachineOpValue(MI, OpIdx++); 1152 1153 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); 1154 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; 1155 1156 // Instr{20-16} = widthm1, Instr{11-7} = lsb 1157 Binary |= (widthm1 & 0x1F) << 16; 1158 Binary |= (lsb & 0x1F) << 7; 1159 emitWordLE(Binary); 1160 return; 1161 } 1162 1163 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 1164 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1165 ++OpIdx; 1166 1167 // Encode first non-shifter register operand if there is one. 1168 bool isUnary = MCID.TSFlags & ARMII::UnaryDP; 1169 if (!isUnary) { 1170 if (ImplicitRn) 1171 // Special handling for implicit use (e.g. PC). 1172 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift); 1173 else { 1174 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 1175 ++OpIdx; 1176 } 1177 } 1178 1179 // Encode shifter operand. 1180 const MachineOperand &MO = MI.getOperand(OpIdx); 1181 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 1182 // Encode SoReg. 1183 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx)); 1184 return; 1185 } 1186 1187 if (MO.isReg()) { 1188 // Encode register Rm. 1189 emitWordLE(Binary | II->getRegisterInfo().getEncodingValue(MO.getReg())); 1190 return; 1191 } 1192 1193 // Encode so_imm. 1194 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 1195 1196 emitWordLE(Binary); 1197 } 1198 1199 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, 1200 unsigned ImplicitRd, 1201 unsigned ImplicitRn) { 1202 const MCInstrDesc &MCID = MI.getDesc(); 1203 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1204 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1205 1206 // Part of binary is determined by TableGn. 1207 unsigned Binary = getBinaryCodeForInstr(MI); 1208 1209 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done. 1210 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp || 1211 MI.getOpcode() == ARM::STRi12 || MI.getOpcode() == ARM::LDRBi12 || 1212 MI.getOpcode() == ARM::STRBi12) { 1213 emitWordLE(Binary); 1214 return; 1215 } 1216 1217 if (MI.getOpcode() == ARM::BR_JTm) 1218 Binary = 0x710F000; 1219 else if (MI.getOpcode() == ARM::BR_JTr) 1220 Binary = 0x1A0F000; 1221 1222 // Set the conditional execution predicate 1223 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1224 1225 unsigned OpIdx = 0; 1226 1227 // Operand 0 of a pre- and post-indexed store is the address base 1228 // writeback. Skip it. 1229 bool Skipped = false; 1230 if (IsPrePost && Form == ARMII::StFrm) { 1231 ++OpIdx; 1232 Skipped = true; 1233 } 1234 1235 // Set first operand 1236 if (ImplicitRd) 1237 // Special handling for implicit use (e.g. PC). 1238 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift); 1239 else 1240 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1241 1242 // Set second operand 1243 if (ImplicitRn) 1244 // Special handling for implicit use (e.g. PC). 1245 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift); 1246 else 1247 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1248 1249 // If this is a two-address operand, skip it. e.g. LDR_PRE. 1250 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1251 ++OpIdx; 1252 1253 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1254 unsigned AM2Opc = (ImplicitRn == ARM::PC) 1255 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1256 1257 // Set bit U(23) according to sign of immed value (positive or negative). 1258 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 1259 ARMII::U_BitShift); 1260 if (!MO2.getReg()) { // is immediate 1261 if (ARM_AM::getAM2Offset(AM2Opc)) 1262 // Set the value of offset_12 field 1263 Binary |= ARM_AM::getAM2Offset(AM2Opc); 1264 emitWordLE(Binary); 1265 return; 1266 } 1267 1268 // Set bit I(25), because this is not in immediate encoding. 1269 Binary |= 1 << ARMII::I_BitShift; 1270 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 1271 // Set bit[3:0] to the corresponding Rm register 1272 Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg()); 1273 1274 // If this instr is in scaled register offset/index instruction, set 1275 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 1276 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 1277 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 1278 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 1279 } 1280 1281 emitWordLE(Binary); 1282 } 1283 1284 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, 1285 unsigned ImplicitRn) { 1286 const MCInstrDesc &MCID = MI.getDesc(); 1287 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1288 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1289 1290 // Part of binary is determined by TableGn. 1291 unsigned Binary = getBinaryCodeForInstr(MI); 1292 1293 // Set the conditional execution predicate 1294 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1295 1296 unsigned OpIdx = 0; 1297 1298 // Operand 0 of a pre- and post-indexed store is the address base 1299 // writeback. Skip it. 1300 bool Skipped = false; 1301 if (IsPrePost && Form == ARMII::StMiscFrm) { 1302 ++OpIdx; 1303 Skipped = true; 1304 } 1305 1306 // Set first operand 1307 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1308 1309 // Skip LDRD and STRD's second operand. 1310 if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD) 1311 ++OpIdx; 1312 1313 // Set second operand 1314 if (ImplicitRn) 1315 // Special handling for implicit use (e.g. PC). 1316 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift); 1317 else 1318 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1319 1320 // If this is a two-address operand, skip it. e.g. LDRH_POST. 1321 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1322 ++OpIdx; 1323 1324 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1325 unsigned AM3Opc = (ImplicitRn == ARM::PC) 1326 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1327 1328 // Set bit U(23) according to sign of immed value (positive or negative) 1329 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 1330 ARMII::U_BitShift); 1331 1332 // If this instr is in register offset/index encoding, set bit[3:0] 1333 // to the corresponding Rm register. 1334 if (MO2.getReg()) { 1335 Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg()); 1336 emitWordLE(Binary); 1337 return; 1338 } 1339 1340 // This instr is in immediate offset/index encoding, set bit 22 to 1. 1341 Binary |= 1 << ARMII::AM3_I_BitShift; 1342 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 1343 // Set operands 1344 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 1345 Binary |= (ImmOffs & 0xF); // immedL 1346 } 1347 1348 emitWordLE(Binary); 1349 } 1350 1351 static unsigned getAddrModeUPBits(unsigned Mode) { 1352 unsigned Binary = 0; 1353 1354 // Set addressing mode by modifying bits U(23) and P(24) 1355 // IA - Increment after - bit U = 1 and bit P = 0 1356 // IB - Increment before - bit U = 1 and bit P = 1 1357 // DA - Decrement after - bit U = 0 and bit P = 0 1358 // DB - Decrement before - bit U = 0 and bit P = 1 1359 switch (Mode) { 1360 default: llvm_unreachable("Unknown addressing sub-mode!"); 1361 case ARM_AM::da: break; 1362 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 1363 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 1364 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 1365 } 1366 1367 return Binary; 1368 } 1369 1370 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { 1371 const MCInstrDesc &MCID = MI.getDesc(); 1372 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1373 1374 // Part of binary is determined by TableGn. 1375 unsigned Binary = getBinaryCodeForInstr(MI); 1376 1377 if (MCID.getOpcode() == ARM::LDMIA_RET) { 1378 IsUpdating = true; 1379 Binary |= 0x8B00000; 1380 } 1381 1382 // Set the conditional execution predicate 1383 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1384 1385 // Skip operand 0 of an instruction with base register update. 1386 unsigned OpIdx = 0; 1387 if (IsUpdating) 1388 ++OpIdx; 1389 1390 // Set base address operand 1391 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1392 1393 // Set addressing mode by modifying bits U(23) and P(24) 1394 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1395 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1396 1397 // Set bit W(21) 1398 if (IsUpdating) 1399 Binary |= 0x1 << ARMII::W_BitShift; 1400 1401 // Set registers 1402 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { 1403 const MachineOperand &MO = MI.getOperand(i); 1404 if (!MO.isReg() || MO.isImplicit()) 1405 break; 1406 unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg()); 1407 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 1408 RegNum < 16); 1409 Binary |= 0x1 << RegNum; 1410 } 1411 1412 emitWordLE(Binary); 1413 } 1414 1415 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { 1416 const MCInstrDesc &MCID = MI.getDesc(); 1417 1418 // Part of binary is determined by TableGn. 1419 unsigned Binary = getBinaryCodeForInstr(MI); 1420 1421 // Set the conditional execution predicate 1422 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1423 1424 // Encode S bit if MI modifies CPSR. 1425 Binary |= getAddrModeSBit(MI, MCID); 1426 1427 // 32x32->64bit operations have two destination registers. The number 1428 // of register definitions will tell us if that's what we're dealing with. 1429 unsigned OpIdx = 0; 1430 if (MCID.getNumDefs() == 2) 1431 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1432 1433 // Encode Rd 1434 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1435 1436 // Encode Rm 1437 Binary |= getMachineOpValue(MI, OpIdx++); 1438 1439 // Encode Rs 1440 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1441 1442 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1443 // it as Rn (for multiply, that's in the same offset as RdLo. 1444 if (MCID.getNumOperands() > OpIdx && 1445 !MCID.OpInfo[OpIdx].isPredicate() && 1446 !MCID.OpInfo[OpIdx].isOptionalDef()) 1447 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1448 1449 emitWordLE(Binary); 1450 } 1451 1452 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { 1453 const MCInstrDesc &MCID = MI.getDesc(); 1454 1455 // Part of binary is determined by TableGn. 1456 unsigned Binary = getBinaryCodeForInstr(MI); 1457 1458 // Set the conditional execution predicate 1459 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1460 1461 unsigned OpIdx = 0; 1462 1463 // Encode Rd 1464 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1465 1466 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1467 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1468 if (MO2.isReg()) { 1469 // Two register operand form. 1470 // Encode Rn. 1471 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1472 1473 // Encode Rm. 1474 Binary |= getMachineOpValue(MI, MO2); 1475 ++OpIdx; 1476 } else { 1477 Binary |= getMachineOpValue(MI, MO1); 1478 } 1479 1480 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1481 if (MI.getOperand(OpIdx).isImm() && 1482 !MCID.OpInfo[OpIdx].isPredicate() && 1483 !MCID.OpInfo[OpIdx].isOptionalDef()) 1484 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1485 1486 emitWordLE(Binary); 1487 } 1488 1489 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { 1490 const MCInstrDesc &MCID = MI.getDesc(); 1491 1492 // Part of binary is determined by TableGn. 1493 unsigned Binary = getBinaryCodeForInstr(MI); 1494 1495 // Set the conditional execution predicate 1496 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1497 1498 // PKH instructions are finished at this point 1499 if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) { 1500 emitWordLE(Binary); 1501 return; 1502 } 1503 1504 unsigned OpIdx = 0; 1505 1506 // Encode Rd 1507 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1508 1509 const MachineOperand &MO = MI.getOperand(OpIdx++); 1510 if (OpIdx == MCID.getNumOperands() || 1511 MCID.OpInfo[OpIdx].isPredicate() || 1512 MCID.OpInfo[OpIdx].isOptionalDef()) { 1513 // Encode Rm and it's done. 1514 Binary |= getMachineOpValue(MI, MO); 1515 emitWordLE(Binary); 1516 return; 1517 } 1518 1519 // Encode Rn. 1520 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1521 1522 // Encode Rm. 1523 Binary |= getMachineOpValue(MI, OpIdx++); 1524 1525 // Encode shift_imm. 1526 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1527 if (MCID.Opcode == ARM::PKHTB) { 1528 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); 1529 if (ShiftAmt == 32) 1530 ShiftAmt = 0; 1531 } 1532 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1533 Binary |= ShiftAmt << ARMII::ShiftShift; 1534 1535 emitWordLE(Binary); 1536 } 1537 1538 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { 1539 const MCInstrDesc &MCID = MI.getDesc(); 1540 1541 // Part of binary is determined by TableGen. 1542 unsigned Binary = getBinaryCodeForInstr(MI); 1543 1544 // Set the conditional execution predicate 1545 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1546 1547 // Encode Rd 1548 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 1549 1550 // Encode saturate bit position. 1551 unsigned Pos = MI.getOperand(1).getImm(); 1552 if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16) 1553 Pos -= 1; 1554 assert((Pos < 16 || (Pos < 32 && 1555 MCID.Opcode != ARM::SSAT16 && 1556 MCID.Opcode != ARM::USAT16)) && 1557 "saturate bit position out of range"); 1558 Binary |= Pos << 16; 1559 1560 // Encode Rm 1561 Binary |= getMachineOpValue(MI, 2); 1562 1563 // Encode shift_imm. 1564 if (MCID.getNumOperands() == 4) { 1565 unsigned ShiftOp = MI.getOperand(3).getImm(); 1566 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); 1567 if (Opc == ARM_AM::asr) 1568 Binary |= (1 << 6); 1569 unsigned ShiftAmt = MI.getOperand(3).getImm(); 1570 if (ShiftAmt == 32 && Opc == ARM_AM::asr) 1571 ShiftAmt = 0; 1572 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1573 Binary |= ShiftAmt << ARMII::ShiftShift; 1574 } 1575 1576 emitWordLE(Binary); 1577 } 1578 1579 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { 1580 const MCInstrDesc &MCID = MI.getDesc(); 1581 1582 if (MCID.Opcode == ARM::TPsoft) { 1583 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1584 } 1585 1586 // Part of binary is determined by TableGn. 1587 unsigned Binary = getBinaryCodeForInstr(MI); 1588 1589 if (MCID.Opcode == ARM::B) { 1590 Binary = 0xEA000000; 1591 } 1592 1593 // Set the conditional execution predicate 1594 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1595 1596 // Set signed_immed_24 field 1597 Binary |= getMachineOpValue(MI, 0); 1598 1599 emitWordLE(Binary); 1600 } 1601 1602 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { 1603 // Remember the base address of the inline jump table. 1604 uintptr_t JTBase = MCE.getCurrentPCValue(); 1605 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1606 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1607 << '\n'); 1608 1609 // Now emit the jump table entries. 1610 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1611 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1612 if (IsPIC) 1613 // DestBB address - JT base. 1614 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1615 else 1616 // Absolute DestBB address. 1617 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1618 emitWordLE(0); 1619 } 1620 } 1621 1622 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { 1623 const MCInstrDesc &MCID = MI.getDesc(); 1624 1625 // Handle jump tables. 1626 if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) { 1627 // First emit a ldr pc, [] instruction. 1628 emitDataProcessingInstruction(MI, ARM::PC); 1629 1630 // Then emit the inline jump table. 1631 unsigned JTIndex = 1632 (MCID.Opcode == ARM::BR_JTr) 1633 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1634 emitInlineJumpTable(JTIndex); 1635 return; 1636 } else if (MCID.Opcode == ARM::BR_JTm) { 1637 // First emit a ldr pc, [] instruction. 1638 emitLoadStoreInstruction(MI, ARM::PC); 1639 1640 // Then emit the inline jump table. 1641 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1642 return; 1643 } 1644 1645 // Part of binary is determined by TableGn. 1646 unsigned Binary = getBinaryCodeForInstr(MI); 1647 1648 // Set the conditional execution predicate 1649 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1650 1651 if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR) 1652 // The return register is LR. 1653 Binary |= II->getRegisterInfo().getEncodingValue(ARM::LR); 1654 else 1655 // otherwise, set the return register 1656 Binary |= getMachineOpValue(MI, 0); 1657 1658 emitWordLE(Binary); 1659 } 1660 1661 unsigned ARMCodeEmitter::encodeVFPRd(const MachineInstr &MI, 1662 unsigned OpIdx) const { 1663 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1664 unsigned Binary = 0; 1665 bool isSPVFP = ARM::SPRRegClass.contains(RegD); 1666 RegD = II->getRegisterInfo().getEncodingValue(RegD); 1667 if (!isSPVFP) { 1668 Binary |= (RegD & 0x0F) << ARMII::RegRdShift; 1669 Binary |= ((RegD & 0x10) >> 4) << ARMII::D_BitShift; 1670 } else { 1671 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1672 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1673 } 1674 return Binary; 1675 } 1676 1677 unsigned ARMCodeEmitter::encodeVFPRn(const MachineInstr &MI, 1678 unsigned OpIdx) const { 1679 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1680 unsigned Binary = 0; 1681 bool isSPVFP = ARM::SPRRegClass.contains(RegN); 1682 RegN = II->getRegisterInfo().getEncodingValue(RegN); 1683 if (!isSPVFP) { 1684 Binary |= (RegN & 0x0F) << ARMII::RegRnShift; 1685 Binary |= ((RegN & 0x10) >> 4) << ARMII::N_BitShift; 1686 } else { 1687 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1688 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1689 } 1690 return Binary; 1691 } 1692 1693 unsigned ARMCodeEmitter::encodeVFPRm(const MachineInstr &MI, 1694 unsigned OpIdx) const { 1695 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1696 unsigned Binary = 0; 1697 bool isSPVFP = ARM::SPRRegClass.contains(RegM); 1698 RegM = II->getRegisterInfo().getEncodingValue(RegM); 1699 if (!isSPVFP) { 1700 Binary |= (RegM & 0x0F); 1701 Binary |= ((RegM & 0x10) >> 4) << ARMII::M_BitShift; 1702 } else { 1703 Binary |= ((RegM & 0x1E) >> 1); 1704 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1705 } 1706 return Binary; 1707 } 1708 1709 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { 1710 const MCInstrDesc &MCID = MI.getDesc(); 1711 1712 // Part of binary is determined by TableGn. 1713 unsigned Binary = getBinaryCodeForInstr(MI); 1714 1715 // Set the conditional execution predicate 1716 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1717 1718 unsigned OpIdx = 0; 1719 1720 // Encode Dd / Sd. 1721 Binary |= encodeVFPRd(MI, OpIdx++); 1722 1723 // If this is a two-address operand, skip it, e.g. FMACD. 1724 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1725 ++OpIdx; 1726 1727 // Encode Dn / Sn. 1728 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1729 Binary |= encodeVFPRn(MI, OpIdx++); 1730 1731 if (OpIdx == MCID.getNumOperands() || 1732 MCID.OpInfo[OpIdx].isPredicate() || 1733 MCID.OpInfo[OpIdx].isOptionalDef()) { 1734 // FCMPEZD etc. has only one operand. 1735 emitWordLE(Binary); 1736 return; 1737 } 1738 1739 // Encode Dm / Sm. 1740 Binary |= encodeVFPRm(MI, OpIdx); 1741 1742 emitWordLE(Binary); 1743 } 1744 1745 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { 1746 const MCInstrDesc &MCID = MI.getDesc(); 1747 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1748 1749 // Part of binary is determined by TableGn. 1750 unsigned Binary = getBinaryCodeForInstr(MI); 1751 1752 // Set the conditional execution predicate 1753 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1754 1755 switch (Form) { 1756 default: break; 1757 case ARMII::VFPConv1Frm: 1758 case ARMII::VFPConv2Frm: 1759 case ARMII::VFPConv3Frm: 1760 // Encode Dd / Sd. 1761 Binary |= encodeVFPRd(MI, 0); 1762 break; 1763 case ARMII::VFPConv4Frm: 1764 // Encode Dn / Sn. 1765 Binary |= encodeVFPRn(MI, 0); 1766 break; 1767 case ARMII::VFPConv5Frm: 1768 // Encode Dm / Sm. 1769 Binary |= encodeVFPRm(MI, 0); 1770 break; 1771 } 1772 1773 switch (Form) { 1774 default: break; 1775 case ARMII::VFPConv1Frm: 1776 // Encode Dm / Sm. 1777 Binary |= encodeVFPRm(MI, 1); 1778 break; 1779 case ARMII::VFPConv2Frm: 1780 case ARMII::VFPConv3Frm: 1781 // Encode Dn / Sn. 1782 Binary |= encodeVFPRn(MI, 1); 1783 break; 1784 case ARMII::VFPConv4Frm: 1785 case ARMII::VFPConv5Frm: 1786 // Encode Dd / Sd. 1787 Binary |= encodeVFPRd(MI, 1); 1788 break; 1789 } 1790 1791 if (Form == ARMII::VFPConv5Frm) 1792 // Encode Dn / Sn. 1793 Binary |= encodeVFPRn(MI, 2); 1794 else if (Form == ARMII::VFPConv3Frm) 1795 // Encode Dm / Sm. 1796 Binary |= encodeVFPRm(MI, 2); 1797 1798 emitWordLE(Binary); 1799 } 1800 1801 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1802 // Part of binary is determined by TableGn. 1803 unsigned Binary = getBinaryCodeForInstr(MI); 1804 1805 // Set the conditional execution predicate 1806 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1807 1808 if (MI.getOpcode() == ARM::VLDRS || MI.getOpcode() == ARM::VLDRD || 1809 MI.getOpcode() == ARM::VSTRS || MI.getOpcode() == ARM::VSTRD){ 1810 emitWordLE(Binary); 1811 return; 1812 } 1813 1814 unsigned OpIdx = 0; 1815 1816 // Encode Dd / Sd. 1817 Binary |= encodeVFPRd(MI, OpIdx++); 1818 1819 // Encode address base. 1820 const MachineOperand &Base = MI.getOperand(OpIdx++); 1821 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1822 1823 // If there is a non-zero immediate offset, encode it. 1824 if (Base.isReg()) { 1825 const MachineOperand &Offset = MI.getOperand(OpIdx); 1826 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1827 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1828 Binary |= 1 << ARMII::U_BitShift; 1829 Binary |= ImmOffs; 1830 emitWordLE(Binary); 1831 return; 1832 } 1833 } 1834 1835 // If immediate offset is omitted, default to +0. 1836 Binary |= 1 << ARMII::U_BitShift; 1837 1838 emitWordLE(Binary); 1839 } 1840 1841 void 1842 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { 1843 const MCInstrDesc &MCID = MI.getDesc(); 1844 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1845 1846 // Part of binary is determined by TableGn. 1847 unsigned Binary = getBinaryCodeForInstr(MI); 1848 1849 // Set the conditional execution predicate 1850 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1851 1852 // Skip operand 0 of an instruction with base register update. 1853 unsigned OpIdx = 0; 1854 if (IsUpdating) 1855 ++OpIdx; 1856 1857 // Set base address operand 1858 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1859 1860 // Set addressing mode by modifying bits U(23) and P(24) 1861 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1862 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1863 1864 // Set bit W(21) 1865 if (IsUpdating) 1866 Binary |= 0x1 << ARMII::W_BitShift; 1867 1868 // First register is encoded in Dd. 1869 Binary |= encodeVFPRd(MI, OpIdx+2); 1870 1871 // Count the number of registers. 1872 unsigned NumRegs = 1; 1873 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { 1874 const MachineOperand &MO = MI.getOperand(i); 1875 if (!MO.isReg() || MO.isImplicit()) 1876 break; 1877 ++NumRegs; 1878 } 1879 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0) 1880 // Otherwise, it will be 0, in the case of 32-bit registers. 1881 if(Binary & 0x100) 1882 Binary |= NumRegs * 2; 1883 else 1884 Binary |= NumRegs; 1885 1886 emitWordLE(Binary); 1887 } 1888 1889 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) { 1890 unsigned Opcode = MI.getDesc().Opcode; 1891 // Part of binary is determined by TableGn. 1892 unsigned Binary = getBinaryCodeForInstr(MI); 1893 1894 if (Opcode == ARM::FCONSTS) { 1895 unsigned Imm = getMachineOpValue(MI, 1); 1896 Binary &= ~(0x780000 >> 19); 1897 Binary |= (Imm & 0x780000) >> 19; 1898 Binary &= ~(0x3800000 >> 7); 1899 Binary |= (Imm & 0x3800000) >> 7; 1900 Binary = VFPThumb2PostEncoder(MI, Binary); 1901 } 1902 1903 // Set the conditional execution predicate 1904 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1905 1906 emitWordLE(Binary); 1907 } 1908 1909 unsigned ARMCodeEmitter::encodeNEONRd(const MachineInstr &MI, 1910 unsigned OpIdx) const { 1911 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1912 unsigned Binary = 0; 1913 RegD = II->getRegisterInfo().getEncodingValue(RegD); 1914 Binary |= (RegD & 0xf) << ARMII::RegRdShift; 1915 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; 1916 return Binary; 1917 } 1918 1919 unsigned ARMCodeEmitter::encodeNEONRn(const MachineInstr &MI, 1920 unsigned OpIdx) const { 1921 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1922 unsigned Binary = 0; 1923 RegN = II->getRegisterInfo().getEncodingValue(RegN); 1924 Binary |= (RegN & 0xf) << ARMII::RegRnShift; 1925 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; 1926 return Binary; 1927 } 1928 1929 unsigned ARMCodeEmitter::encodeNEONRm(const MachineInstr &MI, 1930 unsigned OpIdx) const { 1931 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1932 unsigned Binary = 0; 1933 RegM = II->getRegisterInfo().getEncodingValue(RegM); 1934 Binary |= (RegM & 0xf); 1935 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; 1936 return Binary; 1937 } 1938 1939 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON 1940 /// data-processing instruction to the corresponding Thumb encoding. 1941 static unsigned convertNEONDataProcToThumb(unsigned Binary) { 1942 assert((Binary & 0xfe000000) == 0xf2000000 && 1943 "not an ARM NEON data-processing instruction"); 1944 unsigned UBit = (Binary >> 24) & 1; 1945 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff); 1946 } 1947 1948 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { 1949 unsigned Binary = getBinaryCodeForInstr(MI); 1950 1951 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx; 1952 const MCInstrDesc &MCID = MI.getDesc(); 1953 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { 1954 RegTOpIdx = 0; 1955 RegNOpIdx = 1; 1956 LnOpIdx = 2; 1957 } else { // ARMII::NSetLnFrm 1958 RegTOpIdx = 2; 1959 RegNOpIdx = 0; 1960 LnOpIdx = 3; 1961 } 1962 1963 // Set the conditional execution predicate 1964 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1965 1966 unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); 1967 RegT = II->getRegisterInfo().getEncodingValue(RegT); 1968 Binary |= (RegT << ARMII::RegRdShift); 1969 Binary |= encodeNEONRn(MI, RegNOpIdx); 1970 1971 unsigned LaneShift; 1972 if ((Binary & (1 << 22)) != 0) 1973 LaneShift = 0; // 8-bit elements 1974 else if ((Binary & (1 << 5)) != 0) 1975 LaneShift = 1; // 16-bit elements 1976 else 1977 LaneShift = 2; // 32-bit elements 1978 1979 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; 1980 unsigned Opc1 = Lane >> 2; 1981 unsigned Opc2 = Lane & 3; 1982 assert((Opc1 & 3) == 0 && "out-of-range lane number operand"); 1983 Binary |= (Opc1 << 21); 1984 Binary |= (Opc2 << 5); 1985 1986 emitWordLE(Binary); 1987 } 1988 1989 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { 1990 unsigned Binary = getBinaryCodeForInstr(MI); 1991 1992 // Set the conditional execution predicate 1993 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1994 1995 unsigned RegT = MI.getOperand(1).getReg(); 1996 RegT = II->getRegisterInfo().getEncodingValue(RegT); 1997 Binary |= (RegT << ARMII::RegRdShift); 1998 Binary |= encodeNEONRn(MI, 0); 1999 emitWordLE(Binary); 2000 } 2001 2002 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { 2003 unsigned Binary = getBinaryCodeForInstr(MI); 2004 // Destination register is encoded in Dd. 2005 Binary |= encodeNEONRd(MI, 0); 2006 // Immediate fields: Op, Cmode, I, Imm3, Imm4 2007 unsigned Imm = MI.getOperand(1).getImm(); 2008 unsigned Op = (Imm >> 12) & 1; 2009 unsigned Cmode = (Imm >> 8) & 0xf; 2010 unsigned I = (Imm >> 7) & 1; 2011 unsigned Imm3 = (Imm >> 4) & 0x7; 2012 unsigned Imm4 = Imm & 0xf; 2013 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4; 2014 if (IsThumb) 2015 Binary = convertNEONDataProcToThumb(Binary); 2016 emitWordLE(Binary); 2017 } 2018 2019 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { 2020 const MCInstrDesc &MCID = MI.getDesc(); 2021 unsigned Binary = getBinaryCodeForInstr(MI); 2022 // Destination register is encoded in Dd; source register in Dm. 2023 unsigned OpIdx = 0; 2024 Binary |= encodeNEONRd(MI, OpIdx++); 2025 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 2026 ++OpIdx; 2027 Binary |= encodeNEONRm(MI, OpIdx); 2028 if (IsThumb) 2029 Binary = convertNEONDataProcToThumb(Binary); 2030 // FIXME: This does not handle VDUPfdf or VDUPfqf. 2031 emitWordLE(Binary); 2032 } 2033 2034 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { 2035 const MCInstrDesc &MCID = MI.getDesc(); 2036 unsigned Binary = getBinaryCodeForInstr(MI); 2037 // Destination register is encoded in Dd; source registers in Dn and Dm. 2038 unsigned OpIdx = 0; 2039 Binary |= encodeNEONRd(MI, OpIdx++); 2040 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 2041 ++OpIdx; 2042 Binary |= encodeNEONRn(MI, OpIdx++); 2043 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 2044 ++OpIdx; 2045 Binary |= encodeNEONRm(MI, OpIdx); 2046 if (IsThumb) 2047 Binary = convertNEONDataProcToThumb(Binary); 2048 // FIXME: This does not handle VMOVDneon or VMOVQ. 2049 emitWordLE(Binary); 2050 } 2051 2052 #include "ARMGenCodeEmitter.inc" 2053
