1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the TargetRegisterInfo interface. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetRegisterInfo.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/CodeGen/MachineFunction.h" 17 #include "llvm/CodeGen/MachineRegisterInfo.h" 18 #include "llvm/CodeGen/VirtRegMap.h" 19 #include "llvm/Support/raw_ostream.h" 20 21 using namespace llvm; 22 23 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 24 regclass_iterator RCB, regclass_iterator RCE, 25 const char *const *SRINames, 26 const unsigned *SRILaneMasks, 27 unsigned SRICoveringLanes) 28 : InfoDesc(ID), SubRegIndexNames(SRINames), 29 SubRegIndexLaneMasks(SRILaneMasks), 30 RegClassBegin(RCB), RegClassEnd(RCE), 31 CoveringLanes(SRICoveringLanes) { 32 } 33 34 TargetRegisterInfo::~TargetRegisterInfo() {} 35 36 void PrintReg::print(raw_ostream &OS) const { 37 if (!Reg) 38 OS << "%noreg"; 39 else if (TargetRegisterInfo::isStackSlot(Reg)) 40 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); 41 else if (TargetRegisterInfo::isVirtualRegister(Reg)) 42 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); 43 else if (TRI && Reg < TRI->getNumRegs()) 44 OS << '%' << TRI->getName(Reg); 45 else 46 OS << "%physreg" << Reg; 47 if (SubIdx) { 48 if (TRI) 49 OS << ':' << TRI->getSubRegIndexName(SubIdx); 50 else 51 OS << ":sub(" << SubIdx << ')'; 52 } 53 } 54 55 void PrintRegUnit::print(raw_ostream &OS) const { 56 // Generic printout when TRI is missing. 57 if (!TRI) { 58 OS << "Unit~" << Unit; 59 return; 60 } 61 62 // Check for invalid register units. 63 if (Unit >= TRI->getNumRegUnits()) { 64 OS << "BadUnit~" << Unit; 65 return; 66 } 67 68 // Normal units have at least one root. 69 MCRegUnitRootIterator Roots(Unit, TRI); 70 assert(Roots.isValid() && "Unit has no roots."); 71 OS << TRI->getName(*Roots); 72 for (++Roots; Roots.isValid(); ++Roots) 73 OS << '~' << TRI->getName(*Roots); 74 } 75 76 /// getAllocatableClass - Return the maximal subclass of the given register 77 /// class that is alloctable, or NULL. 78 const TargetRegisterClass * 79 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { 80 if (!RC || RC->isAllocatable()) 81 return RC; 82 83 const unsigned *SubClass = RC->getSubClassMask(); 84 for (unsigned Base = 0, BaseE = getNumRegClasses(); 85 Base < BaseE; Base += 32) { 86 unsigned Idx = Base; 87 for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) { 88 unsigned Offset = countTrailingZeros(Mask); 89 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset); 90 if (SubRC->isAllocatable()) 91 return SubRC; 92 Mask >>= Offset; 93 Idx += Offset + 1; 94 } 95 } 96 return NULL; 97 } 98 99 /// getMinimalPhysRegClass - Returns the Register Class of a physical 100 /// register of the given type, picking the most sub register class of 101 /// the right type that contains this physreg. 102 const TargetRegisterClass * 103 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { 104 assert(isPhysicalRegister(reg) && "reg must be a physical register"); 105 106 // Pick the most sub register class of the right type that contains 107 // this physreg. 108 const TargetRegisterClass* BestRC = 0; 109 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ 110 const TargetRegisterClass* RC = *I; 111 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && 112 (!BestRC || BestRC->hasSubClass(RC))) 113 BestRC = RC; 114 } 115 116 assert(BestRC && "Couldn't find the register class"); 117 return BestRC; 118 } 119 120 /// getAllocatableSetForRC - Toggle the bits that represent allocatable 121 /// registers for the specific register class. 122 static void getAllocatableSetForRC(const MachineFunction &MF, 123 const TargetRegisterClass *RC, BitVector &R){ 124 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); 125 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); 126 for (unsigned i = 0; i != Order.size(); ++i) 127 R.set(Order[i]); 128 } 129 130 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, 131 const TargetRegisterClass *RC) const { 132 BitVector Allocatable(getNumRegs()); 133 if (RC) { 134 // A register class with no allocatable subclass returns an empty set. 135 const TargetRegisterClass *SubClass = getAllocatableClass(RC); 136 if (SubClass) 137 getAllocatableSetForRC(MF, SubClass, Allocatable); 138 } else { 139 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), 140 E = regclass_end(); I != E; ++I) 141 if ((*I)->isAllocatable()) 142 getAllocatableSetForRC(MF, *I, Allocatable); 143 } 144 145 // Mask out the reserved registers 146 BitVector Reserved = getReservedRegs(MF); 147 Allocatable &= Reserved.flip(); 148 149 return Allocatable; 150 } 151 152 static inline 153 const TargetRegisterClass *firstCommonClass(const uint32_t *A, 154 const uint32_t *B, 155 const TargetRegisterInfo *TRI) { 156 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32) 157 if (unsigned Common = *A++ & *B++) 158 return TRI->getRegClass(I + countTrailingZeros(Common)); 159 return 0; 160 } 161 162 const TargetRegisterClass * 163 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, 164 const TargetRegisterClass *B) const { 165 // First take care of the trivial cases. 166 if (A == B) 167 return A; 168 if (!A || !B) 169 return 0; 170 171 // Register classes are ordered topologically, so the largest common 172 // sub-class it the common sub-class with the smallest ID. 173 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this); 174 } 175 176 const TargetRegisterClass * 177 TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 178 const TargetRegisterClass *B, 179 unsigned Idx) const { 180 assert(A && B && "Missing register class"); 181 assert(Idx && "Bad sub-register index"); 182 183 // Find Idx in the list of super-register indices. 184 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) 185 if (RCI.getSubReg() == Idx) 186 // The bit mask contains all register classes that are projected into B 187 // by Idx. Find a class that is also a sub-class of A. 188 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this); 189 return 0; 190 } 191 192 const TargetRegisterClass *TargetRegisterInfo:: 193 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 194 const TargetRegisterClass *RCB, unsigned SubB, 195 unsigned &PreA, unsigned &PreB) const { 196 assert(RCA && SubA && RCB && SubB && "Invalid arguments"); 197 198 // Search all pairs of sub-register indices that project into RCA and RCB 199 // respectively. This is quadratic, but usually the sets are very small. On 200 // most targets like X86, there will only be a single sub-register index 201 // (e.g., sub_16bit projecting into GR16). 202 // 203 // The worst case is a register class like DPR on ARM. 204 // We have indices dsub_0..dsub_7 projecting into that class. 205 // 206 // It is very common that one register class is a sub-register of the other. 207 // Arrange for RCA to be the larger register so the answer will be found in 208 // the first iteration. This makes the search linear for the most common 209 // case. 210 const TargetRegisterClass *BestRC = 0; 211 unsigned *BestPreA = &PreA; 212 unsigned *BestPreB = &PreB; 213 if (RCA->getSize() < RCB->getSize()) { 214 std::swap(RCA, RCB); 215 std::swap(SubA, SubB); 216 std::swap(BestPreA, BestPreB); 217 } 218 219 // Also terminate the search one we have found a register class as small as 220 // RCA. 221 unsigned MinSize = RCA->getSize(); 222 223 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) { 224 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); 225 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) { 226 // Check if a common super-register class exists for this index pair. 227 const TargetRegisterClass *RC = 228 firstCommonClass(IA.getMask(), IB.getMask(), this); 229 if (!RC || RC->getSize() < MinSize) 230 continue; 231 232 // The indexes must compose identically: PreA+SubA == PreB+SubB. 233 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); 234 if (FinalA != FinalB) 235 continue; 236 237 // Is RC a better candidate than BestRC? 238 if (BestRC && RC->getSize() >= BestRC->getSize()) 239 continue; 240 241 // Yes, RC is the smallest super-register seen so far. 242 BestRC = RC; 243 *BestPreA = IA.getSubReg(); 244 *BestPreB = IB.getSubReg(); 245 246 // Bail early if we reached MinSize. We won't find a better candidate. 247 if (BestRC->getSize() == MinSize) 248 return BestRC; 249 } 250 } 251 return BestRC; 252 } 253 254 // Compute target-independent register allocator hints to help eliminate copies. 255 void 256 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, 257 ArrayRef<MCPhysReg> Order, 258 SmallVectorImpl<MCPhysReg> &Hints, 259 const MachineFunction &MF, 260 const VirtRegMap *VRM) const { 261 const MachineRegisterInfo &MRI = MF.getRegInfo(); 262 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 263 264 // Hints with HintType != 0 were set by target-dependent code. 265 // Such targets must provide their own implementation of 266 // TRI::getRegAllocationHints to interpret those hint types. 267 assert(Hint.first == 0 && "Target must implement TRI::getRegAllocationHints"); 268 269 // Target-independent hints are either a physical or a virtual register. 270 unsigned Phys = Hint.second; 271 if (VRM && isVirtualRegister(Phys)) 272 Phys = VRM->getPhys(Phys); 273 274 // Check that Phys is a valid hint in VirtReg's register class. 275 if (!isPhysicalRegister(Phys)) 276 return; 277 if (MRI.isReserved(Phys)) 278 return; 279 // Check that Phys is in the allocation order. We shouldn't heed hints 280 // from VirtReg's register class if they aren't in the allocation order. The 281 // target probably has a reason for removing the register. 282 if (std::find(Order.begin(), Order.end(), Phys) == Order.end()) 283 return; 284 285 // All clear, tell the register allocator to prefer this register. 286 Hints.push_back(Phys); 287 } 288
