| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 379 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
380 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
381 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
382 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
383 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
384 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
385 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
386 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
416 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
417 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/clang/test/CodeGen/ |
| x86_64-arguments.c | 155 typedef float v4f32 __attribute__((__vector_size__(16))); typedef
156 v4f32 f25(v4f32 X) {
179 v4f32 v;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 189 { ISD::FP_EXTEND, MVT::v4f32, 4 }
235 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
236 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
244 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
245 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
246 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
247 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
248 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
249 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
259 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }
[all...] |
| ARMISelLowering.cpp | 463 addQRTypeForNEON(MVT::v4f32);
472 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
473 // supported for v4f32.
509 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
510 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
511 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
512 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
513 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
514 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
515 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand)
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 98 v4f32 = 43, // 4 x f32 enumerator in enum:llvm::MVT::SimpleValueType
213 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
292 case v4f32:
328 case v4f32:
393 case v4f32:
527 if (NumElements == 4) return MVT::v4f32;
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 64 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
65 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
76 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
77 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
86 setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
94 setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
|
| AMDILISelLowering.cpp | 53 (int)MVT::v4f32,
78 (int)MVT::v4f32,
407 FLTTY = MVT::v4f32;
|
| R600ISelLowering.cpp | 32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
41 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
43 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
45 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
47 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
552 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
646 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19);
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 317 DecodeSHUFPMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
356 DecodeUNPCKLMask(MVT::v4f32, ShuffleMask);
392 DecodeUNPCKHMask(MVT::v4f32, ShuffleMask);
408 DecodePSHUFMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 161 case MVT::v4f32: return "v4f32";
224 case MVT::v4f32: return VectorType::get(Type::getFloatTy(Context), 4);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600GenRegisterInfo.pl | 97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
|
| AMDILISelLowering.cpp | 61 (int)MVT::v4f32,
89 (int)MVT::v4f32,
505 FLTTY = MVT::v4f32;
|
| R600ISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
|
| SIISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600GenRegisterInfo.pl | 97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
|
| AMDILISelLowering.cpp | 61 (int)MVT::v4f32,
89 (int)MVT::v4f32,
505 FLTTY = MVT::v4f32;
|
| R600ISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
|
| SIISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 631 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
644 // v4f32 != v4f32 could be translate to unordered not equal
645 else if (VecVT == MVT::v4f32)
658 else if (VecVT == MVT::v4f32)
673 if (VecVT == MVT::v4f32)
679 if (VecVT == MVT::v4f32)
683 if (VecVT == MVT::v4f32)
694 // types (v16i8, v8i16, v4i32, and v4f32).
703 case MVT::v4f32
[all...] |
| PPCISelLowering.cpp | 458 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
459 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
460 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
461 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
463 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
468 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
469 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
472 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
473 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
480 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom)
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 102 case MVT::v4f32: return "MVT::v4f32";
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 64 case MVT::v4f32:
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 69 addRegisterClass(MVT::v4f32, &AArch64::VPR128RegClass);
282 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
293 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
[all...] |
