| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 67 SmallVector<ISD::OutputArg, 4> Outs;
68 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
71 Outs, Fn->getContext());
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 317 const SmallVectorImpl<ISD::OutputArg> &Outs,
329 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
399 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
408 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
435 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
437 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
446 Outs, OutVals, Ins, DAG);
475 ISD::ArgFlagsTy Flags = Outs[i].Flags
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 267 const SmallVectorImpl<ISD::OutputArg> &Outs) {
268 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
352 const SmallVectorImpl<ISD::OutputArg> &Outs) {
353 State.AnalyzeReturn(Outs, RetCC_MSP430);
396 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
414 Outs, OutVals, Ins, dl, DAG, InVals);
524 const SmallVectorImpl<ISD::OutputArg> &Outs,
532 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
540 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 75 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
494 const SmallVectorImpl<ISD::OutputArg> &Outs,
551 if (Outs[OIdx].Flags.isByVal() == false) {
563 // update the index for Outs
571 assert((getValueType(Ty) == Outs[OIdx].VT ||
572 (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
592 unsigned align = Outs[OIdx].Flags.getByValAlign();
655 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
680 // Args.size() and Outs.size() need not match
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 173 const SmallVectorImpl<ISD::OutputArg> &Outs,
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
184 const SmallVectorImpl<ISD::OutputArg> &Outs,
197 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
246 const SmallVectorImpl<ISD::OutputArg> &Outs,
257 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
687 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
703 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 807 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
822 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
