| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 105 /// rotate and mask opcode and mask operation.
173 /// Reg in an asm, because the load or store opcode would have to change.
339 // opcode and that it has a immediate integer right operand.
380 unsigned Opcode = N->getOpcode();
385 if (Opcode == ISD::SHL) {
390 } else if (Opcode == ISD::SRL) {
397 } else if (Opcode == ISD::ROTL) {
[all...] |
| PPCInstrInfo.cpp | 322 unsigned Opcode;
324 default: Opcode = PPC::NOP; break;
325 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
326 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
327 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
331 BuildMI(MBB, MI, DL, get(Opcode));
648 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
684 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | [all...] |
| SIISelLowering.cpp | 748 static SDNode *findUser(SDValue Value, unsigned Opcode) {
757 if (I->getOpcode() == Opcode)
[all...] |
| SIInstrInfo.cpp | 70 unsigned Opcode;
107 Opcode = AMDGPU::S_MOV_B32;
112 Opcode = AMDGPU::S_MOV_B32;
117 Opcode = AMDGPU::S_MOV_B32;
130 Opcode = AMDGPU::V_MOV_B32_e32;
135 Opcode = AMDGPU::V_MOV_B32_e32;
141 Opcode = AMDGPU::V_MOV_B32_e32;
147 Opcode = AMDGPU::V_MOV_B32_e32;
153 Opcode = AMDGPU::V_MOV_B32_e32;
162 get(Opcode), RI.getSubReg(DestReg, SubIdx))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 45 getTargetNodeName(unsigned Opcode) const
47 switch (Opcode)
739 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
742 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
746 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 357 unsigned Opcode = I->getOpcode();
359 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub) {
382 if (Opcode == Instruction::FSub)
[all...] |
| InstCombineAndOrXor.cpp | 86 /// opcode and two operands into either a constant true or false, or a brand
98 /// opcode and two operands into either a FCmp instruction. isordered is passed
[all...] |
| InstructionCombining.cpp | 141 Instruction::BinaryOps Opcode = I.getOpcode();
142 if (Opcode != Instruction::Add &&
143 Opcode != Instruction::Sub) {
158 if (Opcode == Instruction::Add) {
204 Instruction::BinaryOps Opcode = I.getOpcode();
220 if (Op0 && Op0->getOpcode() == Opcode) {
226 if (Value *V = SimplifyBinOp(Opcode, B, C, DL)) {
249 if (Op1 && Op1->getOpcode() == Opcode) {
255 if (Value *V = SimplifyBinOp(Opcode, A, B, DL)) {
271 if (Op0 && Op0->getOpcode() == Opcode) {
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| IndVarSimplify.cpp | 795 unsigned Opcode = DU.NarrowUse->getOpcode();
796 switch (Opcode) {
[all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcher.h | 61 CheckOpcode, // Fail if not opcode.
62 SwitchOpcode, // Dispatch based on opcode.
478 /// specified opcode, if not it fails to match.
480 const SDNodeInfo &Opcode;
482 CheckOpcodeMatcher(const SDNodeInfo &opcode)
483 : Matcher(CheckOpcode), Opcode(opcode) {}
485 const SDNodeInfo &getOpcode() const { return Opcode; }
500 /// SwitchOpcodeMatcher - Switch based on the current node's opcode, dispatching
501 /// to one matcher per opcode. If the opcode doesn't match any of the cases
[all...] |
| /external/mesa3d/src/mesa/program/ |
| prog_instruction.h | 340 gl_inst_opcode Opcode;
439 _mesa_num_inst_src_regs(gl_inst_opcode opcode);
442 _mesa_num_inst_dst_regs(gl_inst_opcode opcode);
445 _mesa_is_tex_instruction(gl_inst_opcode opcode);
451 _mesa_opcode_string(gl_inst_opcode opcode);
|
| /dalvik/libdex/ |
| DexOpcodes.h | 18 * Dalvik opcode information.
21 * automatically by the opcode-gen tool. Any edits to the generated
24 * See the file opcode-gen/README.txt for information about updating
34 * kMaxOpcodeValue: the highest possible raw (unpacked) opcode value
36 * kNumPackedOpcodes: the highest possible packed opcode value of a
37 * valid Dalvik opcode, plus one
42 // BEGIN(libdex-maximum-values); GENERATED AUTOMATICALLY BY opcode-gen
45 // END(libdex-maximum-values); GENERATED AUTOMATICALLY BY opcode-gen
58 * associated with each is the corresponding packed opcode number.
59 * This is different than the opcode value from the Dalvik bytecod
[all...] |
| /external/chromium_org/v8/src/arm/ |
| constants-arm.h | 129 enum Opcode {
607 return static_cast<Opcode>(Bits(24, 21));
609 inline Opcode OpcodeField() const {
610 return static_cast<Opcode>(BitField(24, 21));
|
| lithium-arm.h | 168 virtual Opcode opcode() const V8_FINAL V8_OVERRIDE { \
203 enum Opcode {
211 virtual Opcode opcode() const = 0;
215 bool Is##type() const { return opcode() == k##type; }
220 // an opcode.
[all...] |
| /external/chromium_org/v8/src/ia32/ |
| lithium-ia32.h | 165 virtual Opcode opcode() const V8_FINAL V8_OVERRIDE { \
200 enum Opcode {
208 virtual Opcode opcode() const = 0;
212 bool Is##type() const { return opcode() == k##type; }
217 // an opcode.
[all...] |
| /external/chromium_org/v8/src/mips/ |
| lithium-mips.h | 165 virtual Opcode opcode() const V8_FINAL V8_OVERRIDE { \
200 enum Opcode {
208 virtual Opcode opcode() const = 0;
212 bool Is##type() const { return opcode() == k##type; }
217 // an opcode.
[all...] |
| /external/chromium_org/v8/src/x64/ |
| lithium-x64.h | 165 virtual Opcode opcode() const V8_FINAL V8_OVERRIDE { \
200 enum Opcode {
208 virtual Opcode opcode() const = 0;
212 bool Is##type() const { return opcode() == k##type; }
217 // an opcode.
[all...] |
| /external/chromium_org/v8/src/x87/ |
| lithium-x87.h | 166 virtual Opcode opcode() const V8_FINAL V8_OVERRIDE { \
201 enum Opcode {
209 virtual Opcode opcode() const = 0;
213 bool Is##type() const { return opcode() == k##type; }
218 // an opcode.
[all...] |
| /external/clang/include/clang/Analysis/Analyses/ |
| ThreadSafetyTIL.h | 253 TIL_Opcode opcode() const { return static_cast<TIL_Opcode>(Opcode); } function in class:clang::threadSafety::SExpr
280 SExpr(TIL_Opcode Op) : Opcode(Op), Reserved(0), Flags(0) {}
281 SExpr(const SExpr &E) : Opcode(E.Opcode), Reserved(0), Flags(E.Flags) {}
283 const unsigned char Opcode;
337 unsigned Op = E->opcode();
363 static bool classof(const SExpr *E) { return E->opcode() == COP_Variable; }
432 static bool classof(const SExpr *E) { return E->opcode() == COP_Future; }
501 TIL_Opcode Op = Ptr->opcode();
[all...] |
| /external/llvm/bindings/ocaml/llvm/ |
| llvm.ml | 141 module Opcode = struct
276 | Instruction of Opcode.t
442 external constexpr_opcode : llvalue -> Opcode.t = "llvm_constexpr_get_opcode"
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 487 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
488 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
663 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
664 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 63 uint16_t MLxOpc; // MLA / MLS opcode
64 uint16_t MulOpc; // Expanded multiplication opcode
65 uint16_t AddSubOpc; // Expanded add / sub opcode
[all...] |
| ARMFastISel.cpp | 756 unsigned Opcode = Instruction::UserOp1;
762 Opcode = I->getOpcode();
766 Opcode = C->getOpcode();
776 switch (Opcode) {
[all...] |
