1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Sparc uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef SPARC_ISELLOWERING_H 16 #define SPARC_ISELLOWERING_H 17 18 #include "Sparc.h" 19 #include "llvm/Target/TargetLowering.h" 20 21 namespace llvm { 22 class SparcSubtarget; 23 24 namespace SPISD { 25 enum { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 CMPICC, // Compare two GPR operands, set icc+xcc. 28 CMPFCC, // Compare two FP operands, set fcc. 29 BRICC, // Branch to dest on icc condition 30 BRXCC, // Branch to dest on xcc condition (64-bit only). 31 BRFCC, // Branch to dest on fcc condition 32 SELECT_ICC, // Select between two values using the current ICC flags. 33 SELECT_XCC, // Select between two values using the current XCC flags. 34 SELECT_FCC, // Select between two values using the current FCC flags. 35 36 Hi, Lo, // Hi/Lo operations, typically on a global address. 37 38 FTOI, // FP to Int within a FP register. 39 ITOF, // Int to FP within a FP register. 40 FTOX, // FP to Int64 within a FP register. 41 XTOF, // Int64 to FP within a FP register. 42 43 CALL, // A call instruction. 44 RET_FLAG, // Return with a flag operand. 45 GLOBAL_BASE_REG, // Global base reg for PIC. 46 FLUSHW, // FLUSH register windows to stack. 47 48 TLS_ADD, // For Thread Local Storage (TLS). 49 TLS_LD, 50 TLS_CALL 51 }; 52 } 53 54 class SparcTargetLowering : public TargetLowering { 55 const SparcSubtarget *Subtarget; 56 public: 57 SparcTargetLowering(TargetMachine &TM); 58 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 59 60 /// computeKnownBitsForTargetNode - Determine which of the bits specified 61 /// in Mask are known to be either zero or one and return them in the 62 /// KnownZero/KnownOne bitsets. 63 void computeKnownBitsForTargetNode(const SDValue Op, 64 APInt &KnownZero, 65 APInt &KnownOne, 66 const SelectionDAG &DAG, 67 unsigned Depth = 0) const override; 68 69 MachineBasicBlock * 70 EmitInstrWithCustomInserter(MachineInstr *MI, 71 MachineBasicBlock *MBB) const override; 72 73 const char *getTargetNodeName(unsigned Opcode) const override; 74 75 ConstraintType getConstraintType(const std::string &Constraint) const override; 76 ConstraintWeight 77 getSingleConstraintMatchWeight(AsmOperandInfo &info, 78 const char *constraint) const override; 79 void LowerAsmOperandForConstraint(SDValue Op, 80 std::string &Constraint, 81 std::vector<SDValue> &Ops, 82 SelectionDAG &DAG) const override; 83 std::pair<unsigned, const TargetRegisterClass*> 84 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const override; 85 86 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 87 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; } 88 89 /// getSetCCResultType - Return the ISD::SETCC ValueType 90 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; 91 92 SDValue 93 LowerFormalArguments(SDValue Chain, 94 CallingConv::ID CallConv, 95 bool isVarArg, 96 const SmallVectorImpl<ISD::InputArg> &Ins, 97 SDLoc dl, SelectionDAG &DAG, 98 SmallVectorImpl<SDValue> &InVals) const override; 99 SDValue LowerFormalArguments_32(SDValue Chain, 100 CallingConv::ID CallConv, 101 bool isVarArg, 102 const SmallVectorImpl<ISD::InputArg> &Ins, 103 SDLoc dl, SelectionDAG &DAG, 104 SmallVectorImpl<SDValue> &InVals) const; 105 SDValue LowerFormalArguments_64(SDValue Chain, 106 CallingConv::ID CallConv, 107 bool isVarArg, 108 const SmallVectorImpl<ISD::InputArg> &Ins, 109 SDLoc dl, SelectionDAG &DAG, 110 SmallVectorImpl<SDValue> &InVals) const; 111 112 SDValue 113 LowerCall(TargetLowering::CallLoweringInfo &CLI, 114 SmallVectorImpl<SDValue> &InVals) const override; 115 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 116 SmallVectorImpl<SDValue> &InVals) const; 117 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 118 SmallVectorImpl<SDValue> &InVals) const; 119 120 SDValue 121 LowerReturn(SDValue Chain, 122 CallingConv::ID CallConv, bool isVarArg, 123 const SmallVectorImpl<ISD::OutputArg> &Outs, 124 const SmallVectorImpl<SDValue> &OutVals, 125 SDLoc dl, SelectionDAG &DAG) const override; 126 SDValue LowerReturn_32(SDValue Chain, 127 CallingConv::ID CallConv, bool IsVarArg, 128 const SmallVectorImpl<ISD::OutputArg> &Outs, 129 const SmallVectorImpl<SDValue> &OutVals, 130 SDLoc DL, SelectionDAG &DAG) const; 131 SDValue LowerReturn_64(SDValue Chain, 132 CallingConv::ID CallConv, bool IsVarArg, 133 const SmallVectorImpl<ISD::OutputArg> &Outs, 134 const SmallVectorImpl<SDValue> &OutVals, 135 SDLoc DL, SelectionDAG &DAG) const; 136 137 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 138 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 139 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 140 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 141 142 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const; 143 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const; 144 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, 145 SelectionDAG &DAG) const; 146 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const; 147 148 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, 149 SDValue Arg, SDLoc DL, 150 SelectionDAG &DAG) const; 151 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, 152 const char *LibFuncName, 153 unsigned numArgs) const; 154 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, 155 unsigned &SPCC, 156 SDLoc DL, 157 SelectionDAG &DAG) const; 158 159 bool ShouldShrinkFPConstant(EVT VT) const override { 160 // Do not shrink FP constpool if VT == MVT::f128. 161 // (ldd, call _Q_fdtoq) is more expensive than two ldds. 162 return VT != MVT::f128; 163 } 164 165 void ReplaceNodeResults(SDNode *N, 166 SmallVectorImpl<SDValue>& Results, 167 SelectionDAG &DAG) const override; 168 169 MachineBasicBlock *expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB, 170 unsigned BROpcode) const; 171 MachineBasicBlock *expandAtomicRMW(MachineInstr *MI, 172 MachineBasicBlock *BB, 173 unsigned Opcode, 174 unsigned CondCode = 0) const; 175 }; 176 } // end namespace llvm 177 178 #endif // SPARC_ISELLOWERING_H 179
