/art/compiler/dex/quick/mips/ |
utility_mips.cc | 328 LIR* MipsMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, 334 LIR* MipsMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { 356 LIR* MipsMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 373 first = NewLIR3(kMipsAddu, t_reg.GetReg() , r_base.GetReg(), r_index.GetReg()); 376 NewLIR3(kMipsAddu, t_reg.GetReg() , r_base.GetReg(), t_reg.GetReg()); 409 LIR* MipsMir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 425 first = NewLIR3(kMipsAddu, t_reg.GetReg() , r_base.GetReg(), r_index.GetReg()); 428 NewLIR3(kMipsAddu, t_reg.GetReg() , r_base.GetReg(), t_reg.GetReg()); 455 LIR* MipsMir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, 519 load = res = NewLIR3(opcode, r_dest.GetReg(), displacement, r_base.GetReg()) [all...] |
call_mips.cc | 50 * addiu r_base, rRA, <table> - <BaseLabel> ; table relative to BaseLabel 51 addu r_end, r_end, r_base ; end of table 54 * beq r_base, r_end, done 55 * lw r_key, 0(r_base) 56 * addu r_base, 8 58 * lw r_disp, -4(r_base) 104 RegStorage r_base = AllocTemp(); local 105 NewLIR4(kMipsDelta, r_base.GetReg(), 0, WrapPointer(base_label), WrapPointer(tab_rec)); 106 OpRegRegReg(kOpAdd, r_end, r_end, r_base); 114 LIR* exit_branch = OpCmpBranch(kCondEq, r_base, r_end, NULL) 197 RegStorage r_base = AllocTemp(); local [all...] |
codegen_mips.h | 35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 43 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 45 LIR* GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest); 46 LIR* GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src); 144 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 151 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 152 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 157 LIR* OpVldm(RegStorage r_base, int count) [all...] |
target_mips.cc | 495 LIR* MipsMir2Lir::GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest) { 501 OpRegRegImm(kOpAdd, reg_ptr, r_base, displacement); 509 LIR* MipsMir2Lir::GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src) { 515 OpRegRegImm(kOpAdd, temp_ptr, r_base, displacement);
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int_mips.cc | 332 LIR* MipsMir2Lir::OpVldm(RegStorage r_base, int count) { 337 LIR* MipsMir2Lir::OpVstm(RegStorage r_base, int count) {
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/art/compiler/dex/quick/x86/ |
utility_x86.cc | 251 LIR* X86Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) { 252 DCHECK(!r_base.IsFloat()); 300 return NewLIR3(opcode, dest, r_base.GetReg(), offset); 303 LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { 304 DCHECK(!r_base.IsFloat()); 353 return NewLIR3(opcode, r_base.GetReg(), offset, src); 364 LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) { 384 LIR *l = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), offset); 386 DCHECK(r_base == rs_rX86_SP); 549 LIR* X86Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) [all...] |
codegen_x86.h | 72 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 74 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 78 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 80 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 271 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE; 278 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE; 279 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE; 284 LIR* OpVldm(RegStorage r_base, int count) OVERRIDE; 285 LIR* OpVstm(RegStorage r_base, int count) OVERRIDE; 410 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement [all...] |
int_x86.cc | 905 void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) 1611 int r_base = rs_rX86_SP.GetReg(); local 1646 int r_base = rs_rX86_SP.GetReg(); local 2483 int r_base = rs_rX86_SP.GetReg(); local 2514 int r_base = rs_rX86_SP.GetReg(); local [all...] |
target_x86.cc | 916 int r_base = rs_rX86_SP.GetReg(); local 920 LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo); 923 store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi); [all...] |
/art/compiler/dex/quick/arm/ |
utility_arm.cc | 375 LIR* ArmMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) { 380 LIR* ArmMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { 692 LIR* ArmMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 694 bool all_low_regs = r_base.Low8() && r_index.Low8() && r_dest.Low8(); 722 NewLIR4(kThumb2AddRRR, reg_ptr.GetReg(), r_base.GetReg(), r_index.GetReg(), 725 OpRegRegReg(kOpAdd, reg_ptr, r_base, r_index); 751 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg()); 753 load = NewLIR4(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale); 758 LIR* ArmMir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 760 bool all_low_regs = r_base.Low8() && r_index.Low8() && r_src.Low8() [all...] |
codegen_arm.h | 35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 43 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 147 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 154 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 155 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 160 LIR* OpVldm(RegStorage r_base, int count); 161 LIR* OpVstm(RegStorage r_base, int count); 164 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size) [all...] |
call_arm.cc | 35 * adr r_base, <table> 39 * ldmia r_base!, {r_key, r_disp} 62 RegStorage r_base = AllocTemp(); local 73 NewLIR3(kThumb2Adr, r_base.GetReg(), 0, WrapPointer(tab_rec)); 80 NewLIR2(kThumb2LdmiaWB, r_base.GetReg(), (1 << r_key.GetRegNum()) | (1 << r_disp.GetRegNum()));
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int_arm.cc | [all...] |
/art/compiler/dex/quick/arm64/ |
utility_arm64.cc | 680 LIR* Arm64Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) { 685 LIR* Arm64Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { [all...] |
codegen_arm64.h | 75 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 77 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, 79 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 81 LIR* LoadRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale) 85 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, 87 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, VolatileKind is_volatile) 89 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 91 LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) OVERRIDE; 212 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE; 219 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE [all...] |
call_arm64.cc | 32 * adr r_base, <table> 37 * ldp r_key, r_disp, [r_base], #8 41 * adr r_base, #0 ; This is the instruction from which we compute displacements 42 * add r_base, r_disp 43 * br r_base 62 RegStorage r_base = AllocTempWide(); local 67 NewLIR3(kA64Adr2xd, r_base.GetReg(), 0, WrapPointer(tab_rec)); 77 NewLIR4(kA64LdpPost4rrXD, r_key.GetReg(), r_disp.GetReg(), r_base.GetReg(), 2); 85 LIR* switch_label = NewLIR3(kA64Adr2xd, r_base.GetReg(), 0, -1); 89 OpRegRegRegExtend(kOpAdd, r_base, r_base, As64BitReg(r_disp), kA64Sxtw, 0U) [all...] |
int_arm64.cc | [all...] |
/art/compiler/dex/quick/ |
mir_to_lir.h | [all...] |
gen_common.cc | 510 RegStorage r_base) : 512 storage_index_(storage_index), r_base_(r_base) { 519 // Copy helper's result into r_base, a no-op on all but MIPS. 538 RegStorage r_base; local 542 r_base = AllocTempRef(); 543 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base, 559 r_base = TargetReg(kArg0, kRef); 560 LockTemp(r_base); 561 LoadRefDisp(r_method, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base, 564 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile) 627 RegStorage r_base; local [all...] |