1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "ARMFPUName.h" 11 #include "ARMFeatures.h" 12 #include "MCTargetDesc/ARMAddressingModes.h" 13 #include "MCTargetDesc/ARMArchName.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/ADT/Twine.h" 21 #include "llvm/MC/MCAsmInfo.h" 22 #include "llvm/MC/MCAssembler.h" 23 #include "llvm/MC/MCContext.h" 24 #include "llvm/MC/MCDisassembler.h" 25 #include "llvm/MC/MCELFStreamer.h" 26 #include "llvm/MC/MCExpr.h" 27 #include "llvm/MC/MCInst.h" 28 #include "llvm/MC/MCInstrDesc.h" 29 #include "llvm/MC/MCInstrInfo.h" 30 #include "llvm/MC/MCObjectFileInfo.h" 31 #include "llvm/MC/MCParser/MCAsmLexer.h" 32 #include "llvm/MC/MCParser/MCAsmParser.h" 33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 34 #include "llvm/MC/MCRegisterInfo.h" 35 #include "llvm/MC/MCSection.h" 36 #include "llvm/MC/MCStreamer.h" 37 #include "llvm/MC/MCSubtargetInfo.h" 38 #include "llvm/MC/MCSymbol.h" 39 #include "llvm/MC/MCTargetAsmParser.h" 40 #include "llvm/Support/ARMBuildAttributes.h" 41 #include "llvm/Support/ARMEHABI.h" 42 #include "llvm/Support/COFF.h" 43 #include "llvm/Support/Debug.h" 44 #include "llvm/Support/ELF.h" 45 #include "llvm/Support/MathExtras.h" 46 #include "llvm/Support/SourceMgr.h" 47 #include "llvm/Support/TargetRegistry.h" 48 #include "llvm/Support/raw_ostream.h" 49 50 using namespace llvm; 51 52 namespace { 53 54 class ARMOperand; 55 56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 57 58 class UnwindContext { 59 MCAsmParser &Parser; 60 61 typedef SmallVector<SMLoc, 4> Locs; 62 63 Locs FnStartLocs; 64 Locs CantUnwindLocs; 65 Locs PersonalityLocs; 66 Locs PersonalityIndexLocs; 67 Locs HandlerDataLocs; 68 int FPReg; 69 70 public: 71 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} 72 73 bool hasFnStart() const { return !FnStartLocs.empty(); } 74 bool cantUnwind() const { return !CantUnwindLocs.empty(); } 75 bool hasHandlerData() const { return !HandlerDataLocs.empty(); } 76 bool hasPersonality() const { 77 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty()); 78 } 79 80 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); } 81 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); } 82 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); } 83 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); } 84 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); } 85 86 void saveFPReg(int Reg) { FPReg = Reg; } 87 int getFPReg() const { return FPReg; } 88 89 void emitFnStartLocNotes() const { 90 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end(); 91 FI != FE; ++FI) 92 Parser.Note(*FI, ".fnstart was specified here"); 93 } 94 void emitCantUnwindLocNotes() const { 95 for (Locs::const_iterator UI = CantUnwindLocs.begin(), 96 UE = CantUnwindLocs.end(); UI != UE; ++UI) 97 Parser.Note(*UI, ".cantunwind was specified here"); 98 } 99 void emitHandlerDataLocNotes() const { 100 for (Locs::const_iterator HI = HandlerDataLocs.begin(), 101 HE = HandlerDataLocs.end(); HI != HE; ++HI) 102 Parser.Note(*HI, ".handlerdata was specified here"); 103 } 104 void emitPersonalityLocNotes() const { 105 for (Locs::const_iterator PI = PersonalityLocs.begin(), 106 PE = PersonalityLocs.end(), 107 PII = PersonalityIndexLocs.begin(), 108 PIE = PersonalityIndexLocs.end(); 109 PI != PE || PII != PIE;) { 110 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer())) 111 Parser.Note(*PI++, ".personality was specified here"); 112 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer())) 113 Parser.Note(*PII++, ".personalityindex was specified here"); 114 else 115 llvm_unreachable(".personality and .personalityindex cannot be " 116 "at the same location"); 117 } 118 } 119 120 void reset() { 121 FnStartLocs = Locs(); 122 CantUnwindLocs = Locs(); 123 PersonalityLocs = Locs(); 124 HandlerDataLocs = Locs(); 125 PersonalityIndexLocs = Locs(); 126 FPReg = ARM::SP; 127 } 128 }; 129 130 class ARMAsmParser : public MCTargetAsmParser { 131 MCSubtargetInfo &STI; 132 MCAsmParser &Parser; 133 const MCInstrInfo &MII; 134 const MCRegisterInfo *MRI; 135 UnwindContext UC; 136 137 ARMTargetStreamer &getTargetStreamer() { 138 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); 139 return static_cast<ARMTargetStreamer &>(TS); 140 } 141 142 // Map of register aliases registers via the .req directive. 143 StringMap<unsigned> RegisterReqs; 144 145 bool NextSymbolIsThumb; 146 147 struct { 148 ARMCC::CondCodes Cond; // Condition for IT block. 149 unsigned Mask:4; // Condition mask for instructions. 150 // Starting at first 1 (from lsb). 151 // '1' condition as indicated in IT. 152 // '0' inverse of condition (else). 153 // Count of instructions in IT block is 154 // 4 - trailingzeroes(mask) 155 156 bool FirstCond; // Explicit flag for when we're parsing the 157 // First instruction in the IT block. It's 158 // implied in the mask, so needs special 159 // handling. 160 161 unsigned CurPosition; // Current position in parsing of IT 162 // block. In range [0,3]. Initialized 163 // according to count of instructions in block. 164 // ~0U if no active IT block. 165 } ITState; 166 bool inITBlock() { return ITState.CurPosition != ~0U;} 167 void forwardITPosition() { 168 if (!inITBlock()) return; 169 // Move to the next instruction in the IT block, if there is one. If not, 170 // mark the block as done. 171 unsigned TZ = countTrailingZeros(ITState.Mask); 172 if (++ITState.CurPosition == 5 - TZ) 173 ITState.CurPosition = ~0U; // Done with the IT block after this. 174 } 175 176 177 MCAsmParser &getParser() const { return Parser; } 178 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 179 180 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) { 181 return Parser.Note(L, Msg, Ranges); 182 } 183 bool Warning(SMLoc L, const Twine &Msg, 184 ArrayRef<SMRange> Ranges = None) { 185 return Parser.Warning(L, Msg, Ranges); 186 } 187 bool Error(SMLoc L, const Twine &Msg, 188 ArrayRef<SMRange> Ranges = None) { 189 return Parser.Error(L, Msg, Ranges); 190 } 191 192 int tryParseRegister(); 193 bool tryParseRegisterWithWriteBack(OperandVector &); 194 int tryParseShiftRegister(OperandVector &); 195 bool parseRegisterList(OperandVector &); 196 bool parseMemory(OperandVector &); 197 bool parseOperand(OperandVector &, StringRef Mnemonic); 198 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 199 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 200 unsigned &ShiftAmount); 201 bool parseLiteralValues(unsigned Size, SMLoc L); 202 bool parseDirectiveThumb(SMLoc L); 203 bool parseDirectiveARM(SMLoc L); 204 bool parseDirectiveThumbFunc(SMLoc L); 205 bool parseDirectiveCode(SMLoc L); 206 bool parseDirectiveSyntax(SMLoc L); 207 bool parseDirectiveReq(StringRef Name, SMLoc L); 208 bool parseDirectiveUnreq(SMLoc L); 209 bool parseDirectiveArch(SMLoc L); 210 bool parseDirectiveEabiAttr(SMLoc L); 211 bool parseDirectiveCPU(SMLoc L); 212 bool parseDirectiveFPU(SMLoc L); 213 bool parseDirectiveFnStart(SMLoc L); 214 bool parseDirectiveFnEnd(SMLoc L); 215 bool parseDirectiveCantUnwind(SMLoc L); 216 bool parseDirectivePersonality(SMLoc L); 217 bool parseDirectiveHandlerData(SMLoc L); 218 bool parseDirectiveSetFP(SMLoc L); 219 bool parseDirectivePad(SMLoc L); 220 bool parseDirectiveRegSave(SMLoc L, bool IsVector); 221 bool parseDirectiveInst(SMLoc L, char Suffix = '\0'); 222 bool parseDirectiveLtorg(SMLoc L); 223 bool parseDirectiveEven(SMLoc L); 224 bool parseDirectivePersonalityIndex(SMLoc L); 225 bool parseDirectiveUnwindRaw(SMLoc L); 226 bool parseDirectiveTLSDescSeq(SMLoc L); 227 bool parseDirectiveMovSP(SMLoc L); 228 bool parseDirectiveObjectArch(SMLoc L); 229 bool parseDirectiveArchExtension(SMLoc L); 230 bool parseDirectiveAlign(SMLoc L); 231 bool parseDirectiveThumbSet(SMLoc L); 232 233 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 234 bool &CarrySetting, unsigned &ProcessorIMod, 235 StringRef &ITMask); 236 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, 237 bool &CanAcceptCarrySet, 238 bool &CanAcceptPredicationCode); 239 240 bool isThumb() const { 241 // FIXME: Can tablegen auto-generate this? 242 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 243 } 244 bool isThumbOne() const { 245 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 246 } 247 bool isThumbTwo() const { 248 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 249 } 250 bool hasThumb() const { 251 return STI.getFeatureBits() & ARM::HasV4TOps; 252 } 253 bool hasV6Ops() const { 254 return STI.getFeatureBits() & ARM::HasV6Ops; 255 } 256 bool hasV6MOps() const { 257 return STI.getFeatureBits() & ARM::HasV6MOps; 258 } 259 bool hasV7Ops() const { 260 return STI.getFeatureBits() & ARM::HasV7Ops; 261 } 262 bool hasV8Ops() const { 263 return STI.getFeatureBits() & ARM::HasV8Ops; 264 } 265 bool hasARM() const { 266 return !(STI.getFeatureBits() & ARM::FeatureNoARM); 267 } 268 269 void SwitchMode() { 270 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 271 setAvailableFeatures(FB); 272 } 273 bool isMClass() const { 274 return STI.getFeatureBits() & ARM::FeatureMClass; 275 } 276 277 /// @name Auto-generated Match Functions 278 /// { 279 280 #define GET_ASSEMBLER_HEADER 281 #include "ARMGenAsmMatcher.inc" 282 283 /// } 284 285 OperandMatchResultTy parseITCondCode(OperandVector &); 286 OperandMatchResultTy parseCoprocNumOperand(OperandVector &); 287 OperandMatchResultTy parseCoprocRegOperand(OperandVector &); 288 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &); 289 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &); 290 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &); 291 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &); 292 OperandMatchResultTy parseMSRMaskOperand(OperandVector &); 293 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low, 294 int High); 295 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) { 296 return parsePKHImm(O, "lsl", 0, 31); 297 } 298 OperandMatchResultTy parsePKHASRImm(OperandVector &O) { 299 return parsePKHImm(O, "asr", 1, 32); 300 } 301 OperandMatchResultTy parseSetEndImm(OperandVector &); 302 OperandMatchResultTy parseShifterImm(OperandVector &); 303 OperandMatchResultTy parseRotImm(OperandVector &); 304 OperandMatchResultTy parseBitfield(OperandVector &); 305 OperandMatchResultTy parsePostIdxReg(OperandVector &); 306 OperandMatchResultTy parseAM3Offset(OperandVector &); 307 OperandMatchResultTy parseFPImm(OperandVector &); 308 OperandMatchResultTy parseVectorList(OperandVector &); 309 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, 310 SMLoc &EndLoc); 311 312 // Asm Match Converter Methods 313 void cvtThumbMultiply(MCInst &Inst, const OperandVector &); 314 void cvtThumbBranches(MCInst &Inst, const OperandVector &); 315 316 bool validateInstruction(MCInst &Inst, const OperandVector &Ops); 317 bool processInstruction(MCInst &Inst, const OperandVector &Ops); 318 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands); 319 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands); 320 321 public: 322 enum ARMMatchResultTy { 323 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 324 Match_RequiresNotITBlock, 325 Match_RequiresV6, 326 Match_RequiresThumb2, 327 #define GET_OPERAND_DIAGNOSTIC_TYPES 328 #include "ARMGenAsmMatcher.inc" 329 330 }; 331 332 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser, 333 const MCInstrInfo &MII, 334 const MCTargetOptions &Options) 335 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) { 336 MCAsmParserExtension::Initialize(_Parser); 337 338 // Cache the MCRegisterInfo. 339 MRI = getContext().getRegisterInfo(); 340 341 // Initialize the set of available features. 342 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 343 344 // Not in an ITBlock to start with. 345 ITState.CurPosition = ~0U; 346 347 NextSymbolIsThumb = false; 348 } 349 350 // Implementation of the MCTargetAsmParser interface: 351 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 352 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 353 SMLoc NameLoc, OperandVector &Operands) override; 354 bool ParseDirective(AsmToken DirectiveID) override; 355 356 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 357 unsigned Kind) override; 358 unsigned checkTargetMatchPredicate(MCInst &Inst) override; 359 360 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 361 OperandVector &Operands, MCStreamer &Out, 362 unsigned &ErrorInfo, 363 bool MatchingInlineAsm) override; 364 void onLabelParsed(MCSymbol *Symbol) override; 365 }; 366 } // end anonymous namespace 367 368 namespace { 369 370 /// ARMOperand - Instances of this class represent a parsed ARM machine 371 /// operand. 372 class ARMOperand : public MCParsedAsmOperand { 373 enum KindTy { 374 k_CondCode, 375 k_CCOut, 376 k_ITCondMask, 377 k_CoprocNum, 378 k_CoprocReg, 379 k_CoprocOption, 380 k_Immediate, 381 k_MemBarrierOpt, 382 k_InstSyncBarrierOpt, 383 k_Memory, 384 k_PostIndexRegister, 385 k_MSRMask, 386 k_ProcIFlags, 387 k_VectorIndex, 388 k_Register, 389 k_RegisterList, 390 k_DPRRegisterList, 391 k_SPRRegisterList, 392 k_VectorList, 393 k_VectorListAllLanes, 394 k_VectorListIndexed, 395 k_ShiftedRegister, 396 k_ShiftedImmediate, 397 k_ShifterImmediate, 398 k_RotateImmediate, 399 k_BitfieldDescriptor, 400 k_Token 401 } Kind; 402 403 SMLoc StartLoc, EndLoc, AlignmentLoc; 404 SmallVector<unsigned, 8> Registers; 405 406 struct CCOp { 407 ARMCC::CondCodes Val; 408 }; 409 410 struct CopOp { 411 unsigned Val; 412 }; 413 414 struct CoprocOptionOp { 415 unsigned Val; 416 }; 417 418 struct ITMaskOp { 419 unsigned Mask:4; 420 }; 421 422 struct MBOptOp { 423 ARM_MB::MemBOpt Val; 424 }; 425 426 struct ISBOptOp { 427 ARM_ISB::InstSyncBOpt Val; 428 }; 429 430 struct IFlagsOp { 431 ARM_PROC::IFlags Val; 432 }; 433 434 struct MMaskOp { 435 unsigned Val; 436 }; 437 438 struct TokOp { 439 const char *Data; 440 unsigned Length; 441 }; 442 443 struct RegOp { 444 unsigned RegNum; 445 }; 446 447 // A vector register list is a sequential list of 1 to 4 registers. 448 struct VectorListOp { 449 unsigned RegNum; 450 unsigned Count; 451 unsigned LaneIndex; 452 bool isDoubleSpaced; 453 }; 454 455 struct VectorIndexOp { 456 unsigned Val; 457 }; 458 459 struct ImmOp { 460 const MCExpr *Val; 461 }; 462 463 /// Combined record for all forms of ARM address expressions. 464 struct MemoryOp { 465 unsigned BaseRegNum; 466 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 467 // was specified. 468 const MCConstantExpr *OffsetImm; // Offset immediate value 469 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 470 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 471 unsigned ShiftImm; // shift for OffsetReg. 472 unsigned Alignment; // 0 = no alignment specified 473 // n = alignment in bytes (2, 4, 8, 16, or 32) 474 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 475 }; 476 477 struct PostIdxRegOp { 478 unsigned RegNum; 479 bool isAdd; 480 ARM_AM::ShiftOpc ShiftTy; 481 unsigned ShiftImm; 482 }; 483 484 struct ShifterImmOp { 485 bool isASR; 486 unsigned Imm; 487 }; 488 489 struct RegShiftedRegOp { 490 ARM_AM::ShiftOpc ShiftTy; 491 unsigned SrcReg; 492 unsigned ShiftReg; 493 unsigned ShiftImm; 494 }; 495 496 struct RegShiftedImmOp { 497 ARM_AM::ShiftOpc ShiftTy; 498 unsigned SrcReg; 499 unsigned ShiftImm; 500 }; 501 502 struct RotImmOp { 503 unsigned Imm; 504 }; 505 506 struct BitfieldOp { 507 unsigned LSB; 508 unsigned Width; 509 }; 510 511 union { 512 struct CCOp CC; 513 struct CopOp Cop; 514 struct CoprocOptionOp CoprocOption; 515 struct MBOptOp MBOpt; 516 struct ISBOptOp ISBOpt; 517 struct ITMaskOp ITMask; 518 struct IFlagsOp IFlags; 519 struct MMaskOp MMask; 520 struct TokOp Tok; 521 struct RegOp Reg; 522 struct VectorListOp VectorList; 523 struct VectorIndexOp VectorIndex; 524 struct ImmOp Imm; 525 struct MemoryOp Memory; 526 struct PostIdxRegOp PostIdxReg; 527 struct ShifterImmOp ShifterImm; 528 struct RegShiftedRegOp RegShiftedReg; 529 struct RegShiftedImmOp RegShiftedImm; 530 struct RotImmOp RotImm; 531 struct BitfieldOp Bitfield; 532 }; 533 534 public: 535 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 536 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 537 Kind = o.Kind; 538 StartLoc = o.StartLoc; 539 EndLoc = o.EndLoc; 540 switch (Kind) { 541 case k_CondCode: 542 CC = o.CC; 543 break; 544 case k_ITCondMask: 545 ITMask = o.ITMask; 546 break; 547 case k_Token: 548 Tok = o.Tok; 549 break; 550 case k_CCOut: 551 case k_Register: 552 Reg = o.Reg; 553 break; 554 case k_RegisterList: 555 case k_DPRRegisterList: 556 case k_SPRRegisterList: 557 Registers = o.Registers; 558 break; 559 case k_VectorList: 560 case k_VectorListAllLanes: 561 case k_VectorListIndexed: 562 VectorList = o.VectorList; 563 break; 564 case k_CoprocNum: 565 case k_CoprocReg: 566 Cop = o.Cop; 567 break; 568 case k_CoprocOption: 569 CoprocOption = o.CoprocOption; 570 break; 571 case k_Immediate: 572 Imm = o.Imm; 573 break; 574 case k_MemBarrierOpt: 575 MBOpt = o.MBOpt; 576 break; 577 case k_InstSyncBarrierOpt: 578 ISBOpt = o.ISBOpt; 579 case k_Memory: 580 Memory = o.Memory; 581 break; 582 case k_PostIndexRegister: 583 PostIdxReg = o.PostIdxReg; 584 break; 585 case k_MSRMask: 586 MMask = o.MMask; 587 break; 588 case k_ProcIFlags: 589 IFlags = o.IFlags; 590 break; 591 case k_ShifterImmediate: 592 ShifterImm = o.ShifterImm; 593 break; 594 case k_ShiftedRegister: 595 RegShiftedReg = o.RegShiftedReg; 596 break; 597 case k_ShiftedImmediate: 598 RegShiftedImm = o.RegShiftedImm; 599 break; 600 case k_RotateImmediate: 601 RotImm = o.RotImm; 602 break; 603 case k_BitfieldDescriptor: 604 Bitfield = o.Bitfield; 605 break; 606 case k_VectorIndex: 607 VectorIndex = o.VectorIndex; 608 break; 609 } 610 } 611 612 /// getStartLoc - Get the location of the first token of this operand. 613 SMLoc getStartLoc() const override { return StartLoc; } 614 /// getEndLoc - Get the location of the last token of this operand. 615 SMLoc getEndLoc() const override { return EndLoc; } 616 /// getLocRange - Get the range between the first and last token of this 617 /// operand. 618 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 619 620 /// getAlignmentLoc - Get the location of the Alignment token of this operand. 621 SMLoc getAlignmentLoc() const { 622 assert(Kind == k_Memory && "Invalid access!"); 623 return AlignmentLoc; 624 } 625 626 ARMCC::CondCodes getCondCode() const { 627 assert(Kind == k_CondCode && "Invalid access!"); 628 return CC.Val; 629 } 630 631 unsigned getCoproc() const { 632 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 633 return Cop.Val; 634 } 635 636 StringRef getToken() const { 637 assert(Kind == k_Token && "Invalid access!"); 638 return StringRef(Tok.Data, Tok.Length); 639 } 640 641 unsigned getReg() const override { 642 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 643 return Reg.RegNum; 644 } 645 646 const SmallVectorImpl<unsigned> &getRegList() const { 647 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 648 Kind == k_SPRRegisterList) && "Invalid access!"); 649 return Registers; 650 } 651 652 const MCExpr *getImm() const { 653 assert(isImm() && "Invalid access!"); 654 return Imm.Val; 655 } 656 657 unsigned getVectorIndex() const { 658 assert(Kind == k_VectorIndex && "Invalid access!"); 659 return VectorIndex.Val; 660 } 661 662 ARM_MB::MemBOpt getMemBarrierOpt() const { 663 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 664 return MBOpt.Val; 665 } 666 667 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { 668 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!"); 669 return ISBOpt.Val; 670 } 671 672 ARM_PROC::IFlags getProcIFlags() const { 673 assert(Kind == k_ProcIFlags && "Invalid access!"); 674 return IFlags.Val; 675 } 676 677 unsigned getMSRMask() const { 678 assert(Kind == k_MSRMask && "Invalid access!"); 679 return MMask.Val; 680 } 681 682 bool isCoprocNum() const { return Kind == k_CoprocNum; } 683 bool isCoprocReg() const { return Kind == k_CoprocReg; } 684 bool isCoprocOption() const { return Kind == k_CoprocOption; } 685 bool isCondCode() const { return Kind == k_CondCode; } 686 bool isCCOut() const { return Kind == k_CCOut; } 687 bool isITMask() const { return Kind == k_ITCondMask; } 688 bool isITCondCode() const { return Kind == k_CondCode; } 689 bool isImm() const override { return Kind == k_Immediate; } 690 // checks whether this operand is an unsigned offset which fits is a field 691 // of specified width and scaled by a specific number of bits 692 template<unsigned width, unsigned scale> 693 bool isUnsignedOffset() const { 694 if (!isImm()) return false; 695 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 696 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 697 int64_t Val = CE->getValue(); 698 int64_t Align = 1LL << scale; 699 int64_t Max = Align * ((1LL << width) - 1); 700 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max); 701 } 702 return false; 703 } 704 // checks whether this operand is an signed offset which fits is a field 705 // of specified width and scaled by a specific number of bits 706 template<unsigned width, unsigned scale> 707 bool isSignedOffset() const { 708 if (!isImm()) return false; 709 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 710 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 711 int64_t Val = CE->getValue(); 712 int64_t Align = 1LL << scale; 713 int64_t Max = Align * ((1LL << (width-1)) - 1); 714 int64_t Min = -Align * (1LL << (width-1)); 715 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max); 716 } 717 return false; 718 } 719 720 // checks whether this operand is a memory operand computed as an offset 721 // applied to PC. the offset may have 8 bits of magnitude and is represented 722 // with two bits of shift. textually it may be either [pc, #imm], #imm or 723 // relocable expression... 724 bool isThumbMemPC() const { 725 int64_t Val = 0; 726 if (isImm()) { 727 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 728 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val); 729 if (!CE) return false; 730 Val = CE->getValue(); 731 } 732 else if (isMem()) { 733 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; 734 if(Memory.BaseRegNum != ARM::PC) return false; 735 Val = Memory.OffsetImm->getValue(); 736 } 737 else return false; 738 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020); 739 } 740 bool isFPImm() const { 741 if (!isImm()) return false; 742 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 743 if (!CE) return false; 744 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 745 return Val != -1; 746 } 747 bool isFBits16() const { 748 if (!isImm()) return false; 749 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 750 if (!CE) return false; 751 int64_t Value = CE->getValue(); 752 return Value >= 0 && Value <= 16; 753 } 754 bool isFBits32() const { 755 if (!isImm()) return false; 756 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 757 if (!CE) return false; 758 int64_t Value = CE->getValue(); 759 return Value >= 1 && Value <= 32; 760 } 761 bool isImm8s4() const { 762 if (!isImm()) return false; 763 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 764 if (!CE) return false; 765 int64_t Value = CE->getValue(); 766 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 767 } 768 bool isImm0_1020s4() const { 769 if (!isImm()) return false; 770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 771 if (!CE) return false; 772 int64_t Value = CE->getValue(); 773 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 774 } 775 bool isImm0_508s4() const { 776 if (!isImm()) return false; 777 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 778 if (!CE) return false; 779 int64_t Value = CE->getValue(); 780 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 781 } 782 bool isImm0_508s4Neg() const { 783 if (!isImm()) return false; 784 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 785 if (!CE) return false; 786 int64_t Value = -CE->getValue(); 787 // explicitly exclude zero. we want that to use the normal 0_508 version. 788 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 789 } 790 bool isImm0_239() const { 791 if (!isImm()) return false; 792 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 793 if (!CE) return false; 794 int64_t Value = CE->getValue(); 795 return Value >= 0 && Value < 240; 796 } 797 bool isImm0_255() const { 798 if (!isImm()) return false; 799 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 800 if (!CE) return false; 801 int64_t Value = CE->getValue(); 802 return Value >= 0 && Value < 256; 803 } 804 bool isImm0_4095() const { 805 if (!isImm()) return false; 806 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 807 if (!CE) return false; 808 int64_t Value = CE->getValue(); 809 return Value >= 0 && Value < 4096; 810 } 811 bool isImm0_4095Neg() const { 812 if (!isImm()) return false; 813 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 814 if (!CE) return false; 815 int64_t Value = -CE->getValue(); 816 return Value > 0 && Value < 4096; 817 } 818 bool isImm0_1() const { 819 if (!isImm()) return false; 820 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 821 if (!CE) return false; 822 int64_t Value = CE->getValue(); 823 return Value >= 0 && Value < 2; 824 } 825 bool isImm0_3() const { 826 if (!isImm()) return false; 827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 828 if (!CE) return false; 829 int64_t Value = CE->getValue(); 830 return Value >= 0 && Value < 4; 831 } 832 bool isImm0_7() const { 833 if (!isImm()) return false; 834 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 835 if (!CE) return false; 836 int64_t Value = CE->getValue(); 837 return Value >= 0 && Value < 8; 838 } 839 bool isImm0_15() const { 840 if (!isImm()) return false; 841 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 842 if (!CE) return false; 843 int64_t Value = CE->getValue(); 844 return Value >= 0 && Value < 16; 845 } 846 bool isImm0_31() const { 847 if (!isImm()) return false; 848 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 849 if (!CE) return false; 850 int64_t Value = CE->getValue(); 851 return Value >= 0 && Value < 32; 852 } 853 bool isImm0_63() const { 854 if (!isImm()) return false; 855 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 856 if (!CE) return false; 857 int64_t Value = CE->getValue(); 858 return Value >= 0 && Value < 64; 859 } 860 bool isImm8() const { 861 if (!isImm()) return false; 862 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 863 if (!CE) return false; 864 int64_t Value = CE->getValue(); 865 return Value == 8; 866 } 867 bool isImm16() const { 868 if (!isImm()) return false; 869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 870 if (!CE) return false; 871 int64_t Value = CE->getValue(); 872 return Value == 16; 873 } 874 bool isImm32() const { 875 if (!isImm()) return false; 876 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 877 if (!CE) return false; 878 int64_t Value = CE->getValue(); 879 return Value == 32; 880 } 881 bool isShrImm8() const { 882 if (!isImm()) return false; 883 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 884 if (!CE) return false; 885 int64_t Value = CE->getValue(); 886 return Value > 0 && Value <= 8; 887 } 888 bool isShrImm16() const { 889 if (!isImm()) return false; 890 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 891 if (!CE) return false; 892 int64_t Value = CE->getValue(); 893 return Value > 0 && Value <= 16; 894 } 895 bool isShrImm32() const { 896 if (!isImm()) return false; 897 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 898 if (!CE) return false; 899 int64_t Value = CE->getValue(); 900 return Value > 0 && Value <= 32; 901 } 902 bool isShrImm64() const { 903 if (!isImm()) return false; 904 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 905 if (!CE) return false; 906 int64_t Value = CE->getValue(); 907 return Value > 0 && Value <= 64; 908 } 909 bool isImm1_7() const { 910 if (!isImm()) return false; 911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 912 if (!CE) return false; 913 int64_t Value = CE->getValue(); 914 return Value > 0 && Value < 8; 915 } 916 bool isImm1_15() const { 917 if (!isImm()) return false; 918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 919 if (!CE) return false; 920 int64_t Value = CE->getValue(); 921 return Value > 0 && Value < 16; 922 } 923 bool isImm1_31() const { 924 if (!isImm()) return false; 925 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 926 if (!CE) return false; 927 int64_t Value = CE->getValue(); 928 return Value > 0 && Value < 32; 929 } 930 bool isImm1_16() const { 931 if (!isImm()) return false; 932 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 933 if (!CE) return false; 934 int64_t Value = CE->getValue(); 935 return Value > 0 && Value < 17; 936 } 937 bool isImm1_32() const { 938 if (!isImm()) return false; 939 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 940 if (!CE) return false; 941 int64_t Value = CE->getValue(); 942 return Value > 0 && Value < 33; 943 } 944 bool isImm0_32() const { 945 if (!isImm()) return false; 946 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 947 if (!CE) return false; 948 int64_t Value = CE->getValue(); 949 return Value >= 0 && Value < 33; 950 } 951 bool isImm0_65535() const { 952 if (!isImm()) return false; 953 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 954 if (!CE) return false; 955 int64_t Value = CE->getValue(); 956 return Value >= 0 && Value < 65536; 957 } 958 bool isImm256_65535Expr() const { 959 if (!isImm()) return false; 960 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 961 // If it's not a constant expression, it'll generate a fixup and be 962 // handled later. 963 if (!CE) return true; 964 int64_t Value = CE->getValue(); 965 return Value >= 256 && Value < 65536; 966 } 967 bool isImm0_65535Expr() const { 968 if (!isImm()) return false; 969 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 970 // If it's not a constant expression, it'll generate a fixup and be 971 // handled later. 972 if (!CE) return true; 973 int64_t Value = CE->getValue(); 974 return Value >= 0 && Value < 65536; 975 } 976 bool isImm24bit() const { 977 if (!isImm()) return false; 978 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 979 if (!CE) return false; 980 int64_t Value = CE->getValue(); 981 return Value >= 0 && Value <= 0xffffff; 982 } 983 bool isImmThumbSR() const { 984 if (!isImm()) return false; 985 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 986 if (!CE) return false; 987 int64_t Value = CE->getValue(); 988 return Value > 0 && Value < 33; 989 } 990 bool isPKHLSLImm() const { 991 if (!isImm()) return false; 992 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 993 if (!CE) return false; 994 int64_t Value = CE->getValue(); 995 return Value >= 0 && Value < 32; 996 } 997 bool isPKHASRImm() const { 998 if (!isImm()) return false; 999 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1000 if (!CE) return false; 1001 int64_t Value = CE->getValue(); 1002 return Value > 0 && Value <= 32; 1003 } 1004 bool isAdrLabel() const { 1005 // If we have an immediate that's not a constant, treat it as a label 1006 // reference needing a fixup. If it is a constant, but it can't fit 1007 // into shift immediate encoding, we reject it. 1008 if (isImm() && !isa<MCConstantExpr>(getImm())) return true; 1009 else return (isARMSOImm() || isARMSOImmNeg()); 1010 } 1011 bool isARMSOImm() const { 1012 if (!isImm()) return false; 1013 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1014 if (!CE) return false; 1015 int64_t Value = CE->getValue(); 1016 return ARM_AM::getSOImmVal(Value) != -1; 1017 } 1018 bool isARMSOImmNot() const { 1019 if (!isImm()) return false; 1020 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1021 if (!CE) return false; 1022 int64_t Value = CE->getValue(); 1023 return ARM_AM::getSOImmVal(~Value) != -1; 1024 } 1025 bool isARMSOImmNeg() const { 1026 if (!isImm()) return false; 1027 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1028 if (!CE) return false; 1029 int64_t Value = CE->getValue(); 1030 // Only use this when not representable as a plain so_imm. 1031 return ARM_AM::getSOImmVal(Value) == -1 && 1032 ARM_AM::getSOImmVal(-Value) != -1; 1033 } 1034 bool isT2SOImm() const { 1035 if (!isImm()) return false; 1036 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1037 if (!CE) return false; 1038 int64_t Value = CE->getValue(); 1039 return ARM_AM::getT2SOImmVal(Value) != -1; 1040 } 1041 bool isT2SOImmNot() const { 1042 if (!isImm()) return false; 1043 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1044 if (!CE) return false; 1045 int64_t Value = CE->getValue(); 1046 return ARM_AM::getT2SOImmVal(Value) == -1 && 1047 ARM_AM::getT2SOImmVal(~Value) != -1; 1048 } 1049 bool isT2SOImmNeg() const { 1050 if (!isImm()) return false; 1051 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1052 if (!CE) return false; 1053 int64_t Value = CE->getValue(); 1054 // Only use this when not representable as a plain so_imm. 1055 return ARM_AM::getT2SOImmVal(Value) == -1 && 1056 ARM_AM::getT2SOImmVal(-Value) != -1; 1057 } 1058 bool isSetEndImm() const { 1059 if (!isImm()) return false; 1060 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1061 if (!CE) return false; 1062 int64_t Value = CE->getValue(); 1063 return Value == 1 || Value == 0; 1064 } 1065 bool isReg() const override { return Kind == k_Register; } 1066 bool isRegList() const { return Kind == k_RegisterList; } 1067 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 1068 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 1069 bool isToken() const override { return Kind == k_Token; } 1070 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 1071 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } 1072 bool isMem() const override { return Kind == k_Memory; } 1073 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 1074 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 1075 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 1076 bool isRotImm() const { return Kind == k_RotateImmediate; } 1077 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 1078 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 1079 bool isPostIdxReg() const { 1080 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 1081 } 1082 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const { 1083 if (!isMem()) 1084 return false; 1085 // No offset of any kind. 1086 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && 1087 (alignOK || Memory.Alignment == Alignment); 1088 } 1089 bool isMemPCRelImm12() const { 1090 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1091 return false; 1092 // Base register must be PC. 1093 if (Memory.BaseRegNum != ARM::PC) 1094 return false; 1095 // Immediate offset in range [-4095, 4095]. 1096 if (!Memory.OffsetImm) return true; 1097 int64_t Val = Memory.OffsetImm->getValue(); 1098 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1099 } 1100 bool isAlignedMemory() const { 1101 return isMemNoOffset(true); 1102 } 1103 bool isAlignedMemoryNone() const { 1104 return isMemNoOffset(false, 0); 1105 } 1106 bool isDupAlignedMemoryNone() const { 1107 return isMemNoOffset(false, 0); 1108 } 1109 bool isAlignedMemory16() const { 1110 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. 1111 return true; 1112 return isMemNoOffset(false, 0); 1113 } 1114 bool isDupAlignedMemory16() const { 1115 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. 1116 return true; 1117 return isMemNoOffset(false, 0); 1118 } 1119 bool isAlignedMemory32() const { 1120 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. 1121 return true; 1122 return isMemNoOffset(false, 0); 1123 } 1124 bool isDupAlignedMemory32() const { 1125 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. 1126 return true; 1127 return isMemNoOffset(false, 0); 1128 } 1129 bool isAlignedMemory64() const { 1130 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1131 return true; 1132 return isMemNoOffset(false, 0); 1133 } 1134 bool isDupAlignedMemory64() const { 1135 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1136 return true; 1137 return isMemNoOffset(false, 0); 1138 } 1139 bool isAlignedMemory64or128() const { 1140 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1141 return true; 1142 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1143 return true; 1144 return isMemNoOffset(false, 0); 1145 } 1146 bool isDupAlignedMemory64or128() const { 1147 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1148 return true; 1149 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1150 return true; 1151 return isMemNoOffset(false, 0); 1152 } 1153 bool isAlignedMemory64or128or256() const { 1154 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1155 return true; 1156 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1157 return true; 1158 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32. 1159 return true; 1160 return isMemNoOffset(false, 0); 1161 } 1162 bool isAddrMode2() const { 1163 if (!isMem() || Memory.Alignment != 0) return false; 1164 // Check for register offset. 1165 if (Memory.OffsetRegNum) return true; 1166 // Immediate offset in range [-4095, 4095]. 1167 if (!Memory.OffsetImm) return true; 1168 int64_t Val = Memory.OffsetImm->getValue(); 1169 return Val > -4096 && Val < 4096; 1170 } 1171 bool isAM2OffsetImm() const { 1172 if (!isImm()) return false; 1173 // Immediate offset in range [-4095, 4095]. 1174 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1175 if (!CE) return false; 1176 int64_t Val = CE->getValue(); 1177 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096); 1178 } 1179 bool isAddrMode3() const { 1180 // If we have an immediate that's not a constant, treat it as a label 1181 // reference needing a fixup. If it is a constant, it's something else 1182 // and we reject it. 1183 if (isImm() && !isa<MCConstantExpr>(getImm())) 1184 return true; 1185 if (!isMem() || Memory.Alignment != 0) return false; 1186 // No shifts are legal for AM3. 1187 if (Memory.ShiftType != ARM_AM::no_shift) return false; 1188 // Check for register offset. 1189 if (Memory.OffsetRegNum) return true; 1190 // Immediate offset in range [-255, 255]. 1191 if (!Memory.OffsetImm) return true; 1192 int64_t Val = Memory.OffsetImm->getValue(); 1193 // The #-0 offset is encoded as INT32_MIN, and we have to check 1194 // for this too. 1195 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1196 } 1197 bool isAM3Offset() const { 1198 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 1199 return false; 1200 if (Kind == k_PostIndexRegister) 1201 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 1202 // Immediate offset in range [-255, 255]. 1203 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1204 if (!CE) return false; 1205 int64_t Val = CE->getValue(); 1206 // Special case, #-0 is INT32_MIN. 1207 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1208 } 1209 bool isAddrMode5() const { 1210 // If we have an immediate that's not a constant, treat it as a label 1211 // reference needing a fixup. If it is a constant, it's something else 1212 // and we reject it. 1213 if (isImm() && !isa<MCConstantExpr>(getImm())) 1214 return true; 1215 if (!isMem() || Memory.Alignment != 0) return false; 1216 // Check for register offset. 1217 if (Memory.OffsetRegNum) return false; 1218 // Immediate offset in range [-1020, 1020] and a multiple of 4. 1219 if (!Memory.OffsetImm) return true; 1220 int64_t Val = Memory.OffsetImm->getValue(); 1221 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 1222 Val == INT32_MIN; 1223 } 1224 bool isMemTBB() const { 1225 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1226 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1227 return false; 1228 return true; 1229 } 1230 bool isMemTBH() const { 1231 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1232 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 1233 Memory.Alignment != 0 ) 1234 return false; 1235 return true; 1236 } 1237 bool isMemRegOffset() const { 1238 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) 1239 return false; 1240 return true; 1241 } 1242 bool isT2MemRegOffset() const { 1243 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1244 Memory.Alignment != 0) 1245 return false; 1246 // Only lsl #{0, 1, 2, 3} allowed. 1247 if (Memory.ShiftType == ARM_AM::no_shift) 1248 return true; 1249 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 1250 return false; 1251 return true; 1252 } 1253 bool isMemThumbRR() const { 1254 // Thumb reg+reg addressing is simple. Just two registers, a base and 1255 // an offset. No shifts, negations or any other complicating factors. 1256 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1257 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1258 return false; 1259 return isARMLowRegister(Memory.BaseRegNum) && 1260 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 1261 } 1262 bool isMemThumbRIs4() const { 1263 if (!isMem() || Memory.OffsetRegNum != 0 || 1264 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1265 return false; 1266 // Immediate offset, multiple of 4 in range [0, 124]. 1267 if (!Memory.OffsetImm) return true; 1268 int64_t Val = Memory.OffsetImm->getValue(); 1269 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 1270 } 1271 bool isMemThumbRIs2() const { 1272 if (!isMem() || Memory.OffsetRegNum != 0 || 1273 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1274 return false; 1275 // Immediate offset, multiple of 4 in range [0, 62]. 1276 if (!Memory.OffsetImm) return true; 1277 int64_t Val = Memory.OffsetImm->getValue(); 1278 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1279 } 1280 bool isMemThumbRIs1() const { 1281 if (!isMem() || Memory.OffsetRegNum != 0 || 1282 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1283 return false; 1284 // Immediate offset in range [0, 31]. 1285 if (!Memory.OffsetImm) return true; 1286 int64_t Val = Memory.OffsetImm->getValue(); 1287 return Val >= 0 && Val <= 31; 1288 } 1289 bool isMemThumbSPI() const { 1290 if (!isMem() || Memory.OffsetRegNum != 0 || 1291 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1292 return false; 1293 // Immediate offset, multiple of 4 in range [0, 1020]. 1294 if (!Memory.OffsetImm) return true; 1295 int64_t Val = Memory.OffsetImm->getValue(); 1296 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1297 } 1298 bool isMemImm8s4Offset() const { 1299 // If we have an immediate that's not a constant, treat it as a label 1300 // reference needing a fixup. If it is a constant, it's something else 1301 // and we reject it. 1302 if (isImm() && !isa<MCConstantExpr>(getImm())) 1303 return true; 1304 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1305 return false; 1306 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1307 if (!Memory.OffsetImm) return true; 1308 int64_t Val = Memory.OffsetImm->getValue(); 1309 // Special case, #-0 is INT32_MIN. 1310 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; 1311 } 1312 bool isMemImm0_1020s4Offset() const { 1313 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1314 return false; 1315 // Immediate offset a multiple of 4 in range [0, 1020]. 1316 if (!Memory.OffsetImm) return true; 1317 int64_t Val = Memory.OffsetImm->getValue(); 1318 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1319 } 1320 bool isMemImm8Offset() const { 1321 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1322 return false; 1323 // Base reg of PC isn't allowed for these encodings. 1324 if (Memory.BaseRegNum == ARM::PC) return false; 1325 // Immediate offset in range [-255, 255]. 1326 if (!Memory.OffsetImm) return true; 1327 int64_t Val = Memory.OffsetImm->getValue(); 1328 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1329 } 1330 bool isMemPosImm8Offset() const { 1331 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1332 return false; 1333 // Immediate offset in range [0, 255]. 1334 if (!Memory.OffsetImm) return true; 1335 int64_t Val = Memory.OffsetImm->getValue(); 1336 return Val >= 0 && Val < 256; 1337 } 1338 bool isMemNegImm8Offset() const { 1339 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1340 return false; 1341 // Base reg of PC isn't allowed for these encodings. 1342 if (Memory.BaseRegNum == ARM::PC) return false; 1343 // Immediate offset in range [-255, -1]. 1344 if (!Memory.OffsetImm) return false; 1345 int64_t Val = Memory.OffsetImm->getValue(); 1346 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1347 } 1348 bool isMemUImm12Offset() const { 1349 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1350 return false; 1351 // Immediate offset in range [0, 4095]. 1352 if (!Memory.OffsetImm) return true; 1353 int64_t Val = Memory.OffsetImm->getValue(); 1354 return (Val >= 0 && Val < 4096); 1355 } 1356 bool isMemImm12Offset() const { 1357 // If we have an immediate that's not a constant, treat it as a label 1358 // reference needing a fixup. If it is a constant, it's something else 1359 // and we reject it. 1360 if (isImm() && !isa<MCConstantExpr>(getImm())) 1361 return true; 1362 1363 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1364 return false; 1365 // Immediate offset in range [-4095, 4095]. 1366 if (!Memory.OffsetImm) return true; 1367 int64_t Val = Memory.OffsetImm->getValue(); 1368 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1369 } 1370 bool isPostIdxImm8() const { 1371 if (!isImm()) return false; 1372 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1373 if (!CE) return false; 1374 int64_t Val = CE->getValue(); 1375 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1376 } 1377 bool isPostIdxImm8s4() const { 1378 if (!isImm()) return false; 1379 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1380 if (!CE) return false; 1381 int64_t Val = CE->getValue(); 1382 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1383 (Val == INT32_MIN); 1384 } 1385 1386 bool isMSRMask() const { return Kind == k_MSRMask; } 1387 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1388 1389 // NEON operands. 1390 bool isSingleSpacedVectorList() const { 1391 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1392 } 1393 bool isDoubleSpacedVectorList() const { 1394 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1395 } 1396 bool isVecListOneD() const { 1397 if (!isSingleSpacedVectorList()) return false; 1398 return VectorList.Count == 1; 1399 } 1400 1401 bool isVecListDPair() const { 1402 if (!isSingleSpacedVectorList()) return false; 1403 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1404 .contains(VectorList.RegNum)); 1405 } 1406 1407 bool isVecListThreeD() const { 1408 if (!isSingleSpacedVectorList()) return false; 1409 return VectorList.Count == 3; 1410 } 1411 1412 bool isVecListFourD() const { 1413 if (!isSingleSpacedVectorList()) return false; 1414 return VectorList.Count == 4; 1415 } 1416 1417 bool isVecListDPairSpaced() const { 1418 if (Kind != k_VectorList) return false; 1419 if (isSingleSpacedVectorList()) return false; 1420 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1421 .contains(VectorList.RegNum)); 1422 } 1423 1424 bool isVecListThreeQ() const { 1425 if (!isDoubleSpacedVectorList()) return false; 1426 return VectorList.Count == 3; 1427 } 1428 1429 bool isVecListFourQ() const { 1430 if (!isDoubleSpacedVectorList()) return false; 1431 return VectorList.Count == 4; 1432 } 1433 1434 bool isSingleSpacedVectorAllLanes() const { 1435 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1436 } 1437 bool isDoubleSpacedVectorAllLanes() const { 1438 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1439 } 1440 bool isVecListOneDAllLanes() const { 1441 if (!isSingleSpacedVectorAllLanes()) return false; 1442 return VectorList.Count == 1; 1443 } 1444 1445 bool isVecListDPairAllLanes() const { 1446 if (!isSingleSpacedVectorAllLanes()) return false; 1447 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1448 .contains(VectorList.RegNum)); 1449 } 1450 1451 bool isVecListDPairSpacedAllLanes() const { 1452 if (!isDoubleSpacedVectorAllLanes()) return false; 1453 return VectorList.Count == 2; 1454 } 1455 1456 bool isVecListThreeDAllLanes() const { 1457 if (!isSingleSpacedVectorAllLanes()) return false; 1458 return VectorList.Count == 3; 1459 } 1460 1461 bool isVecListThreeQAllLanes() const { 1462 if (!isDoubleSpacedVectorAllLanes()) return false; 1463 return VectorList.Count == 3; 1464 } 1465 1466 bool isVecListFourDAllLanes() const { 1467 if (!isSingleSpacedVectorAllLanes()) return false; 1468 return VectorList.Count == 4; 1469 } 1470 1471 bool isVecListFourQAllLanes() const { 1472 if (!isDoubleSpacedVectorAllLanes()) return false; 1473 return VectorList.Count == 4; 1474 } 1475 1476 bool isSingleSpacedVectorIndexed() const { 1477 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1478 } 1479 bool isDoubleSpacedVectorIndexed() const { 1480 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1481 } 1482 bool isVecListOneDByteIndexed() const { 1483 if (!isSingleSpacedVectorIndexed()) return false; 1484 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1485 } 1486 1487 bool isVecListOneDHWordIndexed() const { 1488 if (!isSingleSpacedVectorIndexed()) return false; 1489 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1490 } 1491 1492 bool isVecListOneDWordIndexed() const { 1493 if (!isSingleSpacedVectorIndexed()) return false; 1494 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1495 } 1496 1497 bool isVecListTwoDByteIndexed() const { 1498 if (!isSingleSpacedVectorIndexed()) return false; 1499 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1500 } 1501 1502 bool isVecListTwoDHWordIndexed() const { 1503 if (!isSingleSpacedVectorIndexed()) return false; 1504 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1505 } 1506 1507 bool isVecListTwoQWordIndexed() const { 1508 if (!isDoubleSpacedVectorIndexed()) return false; 1509 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1510 } 1511 1512 bool isVecListTwoQHWordIndexed() const { 1513 if (!isDoubleSpacedVectorIndexed()) return false; 1514 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1515 } 1516 1517 bool isVecListTwoDWordIndexed() const { 1518 if (!isSingleSpacedVectorIndexed()) return false; 1519 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1520 } 1521 1522 bool isVecListThreeDByteIndexed() const { 1523 if (!isSingleSpacedVectorIndexed()) return false; 1524 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1525 } 1526 1527 bool isVecListThreeDHWordIndexed() const { 1528 if (!isSingleSpacedVectorIndexed()) return false; 1529 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1530 } 1531 1532 bool isVecListThreeQWordIndexed() const { 1533 if (!isDoubleSpacedVectorIndexed()) return false; 1534 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1535 } 1536 1537 bool isVecListThreeQHWordIndexed() const { 1538 if (!isDoubleSpacedVectorIndexed()) return false; 1539 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1540 } 1541 1542 bool isVecListThreeDWordIndexed() const { 1543 if (!isSingleSpacedVectorIndexed()) return false; 1544 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1545 } 1546 1547 bool isVecListFourDByteIndexed() const { 1548 if (!isSingleSpacedVectorIndexed()) return false; 1549 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1550 } 1551 1552 bool isVecListFourDHWordIndexed() const { 1553 if (!isSingleSpacedVectorIndexed()) return false; 1554 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1555 } 1556 1557 bool isVecListFourQWordIndexed() const { 1558 if (!isDoubleSpacedVectorIndexed()) return false; 1559 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1560 } 1561 1562 bool isVecListFourQHWordIndexed() const { 1563 if (!isDoubleSpacedVectorIndexed()) return false; 1564 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1565 } 1566 1567 bool isVecListFourDWordIndexed() const { 1568 if (!isSingleSpacedVectorIndexed()) return false; 1569 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1570 } 1571 1572 bool isVectorIndex8() const { 1573 if (Kind != k_VectorIndex) return false; 1574 return VectorIndex.Val < 8; 1575 } 1576 bool isVectorIndex16() const { 1577 if (Kind != k_VectorIndex) return false; 1578 return VectorIndex.Val < 4; 1579 } 1580 bool isVectorIndex32() const { 1581 if (Kind != k_VectorIndex) return false; 1582 return VectorIndex.Val < 2; 1583 } 1584 1585 bool isNEONi8splat() const { 1586 if (!isImm()) return false; 1587 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1588 // Must be a constant. 1589 if (!CE) return false; 1590 int64_t Value = CE->getValue(); 1591 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1592 // value. 1593 return Value >= 0 && Value < 256; 1594 } 1595 1596 bool isNEONi16splat() const { 1597 if (isNEONByteReplicate(2)) 1598 return false; // Leave that for bytes replication and forbid by default. 1599 if (!isImm()) 1600 return false; 1601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1602 // Must be a constant. 1603 if (!CE) return false; 1604 int64_t Value = CE->getValue(); 1605 // i16 value in the range [0,255] or [0x0100, 0xff00] 1606 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1607 } 1608 1609 bool isNEONi32splat() const { 1610 if (isNEONByteReplicate(4)) 1611 return false; // Leave that for bytes replication and forbid by default. 1612 if (!isImm()) 1613 return false; 1614 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1615 // Must be a constant. 1616 if (!CE) return false; 1617 int64_t Value = CE->getValue(); 1618 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 1619 return (Value >= 0 && Value < 256) || 1620 (Value >= 0x0100 && Value <= 0xff00) || 1621 (Value >= 0x010000 && Value <= 0xff0000) || 1622 (Value >= 0x01000000 && Value <= 0xff000000); 1623 } 1624 1625 bool isNEONByteReplicate(unsigned NumBytes) const { 1626 if (!isImm()) 1627 return false; 1628 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1629 // Must be a constant. 1630 if (!CE) 1631 return false; 1632 int64_t Value = CE->getValue(); 1633 if (!Value) 1634 return false; // Don't bother with zero. 1635 1636 unsigned char B = Value & 0xff; 1637 for (unsigned i = 1; i < NumBytes; ++i) { 1638 Value >>= 8; 1639 if ((Value & 0xff) != B) 1640 return false; 1641 } 1642 return true; 1643 } 1644 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); } 1645 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); } 1646 bool isNEONi32vmov() const { 1647 if (isNEONByteReplicate(4)) 1648 return false; // Let it to be classified as byte-replicate case. 1649 if (!isImm()) 1650 return false; 1651 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1652 // Must be a constant. 1653 if (!CE) 1654 return false; 1655 int64_t Value = CE->getValue(); 1656 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1657 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1658 return (Value >= 0 && Value < 256) || 1659 (Value >= 0x0100 && Value <= 0xff00) || 1660 (Value >= 0x010000 && Value <= 0xff0000) || 1661 (Value >= 0x01000000 && Value <= 0xff000000) || 1662 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1663 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1664 } 1665 bool isNEONi32vmovNeg() const { 1666 if (!isImm()) return false; 1667 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1668 // Must be a constant. 1669 if (!CE) return false; 1670 int64_t Value = ~CE->getValue(); 1671 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1672 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1673 return (Value >= 0 && Value < 256) || 1674 (Value >= 0x0100 && Value <= 0xff00) || 1675 (Value >= 0x010000 && Value <= 0xff0000) || 1676 (Value >= 0x01000000 && Value <= 0xff000000) || 1677 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1678 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1679 } 1680 1681 bool isNEONi64splat() const { 1682 if (!isImm()) return false; 1683 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1684 // Must be a constant. 1685 if (!CE) return false; 1686 uint64_t Value = CE->getValue(); 1687 // i64 value with each byte being either 0 or 0xff. 1688 for (unsigned i = 0; i < 8; ++i) 1689 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1690 return true; 1691 } 1692 1693 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1694 // Add as immediates when possible. Null MCExpr = 0. 1695 if (!Expr) 1696 Inst.addOperand(MCOperand::CreateImm(0)); 1697 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1698 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1699 else 1700 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1701 } 1702 1703 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1704 assert(N == 2 && "Invalid number of operands!"); 1705 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1706 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1707 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1708 } 1709 1710 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1711 assert(N == 1 && "Invalid number of operands!"); 1712 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1713 } 1714 1715 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1716 assert(N == 1 && "Invalid number of operands!"); 1717 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1718 } 1719 1720 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1721 assert(N == 1 && "Invalid number of operands!"); 1722 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1723 } 1724 1725 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1726 assert(N == 1 && "Invalid number of operands!"); 1727 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1728 } 1729 1730 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1731 assert(N == 1 && "Invalid number of operands!"); 1732 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1733 } 1734 1735 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1736 assert(N == 1 && "Invalid number of operands!"); 1737 Inst.addOperand(MCOperand::CreateReg(getReg())); 1738 } 1739 1740 void addRegOperands(MCInst &Inst, unsigned N) const { 1741 assert(N == 1 && "Invalid number of operands!"); 1742 Inst.addOperand(MCOperand::CreateReg(getReg())); 1743 } 1744 1745 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1746 assert(N == 3 && "Invalid number of operands!"); 1747 assert(isRegShiftedReg() && 1748 "addRegShiftedRegOperands() on non-RegShiftedReg!"); 1749 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1750 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1751 Inst.addOperand(MCOperand::CreateImm( 1752 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1753 } 1754 1755 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1756 assert(N == 2 && "Invalid number of operands!"); 1757 assert(isRegShiftedImm() && 1758 "addRegShiftedImmOperands() on non-RegShiftedImm!"); 1759 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1760 // Shift of #32 is encoded as 0 where permitted 1761 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1762 Inst.addOperand(MCOperand::CreateImm( 1763 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1764 } 1765 1766 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1767 assert(N == 1 && "Invalid number of operands!"); 1768 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1769 ShifterImm.Imm)); 1770 } 1771 1772 void addRegListOperands(MCInst &Inst, unsigned N) const { 1773 assert(N == 1 && "Invalid number of operands!"); 1774 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1775 for (SmallVectorImpl<unsigned>::const_iterator 1776 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1777 Inst.addOperand(MCOperand::CreateReg(*I)); 1778 } 1779 1780 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1781 addRegListOperands(Inst, N); 1782 } 1783 1784 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1785 addRegListOperands(Inst, N); 1786 } 1787 1788 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1789 assert(N == 1 && "Invalid number of operands!"); 1790 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1791 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1792 } 1793 1794 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1795 assert(N == 1 && "Invalid number of operands!"); 1796 // Munge the lsb/width into a bitfield mask. 1797 unsigned lsb = Bitfield.LSB; 1798 unsigned width = Bitfield.Width; 1799 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1800 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1801 (32 - (lsb + width))); 1802 Inst.addOperand(MCOperand::CreateImm(Mask)); 1803 } 1804 1805 void addImmOperands(MCInst &Inst, unsigned N) const { 1806 assert(N == 1 && "Invalid number of operands!"); 1807 addExpr(Inst, getImm()); 1808 } 1809 1810 void addFBits16Operands(MCInst &Inst, unsigned N) const { 1811 assert(N == 1 && "Invalid number of operands!"); 1812 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1813 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 1814 } 1815 1816 void addFBits32Operands(MCInst &Inst, unsigned N) const { 1817 assert(N == 1 && "Invalid number of operands!"); 1818 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1819 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 1820 } 1821 1822 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1823 assert(N == 1 && "Invalid number of operands!"); 1824 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1825 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1826 Inst.addOperand(MCOperand::CreateImm(Val)); 1827 } 1828 1829 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1830 assert(N == 1 && "Invalid number of operands!"); 1831 // FIXME: We really want to scale the value here, but the LDRD/STRD 1832 // instruction don't encode operands that way yet. 1833 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1834 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1835 } 1836 1837 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1838 assert(N == 1 && "Invalid number of operands!"); 1839 // The immediate is scaled by four in the encoding and is stored 1840 // in the MCInst as such. Lop off the low two bits here. 1841 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1842 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1843 } 1844 1845 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1846 assert(N == 1 && "Invalid number of operands!"); 1847 // The immediate is scaled by four in the encoding and is stored 1848 // in the MCInst as such. Lop off the low two bits here. 1849 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1850 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); 1851 } 1852 1853 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1854 assert(N == 1 && "Invalid number of operands!"); 1855 // The immediate is scaled by four in the encoding and is stored 1856 // in the MCInst as such. Lop off the low two bits here. 1857 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1858 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1859 } 1860 1861 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1862 assert(N == 1 && "Invalid number of operands!"); 1863 // The constant encodes as the immediate-1, and we store in the instruction 1864 // the bits as encoded, so subtract off one here. 1865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1866 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1867 } 1868 1869 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1870 assert(N == 1 && "Invalid number of operands!"); 1871 // The constant encodes as the immediate-1, and we store in the instruction 1872 // the bits as encoded, so subtract off one here. 1873 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1874 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1875 } 1876 1877 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1878 assert(N == 1 && "Invalid number of operands!"); 1879 // The constant encodes as the immediate, except for 32, which encodes as 1880 // zero. 1881 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1882 unsigned Imm = CE->getValue(); 1883 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1884 } 1885 1886 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1887 assert(N == 1 && "Invalid number of operands!"); 1888 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1889 // the instruction as well. 1890 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1891 int Val = CE->getValue(); 1892 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1893 } 1894 1895 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1896 assert(N == 1 && "Invalid number of operands!"); 1897 // The operand is actually a t2_so_imm, but we have its bitwise 1898 // negation in the assembly source, so twiddle it here. 1899 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1900 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1901 } 1902 1903 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1904 assert(N == 1 && "Invalid number of operands!"); 1905 // The operand is actually a t2_so_imm, but we have its 1906 // negation in the assembly source, so twiddle it here. 1907 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1908 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1909 } 1910 1911 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1912 assert(N == 1 && "Invalid number of operands!"); 1913 // The operand is actually an imm0_4095, but we have its 1914 // negation in the assembly source, so twiddle it here. 1915 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1916 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1917 } 1918 1919 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { 1920 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) { 1921 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2)); 1922 return; 1923 } 1924 1925 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1926 assert(SR && "Unknown value type!"); 1927 Inst.addOperand(MCOperand::CreateExpr(SR)); 1928 } 1929 1930 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { 1931 assert(N == 1 && "Invalid number of operands!"); 1932 if (isImm()) { 1933 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1934 if (CE) { 1935 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1936 return; 1937 } 1938 1939 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1940 assert(SR && "Unknown value type!"); 1941 Inst.addOperand(MCOperand::CreateExpr(SR)); 1942 return; 1943 } 1944 1945 assert(isMem() && "Unknown value type!"); 1946 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!"); 1947 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue())); 1948 } 1949 1950 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1951 assert(N == 1 && "Invalid number of operands!"); 1952 // The operand is actually a so_imm, but we have its bitwise 1953 // negation in the assembly source, so twiddle it here. 1954 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1955 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1956 } 1957 1958 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 1959 assert(N == 1 && "Invalid number of operands!"); 1960 // The operand is actually a so_imm, but we have its 1961 // negation in the assembly source, so twiddle it here. 1962 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1963 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1964 } 1965 1966 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1967 assert(N == 1 && "Invalid number of operands!"); 1968 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1969 } 1970 1971 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { 1972 assert(N == 1 && "Invalid number of operands!"); 1973 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt()))); 1974 } 1975 1976 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1977 assert(N == 1 && "Invalid number of operands!"); 1978 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1979 } 1980 1981 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 1982 assert(N == 1 && "Invalid number of operands!"); 1983 int32_t Imm = Memory.OffsetImm->getValue(); 1984 Inst.addOperand(MCOperand::CreateImm(Imm)); 1985 } 1986 1987 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 1988 assert(N == 1 && "Invalid number of operands!"); 1989 assert(isImm() && "Not an immediate!"); 1990 1991 // If we have an immediate that's not a constant, treat it as a label 1992 // reference needing a fixup. 1993 if (!isa<MCConstantExpr>(getImm())) { 1994 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1995 return; 1996 } 1997 1998 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1999 int Val = CE->getValue(); 2000 Inst.addOperand(MCOperand::CreateImm(Val)); 2001 } 2002 2003 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 2004 assert(N == 2 && "Invalid number of operands!"); 2005 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2006 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 2007 } 2008 2009 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { 2010 addAlignedMemoryOperands(Inst, N); 2011 } 2012 2013 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { 2014 addAlignedMemoryOperands(Inst, N); 2015 } 2016 2017 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const { 2018 addAlignedMemoryOperands(Inst, N); 2019 } 2020 2021 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const { 2022 addAlignedMemoryOperands(Inst, N); 2023 } 2024 2025 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const { 2026 addAlignedMemoryOperands(Inst, N); 2027 } 2028 2029 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const { 2030 addAlignedMemoryOperands(Inst, N); 2031 } 2032 2033 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const { 2034 addAlignedMemoryOperands(Inst, N); 2035 } 2036 2037 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const { 2038 addAlignedMemoryOperands(Inst, N); 2039 } 2040 2041 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { 2042 addAlignedMemoryOperands(Inst, N); 2043 } 2044 2045 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { 2046 addAlignedMemoryOperands(Inst, N); 2047 } 2048 2049 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const { 2050 addAlignedMemoryOperands(Inst, N); 2051 } 2052 2053 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 2054 assert(N == 3 && "Invalid number of operands!"); 2055 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2056 if (!Memory.OffsetRegNum) { 2057 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2058 // Special case for #-0 2059 if (Val == INT32_MIN) Val = 0; 2060 if (Val < 0) Val = -Val; 2061 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 2062 } else { 2063 // For register offset, we encode the shift type and negation flag 2064 // here. 2065 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 2066 Memory.ShiftImm, Memory.ShiftType); 2067 } 2068 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2069 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2070 Inst.addOperand(MCOperand::CreateImm(Val)); 2071 } 2072 2073 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 2074 assert(N == 2 && "Invalid number of operands!"); 2075 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2076 assert(CE && "non-constant AM2OffsetImm operand!"); 2077 int32_t Val = CE->getValue(); 2078 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2079 // Special case for #-0 2080 if (Val == INT32_MIN) Val = 0; 2081 if (Val < 0) Val = -Val; 2082 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 2083 Inst.addOperand(MCOperand::CreateReg(0)); 2084 Inst.addOperand(MCOperand::CreateImm(Val)); 2085 } 2086 2087 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 2088 assert(N == 3 && "Invalid number of operands!"); 2089 // If we have an immediate that's not a constant, treat it as a label 2090 // reference needing a fixup. If it is a constant, it's something else 2091 // and we reject it. 2092 if (isImm()) { 2093 Inst.addOperand(MCOperand::CreateExpr(getImm())); 2094 Inst.addOperand(MCOperand::CreateReg(0)); 2095 Inst.addOperand(MCOperand::CreateImm(0)); 2096 return; 2097 } 2098 2099 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2100 if (!Memory.OffsetRegNum) { 2101 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2102 // Special case for #-0 2103 if (Val == INT32_MIN) Val = 0; 2104 if (Val < 0) Val = -Val; 2105 Val = ARM_AM::getAM3Opc(AddSub, Val); 2106 } else { 2107 // For register offset, we encode the shift type and negation flag 2108 // here. 2109 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 2110 } 2111 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2112 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2113 Inst.addOperand(MCOperand::CreateImm(Val)); 2114 } 2115 2116 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 2117 assert(N == 2 && "Invalid number of operands!"); 2118 if (Kind == k_PostIndexRegister) { 2119 int32_t Val = 2120 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 2121 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2122 Inst.addOperand(MCOperand::CreateImm(Val)); 2123 return; 2124 } 2125 2126 // Constant offset. 2127 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 2128 int32_t Val = CE->getValue(); 2129 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2130 // Special case for #-0 2131 if (Val == INT32_MIN) Val = 0; 2132 if (Val < 0) Val = -Val; 2133 Val = ARM_AM::getAM3Opc(AddSub, Val); 2134 Inst.addOperand(MCOperand::CreateReg(0)); 2135 Inst.addOperand(MCOperand::CreateImm(Val)); 2136 } 2137 2138 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 2139 assert(N == 2 && "Invalid number of operands!"); 2140 // If we have an immediate that's not a constant, treat it as a label 2141 // reference needing a fixup. If it is a constant, it's something else 2142 // and we reject it. 2143 if (isImm()) { 2144 Inst.addOperand(MCOperand::CreateExpr(getImm())); 2145 Inst.addOperand(MCOperand::CreateImm(0)); 2146 return; 2147 } 2148 2149 // The lower two bits are always zero and as such are not encoded. 2150 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2151 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2152 // Special case for #-0 2153 if (Val == INT32_MIN) Val = 0; 2154 if (Val < 0) Val = -Val; 2155 Val = ARM_AM::getAM5Opc(AddSub, Val); 2156 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2157 Inst.addOperand(MCOperand::CreateImm(Val)); 2158 } 2159 2160 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 2161 assert(N == 2 && "Invalid number of operands!"); 2162 // If we have an immediate that's not a constant, treat it as a label 2163 // reference needing a fixup. If it is a constant, it's something else 2164 // and we reject it. 2165 if (isImm()) { 2166 Inst.addOperand(MCOperand::CreateExpr(getImm())); 2167 Inst.addOperand(MCOperand::CreateImm(0)); 2168 return; 2169 } 2170 2171 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2172 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2173 Inst.addOperand(MCOperand::CreateImm(Val)); 2174 } 2175 2176 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 2177 assert(N == 2 && "Invalid number of operands!"); 2178 // The lower two bits are always zero and as such are not encoded. 2179 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2180 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2181 Inst.addOperand(MCOperand::CreateImm(Val)); 2182 } 2183 2184 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2185 assert(N == 2 && "Invalid number of operands!"); 2186 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2187 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2188 Inst.addOperand(MCOperand::CreateImm(Val)); 2189 } 2190 2191 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2192 addMemImm8OffsetOperands(Inst, N); 2193 } 2194 2195 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2196 addMemImm8OffsetOperands(Inst, N); 2197 } 2198 2199 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2200 assert(N == 2 && "Invalid number of operands!"); 2201 // If this is an immediate, it's a label reference. 2202 if (isImm()) { 2203 addExpr(Inst, getImm()); 2204 Inst.addOperand(MCOperand::CreateImm(0)); 2205 return; 2206 } 2207 2208 // Otherwise, it's a normal memory reg+offset. 2209 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2210 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2211 Inst.addOperand(MCOperand::CreateImm(Val)); 2212 } 2213 2214 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2215 assert(N == 2 && "Invalid number of operands!"); 2216 // If this is an immediate, it's a label reference. 2217 if (isImm()) { 2218 addExpr(Inst, getImm()); 2219 Inst.addOperand(MCOperand::CreateImm(0)); 2220 return; 2221 } 2222 2223 // Otherwise, it's a normal memory reg+offset. 2224 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2225 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2226 Inst.addOperand(MCOperand::CreateImm(Val)); 2227 } 2228 2229 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 2230 assert(N == 2 && "Invalid number of operands!"); 2231 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2232 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2233 } 2234 2235 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 2236 assert(N == 2 && "Invalid number of operands!"); 2237 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2238 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2239 } 2240 2241 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2242 assert(N == 3 && "Invalid number of operands!"); 2243 unsigned Val = 2244 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 2245 Memory.ShiftImm, Memory.ShiftType); 2246 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2247 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2248 Inst.addOperand(MCOperand::CreateImm(Val)); 2249 } 2250 2251 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2252 assert(N == 3 && "Invalid number of operands!"); 2253 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2254 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2255 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 2256 } 2257 2258 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 2259 assert(N == 2 && "Invalid number of operands!"); 2260 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2261 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2262 } 2263 2264 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 2265 assert(N == 2 && "Invalid number of operands!"); 2266 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2267 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2268 Inst.addOperand(MCOperand::CreateImm(Val)); 2269 } 2270 2271 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 2272 assert(N == 2 && "Invalid number of operands!"); 2273 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 2274 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2275 Inst.addOperand(MCOperand::CreateImm(Val)); 2276 } 2277 2278 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 2279 assert(N == 2 && "Invalid number of operands!"); 2280 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 2281 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2282 Inst.addOperand(MCOperand::CreateImm(Val)); 2283 } 2284 2285 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 2286 assert(N == 2 && "Invalid number of operands!"); 2287 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2288 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2289 Inst.addOperand(MCOperand::CreateImm(Val)); 2290 } 2291 2292 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 2293 assert(N == 1 && "Invalid number of operands!"); 2294 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2295 assert(CE && "non-constant post-idx-imm8 operand!"); 2296 int Imm = CE->getValue(); 2297 bool isAdd = Imm >= 0; 2298 if (Imm == INT32_MIN) Imm = 0; 2299 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 2300 Inst.addOperand(MCOperand::CreateImm(Imm)); 2301 } 2302 2303 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 2304 assert(N == 1 && "Invalid number of operands!"); 2305 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2306 assert(CE && "non-constant post-idx-imm8s4 operand!"); 2307 int Imm = CE->getValue(); 2308 bool isAdd = Imm >= 0; 2309 if (Imm == INT32_MIN) Imm = 0; 2310 // Immediate is scaled by 4. 2311 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 2312 Inst.addOperand(MCOperand::CreateImm(Imm)); 2313 } 2314 2315 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 2316 assert(N == 2 && "Invalid number of operands!"); 2317 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2318 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 2319 } 2320 2321 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 2322 assert(N == 2 && "Invalid number of operands!"); 2323 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2324 // The sign, shift type, and shift amount are encoded in a single operand 2325 // using the AM2 encoding helpers. 2326 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 2327 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 2328 PostIdxReg.ShiftTy); 2329 Inst.addOperand(MCOperand::CreateImm(Imm)); 2330 } 2331 2332 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 2333 assert(N == 1 && "Invalid number of operands!"); 2334 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 2335 } 2336 2337 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 2338 assert(N == 1 && "Invalid number of operands!"); 2339 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 2340 } 2341 2342 void addVecListOperands(MCInst &Inst, unsigned N) const { 2343 assert(N == 1 && "Invalid number of operands!"); 2344 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2345 } 2346 2347 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 2348 assert(N == 2 && "Invalid number of operands!"); 2349 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2350 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 2351 } 2352 2353 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 2354 assert(N == 1 && "Invalid number of operands!"); 2355 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2356 } 2357 2358 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 2359 assert(N == 1 && "Invalid number of operands!"); 2360 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2361 } 2362 2363 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 2364 assert(N == 1 && "Invalid number of operands!"); 2365 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2366 } 2367 2368 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 2369 assert(N == 1 && "Invalid number of operands!"); 2370 // The immediate encodes the type of constant as well as the value. 2371 // Mask in that this is an i8 splat. 2372 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2373 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 2374 } 2375 2376 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 2377 assert(N == 1 && "Invalid number of operands!"); 2378 // The immediate encodes the type of constant as well as the value. 2379 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2380 unsigned Value = CE->getValue(); 2381 if (Value >= 256) 2382 Value = (Value >> 8) | 0xa00; 2383 else 2384 Value |= 0x800; 2385 Inst.addOperand(MCOperand::CreateImm(Value)); 2386 } 2387 2388 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 2389 assert(N == 1 && "Invalid number of operands!"); 2390 // The immediate encodes the type of constant as well as the value. 2391 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2392 unsigned Value = CE->getValue(); 2393 if (Value >= 256 && Value <= 0xff00) 2394 Value = (Value >> 8) | 0x200; 2395 else if (Value > 0xffff && Value <= 0xff0000) 2396 Value = (Value >> 16) | 0x400; 2397 else if (Value > 0xffffff) 2398 Value = (Value >> 24) | 0x600; 2399 Inst.addOperand(MCOperand::CreateImm(Value)); 2400 } 2401 2402 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const { 2403 assert(N == 1 && "Invalid number of operands!"); 2404 // The immediate encodes the type of constant as well as the value. 2405 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2406 unsigned Value = CE->getValue(); 2407 assert((Inst.getOpcode() == ARM::VMOVv8i8 || 2408 Inst.getOpcode() == ARM::VMOVv16i8) && 2409 "All vmvn instructions that wants to replicate non-zero byte " 2410 "always must be replaced with VMOVv8i8 or VMOVv16i8."); 2411 unsigned B = ((~Value) & 0xff); 2412 B |= 0xe00; // cmode = 0b1110 2413 Inst.addOperand(MCOperand::CreateImm(B)); 2414 } 2415 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2416 assert(N == 1 && "Invalid number of operands!"); 2417 // The immediate encodes the type of constant as well as the value. 2418 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2419 unsigned Value = CE->getValue(); 2420 if (Value >= 256 && Value <= 0xffff) 2421 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2422 else if (Value > 0xffff && Value <= 0xffffff) 2423 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2424 else if (Value > 0xffffff) 2425 Value = (Value >> 24) | 0x600; 2426 Inst.addOperand(MCOperand::CreateImm(Value)); 2427 } 2428 2429 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const { 2430 assert(N == 1 && "Invalid number of operands!"); 2431 // The immediate encodes the type of constant as well as the value. 2432 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2433 unsigned Value = CE->getValue(); 2434 assert((Inst.getOpcode() == ARM::VMOVv8i8 || 2435 Inst.getOpcode() == ARM::VMOVv16i8) && 2436 "All instructions that wants to replicate non-zero byte " 2437 "always must be replaced with VMOVv8i8 or VMOVv16i8."); 2438 unsigned B = Value & 0xff; 2439 B |= 0xe00; // cmode = 0b1110 2440 Inst.addOperand(MCOperand::CreateImm(B)); 2441 } 2442 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2443 assert(N == 1 && "Invalid number of operands!"); 2444 // The immediate encodes the type of constant as well as the value. 2445 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2446 unsigned Value = ~CE->getValue(); 2447 if (Value >= 256 && Value <= 0xffff) 2448 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2449 else if (Value > 0xffff && Value <= 0xffffff) 2450 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2451 else if (Value > 0xffffff) 2452 Value = (Value >> 24) | 0x600; 2453 Inst.addOperand(MCOperand::CreateImm(Value)); 2454 } 2455 2456 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2457 assert(N == 1 && "Invalid number of operands!"); 2458 // The immediate encodes the type of constant as well as the value. 2459 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2460 uint64_t Value = CE->getValue(); 2461 unsigned Imm = 0; 2462 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2463 Imm |= (Value & 1) << i; 2464 } 2465 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 2466 } 2467 2468 void print(raw_ostream &OS) const override; 2469 2470 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) { 2471 auto Op = make_unique<ARMOperand>(k_ITCondMask); 2472 Op->ITMask.Mask = Mask; 2473 Op->StartLoc = S; 2474 Op->EndLoc = S; 2475 return Op; 2476 } 2477 2478 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC, 2479 SMLoc S) { 2480 auto Op = make_unique<ARMOperand>(k_CondCode); 2481 Op->CC.Val = CC; 2482 Op->StartLoc = S; 2483 Op->EndLoc = S; 2484 return Op; 2485 } 2486 2487 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) { 2488 auto Op = make_unique<ARMOperand>(k_CoprocNum); 2489 Op->Cop.Val = CopVal; 2490 Op->StartLoc = S; 2491 Op->EndLoc = S; 2492 return Op; 2493 } 2494 2495 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) { 2496 auto Op = make_unique<ARMOperand>(k_CoprocReg); 2497 Op->Cop.Val = CopVal; 2498 Op->StartLoc = S; 2499 Op->EndLoc = S; 2500 return Op; 2501 } 2502 2503 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S, 2504 SMLoc E) { 2505 auto Op = make_unique<ARMOperand>(k_CoprocOption); 2506 Op->Cop.Val = Val; 2507 Op->StartLoc = S; 2508 Op->EndLoc = E; 2509 return Op; 2510 } 2511 2512 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) { 2513 auto Op = make_unique<ARMOperand>(k_CCOut); 2514 Op->Reg.RegNum = RegNum; 2515 Op->StartLoc = S; 2516 Op->EndLoc = S; 2517 return Op; 2518 } 2519 2520 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) { 2521 auto Op = make_unique<ARMOperand>(k_Token); 2522 Op->Tok.Data = Str.data(); 2523 Op->Tok.Length = Str.size(); 2524 Op->StartLoc = S; 2525 Op->EndLoc = S; 2526 return Op; 2527 } 2528 2529 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S, 2530 SMLoc E) { 2531 auto Op = make_unique<ARMOperand>(k_Register); 2532 Op->Reg.RegNum = RegNum; 2533 Op->StartLoc = S; 2534 Op->EndLoc = E; 2535 return Op; 2536 } 2537 2538 static std::unique_ptr<ARMOperand> 2539 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, 2540 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, 2541 SMLoc E) { 2542 auto Op = make_unique<ARMOperand>(k_ShiftedRegister); 2543 Op->RegShiftedReg.ShiftTy = ShTy; 2544 Op->RegShiftedReg.SrcReg = SrcReg; 2545 Op->RegShiftedReg.ShiftReg = ShiftReg; 2546 Op->RegShiftedReg.ShiftImm = ShiftImm; 2547 Op->StartLoc = S; 2548 Op->EndLoc = E; 2549 return Op; 2550 } 2551 2552 static std::unique_ptr<ARMOperand> 2553 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, 2554 unsigned ShiftImm, SMLoc S, SMLoc E) { 2555 auto Op = make_unique<ARMOperand>(k_ShiftedImmediate); 2556 Op->RegShiftedImm.ShiftTy = ShTy; 2557 Op->RegShiftedImm.SrcReg = SrcReg; 2558 Op->RegShiftedImm.ShiftImm = ShiftImm; 2559 Op->StartLoc = S; 2560 Op->EndLoc = E; 2561 return Op; 2562 } 2563 2564 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm, 2565 SMLoc S, SMLoc E) { 2566 auto Op = make_unique<ARMOperand>(k_ShifterImmediate); 2567 Op->ShifterImm.isASR = isASR; 2568 Op->ShifterImm.Imm = Imm; 2569 Op->StartLoc = S; 2570 Op->EndLoc = E; 2571 return Op; 2572 } 2573 2574 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S, 2575 SMLoc E) { 2576 auto Op = make_unique<ARMOperand>(k_RotateImmediate); 2577 Op->RotImm.Imm = Imm; 2578 Op->StartLoc = S; 2579 Op->EndLoc = E; 2580 return Op; 2581 } 2582 2583 static std::unique_ptr<ARMOperand> 2584 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) { 2585 auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor); 2586 Op->Bitfield.LSB = LSB; 2587 Op->Bitfield.Width = Width; 2588 Op->StartLoc = S; 2589 Op->EndLoc = E; 2590 return Op; 2591 } 2592 2593 static std::unique_ptr<ARMOperand> 2594 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, 2595 SMLoc StartLoc, SMLoc EndLoc) { 2596 assert (Regs.size() > 0 && "RegList contains no registers?"); 2597 KindTy Kind = k_RegisterList; 2598 2599 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second)) 2600 Kind = k_DPRRegisterList; 2601 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2602 contains(Regs.front().second)) 2603 Kind = k_SPRRegisterList; 2604 2605 // Sort based on the register encoding values. 2606 array_pod_sort(Regs.begin(), Regs.end()); 2607 2608 auto Op = make_unique<ARMOperand>(Kind); 2609 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator 2610 I = Regs.begin(), E = Regs.end(); I != E; ++I) 2611 Op->Registers.push_back(I->second); 2612 Op->StartLoc = StartLoc; 2613 Op->EndLoc = EndLoc; 2614 return Op; 2615 } 2616 2617 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum, 2618 unsigned Count, 2619 bool isDoubleSpaced, 2620 SMLoc S, SMLoc E) { 2621 auto Op = make_unique<ARMOperand>(k_VectorList); 2622 Op->VectorList.RegNum = RegNum; 2623 Op->VectorList.Count = Count; 2624 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2625 Op->StartLoc = S; 2626 Op->EndLoc = E; 2627 return Op; 2628 } 2629 2630 static std::unique_ptr<ARMOperand> 2631 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, 2632 SMLoc S, SMLoc E) { 2633 auto Op = make_unique<ARMOperand>(k_VectorListAllLanes); 2634 Op->VectorList.RegNum = RegNum; 2635 Op->VectorList.Count = Count; 2636 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2637 Op->StartLoc = S; 2638 Op->EndLoc = E; 2639 return Op; 2640 } 2641 2642 static std::unique_ptr<ARMOperand> 2643 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, 2644 bool isDoubleSpaced, SMLoc S, SMLoc E) { 2645 auto Op = make_unique<ARMOperand>(k_VectorListIndexed); 2646 Op->VectorList.RegNum = RegNum; 2647 Op->VectorList.Count = Count; 2648 Op->VectorList.LaneIndex = Index; 2649 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2650 Op->StartLoc = S; 2651 Op->EndLoc = E; 2652 return Op; 2653 } 2654 2655 static std::unique_ptr<ARMOperand> 2656 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) { 2657 auto Op = make_unique<ARMOperand>(k_VectorIndex); 2658 Op->VectorIndex.Val = Idx; 2659 Op->StartLoc = S; 2660 Op->EndLoc = E; 2661 return Op; 2662 } 2663 2664 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S, 2665 SMLoc E) { 2666 auto Op = make_unique<ARMOperand>(k_Immediate); 2667 Op->Imm.Val = Val; 2668 Op->StartLoc = S; 2669 Op->EndLoc = E; 2670 return Op; 2671 } 2672 2673 static std::unique_ptr<ARMOperand> 2674 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm, 2675 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, 2676 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, 2677 SMLoc E, SMLoc AlignmentLoc = SMLoc()) { 2678 auto Op = make_unique<ARMOperand>(k_Memory); 2679 Op->Memory.BaseRegNum = BaseRegNum; 2680 Op->Memory.OffsetImm = OffsetImm; 2681 Op->Memory.OffsetRegNum = OffsetRegNum; 2682 Op->Memory.ShiftType = ShiftType; 2683 Op->Memory.ShiftImm = ShiftImm; 2684 Op->Memory.Alignment = Alignment; 2685 Op->Memory.isNegative = isNegative; 2686 Op->StartLoc = S; 2687 Op->EndLoc = E; 2688 Op->AlignmentLoc = AlignmentLoc; 2689 return Op; 2690 } 2691 2692 static std::unique_ptr<ARMOperand> 2693 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, 2694 unsigned ShiftImm, SMLoc S, SMLoc E) { 2695 auto Op = make_unique<ARMOperand>(k_PostIndexRegister); 2696 Op->PostIdxReg.RegNum = RegNum; 2697 Op->PostIdxReg.isAdd = isAdd; 2698 Op->PostIdxReg.ShiftTy = ShiftTy; 2699 Op->PostIdxReg.ShiftImm = ShiftImm; 2700 Op->StartLoc = S; 2701 Op->EndLoc = E; 2702 return Op; 2703 } 2704 2705 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, 2706 SMLoc S) { 2707 auto Op = make_unique<ARMOperand>(k_MemBarrierOpt); 2708 Op->MBOpt.Val = Opt; 2709 Op->StartLoc = S; 2710 Op->EndLoc = S; 2711 return Op; 2712 } 2713 2714 static std::unique_ptr<ARMOperand> 2715 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) { 2716 auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt); 2717 Op->ISBOpt.Val = Opt; 2718 Op->StartLoc = S; 2719 Op->EndLoc = S; 2720 return Op; 2721 } 2722 2723 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags, 2724 SMLoc S) { 2725 auto Op = make_unique<ARMOperand>(k_ProcIFlags); 2726 Op->IFlags.Val = IFlags; 2727 Op->StartLoc = S; 2728 Op->EndLoc = S; 2729 return Op; 2730 } 2731 2732 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) { 2733 auto Op = make_unique<ARMOperand>(k_MSRMask); 2734 Op->MMask.Val = MMask; 2735 Op->StartLoc = S; 2736 Op->EndLoc = S; 2737 return Op; 2738 } 2739 }; 2740 2741 } // end anonymous namespace. 2742 2743 void ARMOperand::print(raw_ostream &OS) const { 2744 switch (Kind) { 2745 case k_CondCode: 2746 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2747 break; 2748 case k_CCOut: 2749 OS << "<ccout " << getReg() << ">"; 2750 break; 2751 case k_ITCondMask: { 2752 static const char *const MaskStr[] = { 2753 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2754 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2755 }; 2756 assert((ITMask.Mask & 0xf) == ITMask.Mask); 2757 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2758 break; 2759 } 2760 case k_CoprocNum: 2761 OS << "<coprocessor number: " << getCoproc() << ">"; 2762 break; 2763 case k_CoprocReg: 2764 OS << "<coprocessor register: " << getCoproc() << ">"; 2765 break; 2766 case k_CoprocOption: 2767 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2768 break; 2769 case k_MSRMask: 2770 OS << "<mask: " << getMSRMask() << ">"; 2771 break; 2772 case k_Immediate: 2773 getImm()->print(OS); 2774 break; 2775 case k_MemBarrierOpt: 2776 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">"; 2777 break; 2778 case k_InstSyncBarrierOpt: 2779 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">"; 2780 break; 2781 case k_Memory: 2782 OS << "<memory " 2783 << " base:" << Memory.BaseRegNum; 2784 OS << ">"; 2785 break; 2786 case k_PostIndexRegister: 2787 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2788 << PostIdxReg.RegNum; 2789 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2790 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2791 << PostIdxReg.ShiftImm; 2792 OS << ">"; 2793 break; 2794 case k_ProcIFlags: { 2795 OS << "<ARM_PROC::"; 2796 unsigned IFlags = getProcIFlags(); 2797 for (int i=2; i >= 0; --i) 2798 if (IFlags & (1 << i)) 2799 OS << ARM_PROC::IFlagsToString(1 << i); 2800 OS << ">"; 2801 break; 2802 } 2803 case k_Register: 2804 OS << "<register " << getReg() << ">"; 2805 break; 2806 case k_ShifterImmediate: 2807 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2808 << " #" << ShifterImm.Imm << ">"; 2809 break; 2810 case k_ShiftedRegister: 2811 OS << "<so_reg_reg " 2812 << RegShiftedReg.SrcReg << " " 2813 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2814 << " " << RegShiftedReg.ShiftReg << ">"; 2815 break; 2816 case k_ShiftedImmediate: 2817 OS << "<so_reg_imm " 2818 << RegShiftedImm.SrcReg << " " 2819 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2820 << " #" << RegShiftedImm.ShiftImm << ">"; 2821 break; 2822 case k_RotateImmediate: 2823 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2824 break; 2825 case k_BitfieldDescriptor: 2826 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2827 << ", width: " << Bitfield.Width << ">"; 2828 break; 2829 case k_RegisterList: 2830 case k_DPRRegisterList: 2831 case k_SPRRegisterList: { 2832 OS << "<register_list "; 2833 2834 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2835 for (SmallVectorImpl<unsigned>::const_iterator 2836 I = RegList.begin(), E = RegList.end(); I != E; ) { 2837 OS << *I; 2838 if (++I < E) OS << ", "; 2839 } 2840 2841 OS << ">"; 2842 break; 2843 } 2844 case k_VectorList: 2845 OS << "<vector_list " << VectorList.Count << " * " 2846 << VectorList.RegNum << ">"; 2847 break; 2848 case k_VectorListAllLanes: 2849 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2850 << VectorList.RegNum << ">"; 2851 break; 2852 case k_VectorListIndexed: 2853 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2854 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2855 break; 2856 case k_Token: 2857 OS << "'" << getToken() << "'"; 2858 break; 2859 case k_VectorIndex: 2860 OS << "<vectorindex " << getVectorIndex() << ">"; 2861 break; 2862 } 2863 } 2864 2865 /// @name Auto-generated Match Functions 2866 /// { 2867 2868 static unsigned MatchRegisterName(StringRef Name); 2869 2870 /// } 2871 2872 bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2873 SMLoc &StartLoc, SMLoc &EndLoc) { 2874 StartLoc = Parser.getTok().getLoc(); 2875 EndLoc = Parser.getTok().getEndLoc(); 2876 RegNo = tryParseRegister(); 2877 2878 return (RegNo == (unsigned)-1); 2879 } 2880 2881 /// Try to parse a register name. The token must be an Identifier when called, 2882 /// and if it is a register name the token is eaten and the register number is 2883 /// returned. Otherwise return -1. 2884 /// 2885 int ARMAsmParser::tryParseRegister() { 2886 const AsmToken &Tok = Parser.getTok(); 2887 if (Tok.isNot(AsmToken::Identifier)) return -1; 2888 2889 std::string lowerCase = Tok.getString().lower(); 2890 unsigned RegNum = MatchRegisterName(lowerCase); 2891 if (!RegNum) { 2892 RegNum = StringSwitch<unsigned>(lowerCase) 2893 .Case("r13", ARM::SP) 2894 .Case("r14", ARM::LR) 2895 .Case("r15", ARM::PC) 2896 .Case("ip", ARM::R12) 2897 // Additional register name aliases for 'gas' compatibility. 2898 .Case("a1", ARM::R0) 2899 .Case("a2", ARM::R1) 2900 .Case("a3", ARM::R2) 2901 .Case("a4", ARM::R3) 2902 .Case("v1", ARM::R4) 2903 .Case("v2", ARM::R5) 2904 .Case("v3", ARM::R6) 2905 .Case("v4", ARM::R7) 2906 .Case("v5", ARM::R8) 2907 .Case("v6", ARM::R9) 2908 .Case("v7", ARM::R10) 2909 .Case("v8", ARM::R11) 2910 .Case("sb", ARM::R9) 2911 .Case("sl", ARM::R10) 2912 .Case("fp", ARM::R11) 2913 .Default(0); 2914 } 2915 if (!RegNum) { 2916 // Check for aliases registered via .req. Canonicalize to lower case. 2917 // That's more consistent since register names are case insensitive, and 2918 // it's how the original entry was passed in from MC/MCParser/AsmParser. 2919 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2920 // If no match, return failure. 2921 if (Entry == RegisterReqs.end()) 2922 return -1; 2923 Parser.Lex(); // Eat identifier token. 2924 return Entry->getValue(); 2925 } 2926 2927 Parser.Lex(); // Eat identifier token. 2928 2929 return RegNum; 2930 } 2931 2932 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2933 // If a recoverable error occurs, return 1. If an irrecoverable error 2934 // occurs, return -1. An irrecoverable error is one where tokens have been 2935 // consumed in the process of trying to parse the shifter (i.e., when it is 2936 // indeed a shifter operand, but malformed). 2937 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { 2938 SMLoc S = Parser.getTok().getLoc(); 2939 const AsmToken &Tok = Parser.getTok(); 2940 if (Tok.isNot(AsmToken::Identifier)) 2941 return -1; 2942 2943 std::string lowerCase = Tok.getString().lower(); 2944 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2945 .Case("asl", ARM_AM::lsl) 2946 .Case("lsl", ARM_AM::lsl) 2947 .Case("lsr", ARM_AM::lsr) 2948 .Case("asr", ARM_AM::asr) 2949 .Case("ror", ARM_AM::ror) 2950 .Case("rrx", ARM_AM::rrx) 2951 .Default(ARM_AM::no_shift); 2952 2953 if (ShiftTy == ARM_AM::no_shift) 2954 return 1; 2955 2956 Parser.Lex(); // Eat the operator. 2957 2958 // The source register for the shift has already been added to the 2959 // operand list, so we need to pop it off and combine it into the shifted 2960 // register operand instead. 2961 std::unique_ptr<ARMOperand> PrevOp( 2962 (ARMOperand *)Operands.pop_back_val().release()); 2963 if (!PrevOp->isReg()) 2964 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2965 int SrcReg = PrevOp->getReg(); 2966 2967 SMLoc EndLoc; 2968 int64_t Imm = 0; 2969 int ShiftReg = 0; 2970 if (ShiftTy == ARM_AM::rrx) { 2971 // RRX Doesn't have an explicit shift amount. The encoder expects 2972 // the shift register to be the same as the source register. Seems odd, 2973 // but OK. 2974 ShiftReg = SrcReg; 2975 } else { 2976 // Figure out if this is shifted by a constant or a register (for non-RRX). 2977 if (Parser.getTok().is(AsmToken::Hash) || 2978 Parser.getTok().is(AsmToken::Dollar)) { 2979 Parser.Lex(); // Eat hash. 2980 SMLoc ImmLoc = Parser.getTok().getLoc(); 2981 const MCExpr *ShiftExpr = nullptr; 2982 if (getParser().parseExpression(ShiftExpr, EndLoc)) { 2983 Error(ImmLoc, "invalid immediate shift value"); 2984 return -1; 2985 } 2986 // The expression must be evaluatable as an immediate. 2987 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 2988 if (!CE) { 2989 Error(ImmLoc, "invalid immediate shift value"); 2990 return -1; 2991 } 2992 // Range check the immediate. 2993 // lsl, ror: 0 <= imm <= 31 2994 // lsr, asr: 0 <= imm <= 32 2995 Imm = CE->getValue(); 2996 if (Imm < 0 || 2997 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2998 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 2999 Error(ImmLoc, "immediate shift value out of range"); 3000 return -1; 3001 } 3002 // shift by zero is a nop. Always send it through as lsl. 3003 // ('as' compatibility) 3004 if (Imm == 0) 3005 ShiftTy = ARM_AM::lsl; 3006 } else if (Parser.getTok().is(AsmToken::Identifier)) { 3007 SMLoc L = Parser.getTok().getLoc(); 3008 EndLoc = Parser.getTok().getEndLoc(); 3009 ShiftReg = tryParseRegister(); 3010 if (ShiftReg == -1) { 3011 Error(L, "expected immediate or register in shift operand"); 3012 return -1; 3013 } 3014 } else { 3015 Error(Parser.getTok().getLoc(), 3016 "expected immediate or register in shift operand"); 3017 return -1; 3018 } 3019 } 3020 3021 if (ShiftReg && ShiftTy != ARM_AM::rrx) 3022 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 3023 ShiftReg, Imm, 3024 S, EndLoc)); 3025 else 3026 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 3027 S, EndLoc)); 3028 3029 return 0; 3030 } 3031 3032 3033 /// Try to parse a register name. The token must be an Identifier when called. 3034 /// If it's a register, an AsmOperand is created. Another AsmOperand is created 3035 /// if there is a "writeback". 'true' if it's not a register. 3036 /// 3037 /// TODO this is likely to change to allow different register types and or to 3038 /// parse for a specific register type. 3039 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { 3040 const AsmToken &RegTok = Parser.getTok(); 3041 int RegNo = tryParseRegister(); 3042 if (RegNo == -1) 3043 return true; 3044 3045 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), 3046 RegTok.getEndLoc())); 3047 3048 const AsmToken &ExclaimTok = Parser.getTok(); 3049 if (ExclaimTok.is(AsmToken::Exclaim)) { 3050 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 3051 ExclaimTok.getLoc())); 3052 Parser.Lex(); // Eat exclaim token 3053 return false; 3054 } 3055 3056 // Also check for an index operand. This is only legal for vector registers, 3057 // but that'll get caught OK in operand matching, so we don't need to 3058 // explicitly filter everything else out here. 3059 if (Parser.getTok().is(AsmToken::LBrac)) { 3060 SMLoc SIdx = Parser.getTok().getLoc(); 3061 Parser.Lex(); // Eat left bracket token. 3062 3063 const MCExpr *ImmVal; 3064 if (getParser().parseExpression(ImmVal)) 3065 return true; 3066 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 3067 if (!MCE) 3068 return TokError("immediate value expected for vector index"); 3069 3070 if (Parser.getTok().isNot(AsmToken::RBrac)) 3071 return Error(Parser.getTok().getLoc(), "']' expected"); 3072 3073 SMLoc E = Parser.getTok().getEndLoc(); 3074 Parser.Lex(); // Eat right bracket token. 3075 3076 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 3077 SIdx, E, 3078 getContext())); 3079 } 3080 3081 return false; 3082 } 3083 3084 /// MatchCoprocessorOperandName - Try to parse an coprocessor related 3085 /// instruction with a symbolic operand name. 3086 /// We accept "crN" syntax for GAS compatibility. 3087 /// <operand-name> ::= <prefix><number> 3088 /// If CoprocOp is 'c', then: 3089 /// <prefix> ::= c | cr 3090 /// If CoprocOp is 'p', then : 3091 /// <prefix> ::= p 3092 /// <number> ::= integer in range [0, 15] 3093 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 3094 // Use the same layout as the tablegen'erated register name matcher. Ugly, 3095 // but efficient. 3096 if (Name.size() < 2 || Name[0] != CoprocOp) 3097 return -1; 3098 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front(); 3099 3100 switch (Name.size()) { 3101 default: return -1; 3102 case 1: 3103 switch (Name[0]) { 3104 default: return -1; 3105 case '0': return 0; 3106 case '1': return 1; 3107 case '2': return 2; 3108 case '3': return 3; 3109 case '4': return 4; 3110 case '5': return 5; 3111 case '6': return 6; 3112 case '7': return 7; 3113 case '8': return 8; 3114 case '9': return 9; 3115 } 3116 case 2: 3117 if (Name[0] != '1') 3118 return -1; 3119 switch (Name[1]) { 3120 default: return -1; 3121 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON) 3122 case '0': return CoprocOp == 'p'? -1: 10; 3123 case '1': return CoprocOp == 'p'? -1: 11; 3124 case '2': return 12; 3125 case '3': return 13; 3126 case '4': return 14; 3127 case '5': return 15; 3128 } 3129 } 3130 } 3131 3132 /// parseITCondCode - Try to parse a condition code for an IT instruction. 3133 ARMAsmParser::OperandMatchResultTy 3134 ARMAsmParser::parseITCondCode(OperandVector &Operands) { 3135 SMLoc S = Parser.getTok().getLoc(); 3136 const AsmToken &Tok = Parser.getTok(); 3137 if (!Tok.is(AsmToken::Identifier)) 3138 return MatchOperand_NoMatch; 3139 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 3140 .Case("eq", ARMCC::EQ) 3141 .Case("ne", ARMCC::NE) 3142 .Case("hs", ARMCC::HS) 3143 .Case("cs", ARMCC::HS) 3144 .Case("lo", ARMCC::LO) 3145 .Case("cc", ARMCC::LO) 3146 .Case("mi", ARMCC::MI) 3147 .Case("pl", ARMCC::PL) 3148 .Case("vs", ARMCC::VS) 3149 .Case("vc", ARMCC::VC) 3150 .Case("hi", ARMCC::HI) 3151 .Case("ls", ARMCC::LS) 3152 .Case("ge", ARMCC::GE) 3153 .Case("lt", ARMCC::LT) 3154 .Case("gt", ARMCC::GT) 3155 .Case("le", ARMCC::LE) 3156 .Case("al", ARMCC::AL) 3157 .Default(~0U); 3158 if (CC == ~0U) 3159 return MatchOperand_NoMatch; 3160 Parser.Lex(); // Eat the token. 3161 3162 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 3163 3164 return MatchOperand_Success; 3165 } 3166 3167 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 3168 /// token must be an Identifier when called, and if it is a coprocessor 3169 /// number, the token is eaten and the operand is added to the operand list. 3170 ARMAsmParser::OperandMatchResultTy 3171 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { 3172 SMLoc S = Parser.getTok().getLoc(); 3173 const AsmToken &Tok = Parser.getTok(); 3174 if (Tok.isNot(AsmToken::Identifier)) 3175 return MatchOperand_NoMatch; 3176 3177 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 3178 if (Num == -1) 3179 return MatchOperand_NoMatch; 3180 3181 Parser.Lex(); // Eat identifier token. 3182 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 3183 return MatchOperand_Success; 3184 } 3185 3186 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 3187 /// token must be an Identifier when called, and if it is a coprocessor 3188 /// number, the token is eaten and the operand is added to the operand list. 3189 ARMAsmParser::OperandMatchResultTy 3190 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { 3191 SMLoc S = Parser.getTok().getLoc(); 3192 const AsmToken &Tok = Parser.getTok(); 3193 if (Tok.isNot(AsmToken::Identifier)) 3194 return MatchOperand_NoMatch; 3195 3196 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 3197 if (Reg == -1) 3198 return MatchOperand_NoMatch; 3199 3200 Parser.Lex(); // Eat identifier token. 3201 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 3202 return MatchOperand_Success; 3203 } 3204 3205 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 3206 /// coproc_option : '{' imm0_255 '}' 3207 ARMAsmParser::OperandMatchResultTy 3208 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { 3209 SMLoc S = Parser.getTok().getLoc(); 3210 3211 // If this isn't a '{', this isn't a coprocessor immediate operand. 3212 if (Parser.getTok().isNot(AsmToken::LCurly)) 3213 return MatchOperand_NoMatch; 3214 Parser.Lex(); // Eat the '{' 3215 3216 const MCExpr *Expr; 3217 SMLoc Loc = Parser.getTok().getLoc(); 3218 if (getParser().parseExpression(Expr)) { 3219 Error(Loc, "illegal expression"); 3220 return MatchOperand_ParseFail; 3221 } 3222 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 3223 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 3224 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 3225 return MatchOperand_ParseFail; 3226 } 3227 int Val = CE->getValue(); 3228 3229 // Check for and consume the closing '}' 3230 if (Parser.getTok().isNot(AsmToken::RCurly)) 3231 return MatchOperand_ParseFail; 3232 SMLoc E = Parser.getTok().getEndLoc(); 3233 Parser.Lex(); // Eat the '}' 3234 3235 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 3236 return MatchOperand_Success; 3237 } 3238 3239 // For register list parsing, we need to map from raw GPR register numbering 3240 // to the enumeration values. The enumeration values aren't sorted by 3241 // register number due to our using "sp", "lr" and "pc" as canonical names. 3242 static unsigned getNextRegister(unsigned Reg) { 3243 // If this is a GPR, we need to do it manually, otherwise we can rely 3244 // on the sort ordering of the enumeration since the other reg-classes 3245 // are sane. 3246 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3247 return Reg + 1; 3248 switch(Reg) { 3249 default: llvm_unreachable("Invalid GPR number!"); 3250 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 3251 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 3252 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 3253 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 3254 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 3255 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 3256 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 3257 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 3258 } 3259 } 3260 3261 // Return the low-subreg of a given Q register. 3262 static unsigned getDRegFromQReg(unsigned QReg) { 3263 switch (QReg) { 3264 default: llvm_unreachable("expected a Q register!"); 3265 case ARM::Q0: return ARM::D0; 3266 case ARM::Q1: return ARM::D2; 3267 case ARM::Q2: return ARM::D4; 3268 case ARM::Q3: return ARM::D6; 3269 case ARM::Q4: return ARM::D8; 3270 case ARM::Q5: return ARM::D10; 3271 case ARM::Q6: return ARM::D12; 3272 case ARM::Q7: return ARM::D14; 3273 case ARM::Q8: return ARM::D16; 3274 case ARM::Q9: return ARM::D18; 3275 case ARM::Q10: return ARM::D20; 3276 case ARM::Q11: return ARM::D22; 3277 case ARM::Q12: return ARM::D24; 3278 case ARM::Q13: return ARM::D26; 3279 case ARM::Q14: return ARM::D28; 3280 case ARM::Q15: return ARM::D30; 3281 } 3282 } 3283 3284 /// Parse a register list. 3285 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) { 3286 assert(Parser.getTok().is(AsmToken::LCurly) && 3287 "Token is not a Left Curly Brace"); 3288 SMLoc S = Parser.getTok().getLoc(); 3289 Parser.Lex(); // Eat '{' token. 3290 SMLoc RegLoc = Parser.getTok().getLoc(); 3291 3292 // Check the first register in the list to see what register class 3293 // this is a list of. 3294 int Reg = tryParseRegister(); 3295 if (Reg == -1) 3296 return Error(RegLoc, "register expected"); 3297 3298 // The reglist instructions have at most 16 registers, so reserve 3299 // space for that many. 3300 int EReg = 0; 3301 SmallVector<std::pair<unsigned, unsigned>, 16> Registers; 3302 3303 // Allow Q regs and just interpret them as the two D sub-registers. 3304 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3305 Reg = getDRegFromQReg(Reg); 3306 EReg = MRI->getEncodingValue(Reg); 3307 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3308 ++Reg; 3309 } 3310 const MCRegisterClass *RC; 3311 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3312 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 3313 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 3314 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 3315 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 3316 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 3317 else 3318 return Error(RegLoc, "invalid register in register list"); 3319 3320 // Store the register. 3321 EReg = MRI->getEncodingValue(Reg); 3322 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3323 3324 // This starts immediately after the first register token in the list, 3325 // so we can see either a comma or a minus (range separator) as a legal 3326 // next token. 3327 while (Parser.getTok().is(AsmToken::Comma) || 3328 Parser.getTok().is(AsmToken::Minus)) { 3329 if (Parser.getTok().is(AsmToken::Minus)) { 3330 Parser.Lex(); // Eat the minus. 3331 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3332 int EndReg = tryParseRegister(); 3333 if (EndReg == -1) 3334 return Error(AfterMinusLoc, "register expected"); 3335 // Allow Q regs and just interpret them as the two D sub-registers. 3336 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3337 EndReg = getDRegFromQReg(EndReg) + 1; 3338 // If the register is the same as the start reg, there's nothing 3339 // more to do. 3340 if (Reg == EndReg) 3341 continue; 3342 // The register must be in the same register class as the first. 3343 if (!RC->contains(EndReg)) 3344 return Error(AfterMinusLoc, "invalid register in register list"); 3345 // Ranges must go from low to high. 3346 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 3347 return Error(AfterMinusLoc, "bad range in register list"); 3348 3349 // Add all the registers in the range to the register list. 3350 while (Reg != EndReg) { 3351 Reg = getNextRegister(Reg); 3352 EReg = MRI->getEncodingValue(Reg); 3353 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3354 } 3355 continue; 3356 } 3357 Parser.Lex(); // Eat the comma. 3358 RegLoc = Parser.getTok().getLoc(); 3359 int OldReg = Reg; 3360 const AsmToken RegTok = Parser.getTok(); 3361 Reg = tryParseRegister(); 3362 if (Reg == -1) 3363 return Error(RegLoc, "register expected"); 3364 // Allow Q regs and just interpret them as the two D sub-registers. 3365 bool isQReg = false; 3366 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3367 Reg = getDRegFromQReg(Reg); 3368 isQReg = true; 3369 } 3370 // The register must be in the same register class as the first. 3371 if (!RC->contains(Reg)) 3372 return Error(RegLoc, "invalid register in register list"); 3373 // List must be monotonically increasing. 3374 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 3375 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3376 Warning(RegLoc, "register list not in ascending order"); 3377 else 3378 return Error(RegLoc, "register list not in ascending order"); 3379 } 3380 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { 3381 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 3382 ") in register list"); 3383 continue; 3384 } 3385 // VFP register lists must also be contiguous. 3386 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 3387 Reg != OldReg + 1) 3388 return Error(RegLoc, "non-contiguous register range"); 3389 EReg = MRI->getEncodingValue(Reg); 3390 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3391 if (isQReg) { 3392 EReg = MRI->getEncodingValue(++Reg); 3393 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3394 } 3395 } 3396 3397 if (Parser.getTok().isNot(AsmToken::RCurly)) 3398 return Error(Parser.getTok().getLoc(), "'}' expected"); 3399 SMLoc E = Parser.getTok().getEndLoc(); 3400 Parser.Lex(); // Eat '}' token. 3401 3402 // Push the register list operand. 3403 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 3404 3405 // The ARM system instruction variants for LDM/STM have a '^' token here. 3406 if (Parser.getTok().is(AsmToken::Caret)) { 3407 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 3408 Parser.Lex(); // Eat '^' token. 3409 } 3410 3411 return false; 3412 } 3413 3414 // Helper function to parse the lane index for vector lists. 3415 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3416 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { 3417 Index = 0; // Always return a defined index value. 3418 if (Parser.getTok().is(AsmToken::LBrac)) { 3419 Parser.Lex(); // Eat the '['. 3420 if (Parser.getTok().is(AsmToken::RBrac)) { 3421 // "Dn[]" is the 'all lanes' syntax. 3422 LaneKind = AllLanes; 3423 EndLoc = Parser.getTok().getEndLoc(); 3424 Parser.Lex(); // Eat the ']'. 3425 return MatchOperand_Success; 3426 } 3427 3428 // There's an optional '#' token here. Normally there wouldn't be, but 3429 // inline assemble puts one in, and it's friendly to accept that. 3430 if (Parser.getTok().is(AsmToken::Hash)) 3431 Parser.Lex(); // Eat '#' or '$'. 3432 3433 const MCExpr *LaneIndex; 3434 SMLoc Loc = Parser.getTok().getLoc(); 3435 if (getParser().parseExpression(LaneIndex)) { 3436 Error(Loc, "illegal expression"); 3437 return MatchOperand_ParseFail; 3438 } 3439 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 3440 if (!CE) { 3441 Error(Loc, "lane index must be empty or an integer"); 3442 return MatchOperand_ParseFail; 3443 } 3444 if (Parser.getTok().isNot(AsmToken::RBrac)) { 3445 Error(Parser.getTok().getLoc(), "']' expected"); 3446 return MatchOperand_ParseFail; 3447 } 3448 EndLoc = Parser.getTok().getEndLoc(); 3449 Parser.Lex(); // Eat the ']'. 3450 int64_t Val = CE->getValue(); 3451 3452 // FIXME: Make this range check context sensitive for .8, .16, .32. 3453 if (Val < 0 || Val > 7) { 3454 Error(Parser.getTok().getLoc(), "lane index out of range"); 3455 return MatchOperand_ParseFail; 3456 } 3457 Index = Val; 3458 LaneKind = IndexedLane; 3459 return MatchOperand_Success; 3460 } 3461 LaneKind = NoLanes; 3462 return MatchOperand_Success; 3463 } 3464 3465 // parse a vector register list 3466 ARMAsmParser::OperandMatchResultTy 3467 ARMAsmParser::parseVectorList(OperandVector &Operands) { 3468 VectorLaneTy LaneKind; 3469 unsigned LaneIndex; 3470 SMLoc S = Parser.getTok().getLoc(); 3471 // As an extension (to match gas), support a plain D register or Q register 3472 // (without encosing curly braces) as a single or double entry list, 3473 // respectively. 3474 if (Parser.getTok().is(AsmToken::Identifier)) { 3475 SMLoc E = Parser.getTok().getEndLoc(); 3476 int Reg = tryParseRegister(); 3477 if (Reg == -1) 3478 return MatchOperand_NoMatch; 3479 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3480 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3481 if (Res != MatchOperand_Success) 3482 return Res; 3483 switch (LaneKind) { 3484 case NoLanes: 3485 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3486 break; 3487 case AllLanes: 3488 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3489 S, E)); 3490 break; 3491 case IndexedLane: 3492 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3493 LaneIndex, 3494 false, S, E)); 3495 break; 3496 } 3497 return MatchOperand_Success; 3498 } 3499 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3500 Reg = getDRegFromQReg(Reg); 3501 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3502 if (Res != MatchOperand_Success) 3503 return Res; 3504 switch (LaneKind) { 3505 case NoLanes: 3506 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3507 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3508 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3509 break; 3510 case AllLanes: 3511 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3512 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3513 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3514 S, E)); 3515 break; 3516 case IndexedLane: 3517 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3518 LaneIndex, 3519 false, S, E)); 3520 break; 3521 } 3522 return MatchOperand_Success; 3523 } 3524 Error(S, "vector register expected"); 3525 return MatchOperand_ParseFail; 3526 } 3527 3528 if (Parser.getTok().isNot(AsmToken::LCurly)) 3529 return MatchOperand_NoMatch; 3530 3531 Parser.Lex(); // Eat '{' token. 3532 SMLoc RegLoc = Parser.getTok().getLoc(); 3533 3534 int Reg = tryParseRegister(); 3535 if (Reg == -1) { 3536 Error(RegLoc, "register expected"); 3537 return MatchOperand_ParseFail; 3538 } 3539 unsigned Count = 1; 3540 int Spacing = 0; 3541 unsigned FirstReg = Reg; 3542 // The list is of D registers, but we also allow Q regs and just interpret 3543 // them as the two D sub-registers. 3544 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3545 FirstReg = Reg = getDRegFromQReg(Reg); 3546 Spacing = 1; // double-spacing requires explicit D registers, otherwise 3547 // it's ambiguous with four-register single spaced. 3548 ++Reg; 3549 ++Count; 3550 } 3551 3552 SMLoc E; 3553 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) 3554 return MatchOperand_ParseFail; 3555 3556 while (Parser.getTok().is(AsmToken::Comma) || 3557 Parser.getTok().is(AsmToken::Minus)) { 3558 if (Parser.getTok().is(AsmToken::Minus)) { 3559 if (!Spacing) 3560 Spacing = 1; // Register range implies a single spaced list. 3561 else if (Spacing == 2) { 3562 Error(Parser.getTok().getLoc(), 3563 "sequential registers in double spaced list"); 3564 return MatchOperand_ParseFail; 3565 } 3566 Parser.Lex(); // Eat the minus. 3567 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3568 int EndReg = tryParseRegister(); 3569 if (EndReg == -1) { 3570 Error(AfterMinusLoc, "register expected"); 3571 return MatchOperand_ParseFail; 3572 } 3573 // Allow Q regs and just interpret them as the two D sub-registers. 3574 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3575 EndReg = getDRegFromQReg(EndReg) + 1; 3576 // If the register is the same as the start reg, there's nothing 3577 // more to do. 3578 if (Reg == EndReg) 3579 continue; 3580 // The register must be in the same register class as the first. 3581 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3582 Error(AfterMinusLoc, "invalid register in register list"); 3583 return MatchOperand_ParseFail; 3584 } 3585 // Ranges must go from low to high. 3586 if (Reg > EndReg) { 3587 Error(AfterMinusLoc, "bad range in register list"); 3588 return MatchOperand_ParseFail; 3589 } 3590 // Parse the lane specifier if present. 3591 VectorLaneTy NextLaneKind; 3592 unsigned NextLaneIndex; 3593 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3594 MatchOperand_Success) 3595 return MatchOperand_ParseFail; 3596 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3597 Error(AfterMinusLoc, "mismatched lane index in register list"); 3598 return MatchOperand_ParseFail; 3599 } 3600 3601 // Add all the registers in the range to the register list. 3602 Count += EndReg - Reg; 3603 Reg = EndReg; 3604 continue; 3605 } 3606 Parser.Lex(); // Eat the comma. 3607 RegLoc = Parser.getTok().getLoc(); 3608 int OldReg = Reg; 3609 Reg = tryParseRegister(); 3610 if (Reg == -1) { 3611 Error(RegLoc, "register expected"); 3612 return MatchOperand_ParseFail; 3613 } 3614 // vector register lists must be contiguous. 3615 // It's OK to use the enumeration values directly here rather, as the 3616 // VFP register classes have the enum sorted properly. 3617 // 3618 // The list is of D registers, but we also allow Q regs and just interpret 3619 // them as the two D sub-registers. 3620 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3621 if (!Spacing) 3622 Spacing = 1; // Register range implies a single spaced list. 3623 else if (Spacing == 2) { 3624 Error(RegLoc, 3625 "invalid register in double-spaced list (must be 'D' register')"); 3626 return MatchOperand_ParseFail; 3627 } 3628 Reg = getDRegFromQReg(Reg); 3629 if (Reg != OldReg + 1) { 3630 Error(RegLoc, "non-contiguous register range"); 3631 return MatchOperand_ParseFail; 3632 } 3633 ++Reg; 3634 Count += 2; 3635 // Parse the lane specifier if present. 3636 VectorLaneTy NextLaneKind; 3637 unsigned NextLaneIndex; 3638 SMLoc LaneLoc = Parser.getTok().getLoc(); 3639 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3640 MatchOperand_Success) 3641 return MatchOperand_ParseFail; 3642 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3643 Error(LaneLoc, "mismatched lane index in register list"); 3644 return MatchOperand_ParseFail; 3645 } 3646 continue; 3647 } 3648 // Normal D register. 3649 // Figure out the register spacing (single or double) of the list if 3650 // we don't know it already. 3651 if (!Spacing) 3652 Spacing = 1 + (Reg == OldReg + 2); 3653 3654 // Just check that it's contiguous and keep going. 3655 if (Reg != OldReg + Spacing) { 3656 Error(RegLoc, "non-contiguous register range"); 3657 return MatchOperand_ParseFail; 3658 } 3659 ++Count; 3660 // Parse the lane specifier if present. 3661 VectorLaneTy NextLaneKind; 3662 unsigned NextLaneIndex; 3663 SMLoc EndLoc = Parser.getTok().getLoc(); 3664 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) 3665 return MatchOperand_ParseFail; 3666 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3667 Error(EndLoc, "mismatched lane index in register list"); 3668 return MatchOperand_ParseFail; 3669 } 3670 } 3671 3672 if (Parser.getTok().isNot(AsmToken::RCurly)) { 3673 Error(Parser.getTok().getLoc(), "'}' expected"); 3674 return MatchOperand_ParseFail; 3675 } 3676 E = Parser.getTok().getEndLoc(); 3677 Parser.Lex(); // Eat '}' token. 3678 3679 switch (LaneKind) { 3680 case NoLanes: 3681 // Two-register operands have been converted to the 3682 // composite register classes. 3683 if (Count == 2) { 3684 const MCRegisterClass *RC = (Spacing == 1) ? 3685 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3686 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3687 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3688 } 3689 3690 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3691 (Spacing == 2), S, E)); 3692 break; 3693 case AllLanes: 3694 // Two-register operands have been converted to the 3695 // composite register classes. 3696 if (Count == 2) { 3697 const MCRegisterClass *RC = (Spacing == 1) ? 3698 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3699 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3700 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3701 } 3702 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3703 (Spacing == 2), 3704 S, E)); 3705 break; 3706 case IndexedLane: 3707 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3708 LaneIndex, 3709 (Spacing == 2), 3710 S, E)); 3711 break; 3712 } 3713 return MatchOperand_Success; 3714 } 3715 3716 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3717 ARMAsmParser::OperandMatchResultTy 3718 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { 3719 SMLoc S = Parser.getTok().getLoc(); 3720 const AsmToken &Tok = Parser.getTok(); 3721 unsigned Opt; 3722 3723 if (Tok.is(AsmToken::Identifier)) { 3724 StringRef OptStr = Tok.getString(); 3725 3726 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 3727 .Case("sy", ARM_MB::SY) 3728 .Case("st", ARM_MB::ST) 3729 .Case("ld", ARM_MB::LD) 3730 .Case("sh", ARM_MB::ISH) 3731 .Case("ish", ARM_MB::ISH) 3732 .Case("shst", ARM_MB::ISHST) 3733 .Case("ishst", ARM_MB::ISHST) 3734 .Case("ishld", ARM_MB::ISHLD) 3735 .Case("nsh", ARM_MB::NSH) 3736 .Case("un", ARM_MB::NSH) 3737 .Case("nshst", ARM_MB::NSHST) 3738 .Case("nshld", ARM_MB::NSHLD) 3739 .Case("unst", ARM_MB::NSHST) 3740 .Case("osh", ARM_MB::OSH) 3741 .Case("oshst", ARM_MB::OSHST) 3742 .Case("oshld", ARM_MB::OSHLD) 3743 .Default(~0U); 3744 3745 // ishld, oshld, nshld and ld are only available from ARMv8. 3746 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD || 3747 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD)) 3748 Opt = ~0U; 3749 3750 if (Opt == ~0U) 3751 return MatchOperand_NoMatch; 3752 3753 Parser.Lex(); // Eat identifier token. 3754 } else if (Tok.is(AsmToken::Hash) || 3755 Tok.is(AsmToken::Dollar) || 3756 Tok.is(AsmToken::Integer)) { 3757 if (Parser.getTok().isNot(AsmToken::Integer)) 3758 Parser.Lex(); // Eat '#' or '$'. 3759 SMLoc Loc = Parser.getTok().getLoc(); 3760 3761 const MCExpr *MemBarrierID; 3762 if (getParser().parseExpression(MemBarrierID)) { 3763 Error(Loc, "illegal expression"); 3764 return MatchOperand_ParseFail; 3765 } 3766 3767 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 3768 if (!CE) { 3769 Error(Loc, "constant expression expected"); 3770 return MatchOperand_ParseFail; 3771 } 3772 3773 int Val = CE->getValue(); 3774 if (Val & ~0xf) { 3775 Error(Loc, "immediate value out of range"); 3776 return MatchOperand_ParseFail; 3777 } 3778 3779 Opt = ARM_MB::RESERVED_0 + Val; 3780 } else 3781 return MatchOperand_ParseFail; 3782 3783 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3784 return MatchOperand_Success; 3785 } 3786 3787 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. 3788 ARMAsmParser::OperandMatchResultTy 3789 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { 3790 SMLoc S = Parser.getTok().getLoc(); 3791 const AsmToken &Tok = Parser.getTok(); 3792 unsigned Opt; 3793 3794 if (Tok.is(AsmToken::Identifier)) { 3795 StringRef OptStr = Tok.getString(); 3796 3797 if (OptStr.equals_lower("sy")) 3798 Opt = ARM_ISB::SY; 3799 else 3800 return MatchOperand_NoMatch; 3801 3802 Parser.Lex(); // Eat identifier token. 3803 } else if (Tok.is(AsmToken::Hash) || 3804 Tok.is(AsmToken::Dollar) || 3805 Tok.is(AsmToken::Integer)) { 3806 if (Parser.getTok().isNot(AsmToken::Integer)) 3807 Parser.Lex(); // Eat '#' or '$'. 3808 SMLoc Loc = Parser.getTok().getLoc(); 3809 3810 const MCExpr *ISBarrierID; 3811 if (getParser().parseExpression(ISBarrierID)) { 3812 Error(Loc, "illegal expression"); 3813 return MatchOperand_ParseFail; 3814 } 3815 3816 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID); 3817 if (!CE) { 3818 Error(Loc, "constant expression expected"); 3819 return MatchOperand_ParseFail; 3820 } 3821 3822 int Val = CE->getValue(); 3823 if (Val & ~0xf) { 3824 Error(Loc, "immediate value out of range"); 3825 return MatchOperand_ParseFail; 3826 } 3827 3828 Opt = ARM_ISB::RESERVED_0 + Val; 3829 } else 3830 return MatchOperand_ParseFail; 3831 3832 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( 3833 (ARM_ISB::InstSyncBOpt)Opt, S)); 3834 return MatchOperand_Success; 3835 } 3836 3837 3838 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3839 ARMAsmParser::OperandMatchResultTy 3840 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { 3841 SMLoc S = Parser.getTok().getLoc(); 3842 const AsmToken &Tok = Parser.getTok(); 3843 if (!Tok.is(AsmToken::Identifier)) 3844 return MatchOperand_NoMatch; 3845 StringRef IFlagsStr = Tok.getString(); 3846 3847 // An iflags string of "none" is interpreted to mean that none of the AIF 3848 // bits are set. Not a terribly useful instruction, but a valid encoding. 3849 unsigned IFlags = 0; 3850 if (IFlagsStr != "none") { 3851 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3852 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3853 .Case("a", ARM_PROC::A) 3854 .Case("i", ARM_PROC::I) 3855 .Case("f", ARM_PROC::F) 3856 .Default(~0U); 3857 3858 // If some specific iflag is already set, it means that some letter is 3859 // present more than once, this is not acceptable. 3860 if (Flag == ~0U || (IFlags & Flag)) 3861 return MatchOperand_NoMatch; 3862 3863 IFlags |= Flag; 3864 } 3865 } 3866 3867 Parser.Lex(); // Eat identifier token. 3868 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3869 return MatchOperand_Success; 3870 } 3871 3872 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3873 ARMAsmParser::OperandMatchResultTy 3874 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { 3875 SMLoc S = Parser.getTok().getLoc(); 3876 const AsmToken &Tok = Parser.getTok(); 3877 if (!Tok.is(AsmToken::Identifier)) 3878 return MatchOperand_NoMatch; 3879 StringRef Mask = Tok.getString(); 3880 3881 if (isMClass()) { 3882 // See ARMv6-M 10.1.1 3883 std::string Name = Mask.lower(); 3884 unsigned FlagsVal = StringSwitch<unsigned>(Name) 3885 // Note: in the documentation: 3886 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 3887 // for MSR APSR_nzcvq. 3888 // but we do make it an alias here. This is so to get the "mask encoding" 3889 // bits correct on MSR APSR writes. 3890 // 3891 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 3892 // should really only be allowed when writing a special register. Note 3893 // they get dropped in the MRS instruction reading a special register as 3894 // the SYSm field is only 8 bits. 3895 // 3896 // FIXME: the _g and _nzcvqg versions are only allowed if the processor 3897 // includes the DSP extension but that is not checked. 3898 .Case("apsr", 0x800) 3899 .Case("apsr_nzcvq", 0x800) 3900 .Case("apsr_g", 0x400) 3901 .Case("apsr_nzcvqg", 0xc00) 3902 .Case("iapsr", 0x801) 3903 .Case("iapsr_nzcvq", 0x801) 3904 .Case("iapsr_g", 0x401) 3905 .Case("iapsr_nzcvqg", 0xc01) 3906 .Case("eapsr", 0x802) 3907 .Case("eapsr_nzcvq", 0x802) 3908 .Case("eapsr_g", 0x402) 3909 .Case("eapsr_nzcvqg", 0xc02) 3910 .Case("xpsr", 0x803) 3911 .Case("xpsr_nzcvq", 0x803) 3912 .Case("xpsr_g", 0x403) 3913 .Case("xpsr_nzcvqg", 0xc03) 3914 .Case("ipsr", 0x805) 3915 .Case("epsr", 0x806) 3916 .Case("iepsr", 0x807) 3917 .Case("msp", 0x808) 3918 .Case("psp", 0x809) 3919 .Case("primask", 0x810) 3920 .Case("basepri", 0x811) 3921 .Case("basepri_max", 0x812) 3922 .Case("faultmask", 0x813) 3923 .Case("control", 0x814) 3924 .Default(~0U); 3925 3926 if (FlagsVal == ~0U) 3927 return MatchOperand_NoMatch; 3928 3929 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 3930 // basepri, basepri_max and faultmask only valid for V7m. 3931 return MatchOperand_NoMatch; 3932 3933 Parser.Lex(); // Eat identifier token. 3934 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3935 return MatchOperand_Success; 3936 } 3937 3938 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3939 size_t Start = 0, Next = Mask.find('_'); 3940 StringRef Flags = ""; 3941 std::string SpecReg = Mask.slice(Start, Next).lower(); 3942 if (Next != StringRef::npos) 3943 Flags = Mask.slice(Next+1, Mask.size()); 3944 3945 // FlagsVal contains the complete mask: 3946 // 3-0: Mask 3947 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3948 unsigned FlagsVal = 0; 3949 3950 if (SpecReg == "apsr") { 3951 FlagsVal = StringSwitch<unsigned>(Flags) 3952 .Case("nzcvq", 0x8) // same as CPSR_f 3953 .Case("g", 0x4) // same as CPSR_s 3954 .Case("nzcvqg", 0xc) // same as CPSR_fs 3955 .Default(~0U); 3956 3957 if (FlagsVal == ~0U) { 3958 if (!Flags.empty()) 3959 return MatchOperand_NoMatch; 3960 else 3961 FlagsVal = 8; // No flag 3962 } 3963 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 3964 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 3965 if (Flags == "all" || Flags == "") 3966 Flags = "fc"; 3967 for (int i = 0, e = Flags.size(); i != e; ++i) { 3968 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3969 .Case("c", 1) 3970 .Case("x", 2) 3971 .Case("s", 4) 3972 .Case("f", 8) 3973 .Default(~0U); 3974 3975 // If some specific flag is already set, it means that some letter is 3976 // present more than once, this is not acceptable. 3977 if (FlagsVal == ~0U || (FlagsVal & Flag)) 3978 return MatchOperand_NoMatch; 3979 FlagsVal |= Flag; 3980 } 3981 } else // No match for special register. 3982 return MatchOperand_NoMatch; 3983 3984 // Special register without flags is NOT equivalent to "fc" flags. 3985 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 3986 // two lines would enable gas compatibility at the expense of breaking 3987 // round-tripping. 3988 // 3989 // if (!FlagsVal) 3990 // FlagsVal = 0x9; 3991 3992 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3993 if (SpecReg == "spsr") 3994 FlagsVal |= 16; 3995 3996 Parser.Lex(); // Eat identifier token. 3997 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3998 return MatchOperand_Success; 3999 } 4000 4001 ARMAsmParser::OperandMatchResultTy 4002 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, 4003 int High) { 4004 const AsmToken &Tok = Parser.getTok(); 4005 if (Tok.isNot(AsmToken::Identifier)) { 4006 Error(Parser.getTok().getLoc(), Op + " operand expected."); 4007 return MatchOperand_ParseFail; 4008 } 4009 StringRef ShiftName = Tok.getString(); 4010 std::string LowerOp = Op.lower(); 4011 std::string UpperOp = Op.upper(); 4012 if (ShiftName != LowerOp && ShiftName != UpperOp) { 4013 Error(Parser.getTok().getLoc(), Op + " operand expected."); 4014 return MatchOperand_ParseFail; 4015 } 4016 Parser.Lex(); // Eat shift type token. 4017 4018 // There must be a '#' and a shift amount. 4019 if (Parser.getTok().isNot(AsmToken::Hash) && 4020 Parser.getTok().isNot(AsmToken::Dollar)) { 4021 Error(Parser.getTok().getLoc(), "'#' expected"); 4022 return MatchOperand_ParseFail; 4023 } 4024 Parser.Lex(); // Eat hash token. 4025 4026 const MCExpr *ShiftAmount; 4027 SMLoc Loc = Parser.getTok().getLoc(); 4028 SMLoc EndLoc; 4029 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4030 Error(Loc, "illegal expression"); 4031 return MatchOperand_ParseFail; 4032 } 4033 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4034 if (!CE) { 4035 Error(Loc, "constant expression expected"); 4036 return MatchOperand_ParseFail; 4037 } 4038 int Val = CE->getValue(); 4039 if (Val < Low || Val > High) { 4040 Error(Loc, "immediate value out of range"); 4041 return MatchOperand_ParseFail; 4042 } 4043 4044 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); 4045 4046 return MatchOperand_Success; 4047 } 4048 4049 ARMAsmParser::OperandMatchResultTy 4050 ARMAsmParser::parseSetEndImm(OperandVector &Operands) { 4051 const AsmToken &Tok = Parser.getTok(); 4052 SMLoc S = Tok.getLoc(); 4053 if (Tok.isNot(AsmToken::Identifier)) { 4054 Error(S, "'be' or 'le' operand expected"); 4055 return MatchOperand_ParseFail; 4056 } 4057 int Val = StringSwitch<int>(Tok.getString().lower()) 4058 .Case("be", 1) 4059 .Case("le", 0) 4060 .Default(-1); 4061 Parser.Lex(); // Eat the token. 4062 4063 if (Val == -1) { 4064 Error(S, "'be' or 'le' operand expected"); 4065 return MatchOperand_ParseFail; 4066 } 4067 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 4068 getContext()), 4069 S, Tok.getEndLoc())); 4070 return MatchOperand_Success; 4071 } 4072 4073 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 4074 /// instructions. Legal values are: 4075 /// lsl #n 'n' in [0,31] 4076 /// asr #n 'n' in [1,32] 4077 /// n == 32 encoded as n == 0. 4078 ARMAsmParser::OperandMatchResultTy 4079 ARMAsmParser::parseShifterImm(OperandVector &Operands) { 4080 const AsmToken &Tok = Parser.getTok(); 4081 SMLoc S = Tok.getLoc(); 4082 if (Tok.isNot(AsmToken::Identifier)) { 4083 Error(S, "shift operator 'asr' or 'lsl' expected"); 4084 return MatchOperand_ParseFail; 4085 } 4086 StringRef ShiftName = Tok.getString(); 4087 bool isASR; 4088 if (ShiftName == "lsl" || ShiftName == "LSL") 4089 isASR = false; 4090 else if (ShiftName == "asr" || ShiftName == "ASR") 4091 isASR = true; 4092 else { 4093 Error(S, "shift operator 'asr' or 'lsl' expected"); 4094 return MatchOperand_ParseFail; 4095 } 4096 Parser.Lex(); // Eat the operator. 4097 4098 // A '#' and a shift amount. 4099 if (Parser.getTok().isNot(AsmToken::Hash) && 4100 Parser.getTok().isNot(AsmToken::Dollar)) { 4101 Error(Parser.getTok().getLoc(), "'#' expected"); 4102 return MatchOperand_ParseFail; 4103 } 4104 Parser.Lex(); // Eat hash token. 4105 SMLoc ExLoc = Parser.getTok().getLoc(); 4106 4107 const MCExpr *ShiftAmount; 4108 SMLoc EndLoc; 4109 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4110 Error(ExLoc, "malformed shift expression"); 4111 return MatchOperand_ParseFail; 4112 } 4113 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4114 if (!CE) { 4115 Error(ExLoc, "shift amount must be an immediate"); 4116 return MatchOperand_ParseFail; 4117 } 4118 4119 int64_t Val = CE->getValue(); 4120 if (isASR) { 4121 // Shift amount must be in [1,32] 4122 if (Val < 1 || Val > 32) { 4123 Error(ExLoc, "'asr' shift amount must be in range [1,32]"); 4124 return MatchOperand_ParseFail; 4125 } 4126 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 4127 if (isThumb() && Val == 32) { 4128 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); 4129 return MatchOperand_ParseFail; 4130 } 4131 if (Val == 32) Val = 0; 4132 } else { 4133 // Shift amount must be in [1,32] 4134 if (Val < 0 || Val > 31) { 4135 Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); 4136 return MatchOperand_ParseFail; 4137 } 4138 } 4139 4140 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); 4141 4142 return MatchOperand_Success; 4143 } 4144 4145 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 4146 /// of instructions. Legal values are: 4147 /// ror #n 'n' in {0, 8, 16, 24} 4148 ARMAsmParser::OperandMatchResultTy 4149 ARMAsmParser::parseRotImm(OperandVector &Operands) { 4150 const AsmToken &Tok = Parser.getTok(); 4151 SMLoc S = Tok.getLoc(); 4152 if (Tok.isNot(AsmToken::Identifier)) 4153 return MatchOperand_NoMatch; 4154 StringRef ShiftName = Tok.getString(); 4155 if (ShiftName != "ror" && ShiftName != "ROR") 4156 return MatchOperand_NoMatch; 4157 Parser.Lex(); // Eat the operator. 4158 4159 // A '#' and a rotate amount. 4160 if (Parser.getTok().isNot(AsmToken::Hash) && 4161 Parser.getTok().isNot(AsmToken::Dollar)) { 4162 Error(Parser.getTok().getLoc(), "'#' expected"); 4163 return MatchOperand_ParseFail; 4164 } 4165 Parser.Lex(); // Eat hash token. 4166 SMLoc ExLoc = Parser.getTok().getLoc(); 4167 4168 const MCExpr *ShiftAmount; 4169 SMLoc EndLoc; 4170 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4171 Error(ExLoc, "malformed rotate expression"); 4172 return MatchOperand_ParseFail; 4173 } 4174 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4175 if (!CE) { 4176 Error(ExLoc, "rotate amount must be an immediate"); 4177 return MatchOperand_ParseFail; 4178 } 4179 4180 int64_t Val = CE->getValue(); 4181 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 4182 // normally, zero is represented in asm by omitting the rotate operand 4183 // entirely. 4184 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 4185 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); 4186 return MatchOperand_ParseFail; 4187 } 4188 4189 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); 4190 4191 return MatchOperand_Success; 4192 } 4193 4194 ARMAsmParser::OperandMatchResultTy 4195 ARMAsmParser::parseBitfield(OperandVector &Operands) { 4196 SMLoc S = Parser.getTok().getLoc(); 4197 // The bitfield descriptor is really two operands, the LSB and the width. 4198 if (Parser.getTok().isNot(AsmToken::Hash) && 4199 Parser.getTok().isNot(AsmToken::Dollar)) { 4200 Error(Parser.getTok().getLoc(), "'#' expected"); 4201 return MatchOperand_ParseFail; 4202 } 4203 Parser.Lex(); // Eat hash token. 4204 4205 const MCExpr *LSBExpr; 4206 SMLoc E = Parser.getTok().getLoc(); 4207 if (getParser().parseExpression(LSBExpr)) { 4208 Error(E, "malformed immediate expression"); 4209 return MatchOperand_ParseFail; 4210 } 4211 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 4212 if (!CE) { 4213 Error(E, "'lsb' operand must be an immediate"); 4214 return MatchOperand_ParseFail; 4215 } 4216 4217 int64_t LSB = CE->getValue(); 4218 // The LSB must be in the range [0,31] 4219 if (LSB < 0 || LSB > 31) { 4220 Error(E, "'lsb' operand must be in the range [0,31]"); 4221 return MatchOperand_ParseFail; 4222 } 4223 E = Parser.getTok().getLoc(); 4224 4225 // Expect another immediate operand. 4226 if (Parser.getTok().isNot(AsmToken::Comma)) { 4227 Error(Parser.getTok().getLoc(), "too few operands"); 4228 return MatchOperand_ParseFail; 4229 } 4230 Parser.Lex(); // Eat hash token. 4231 if (Parser.getTok().isNot(AsmToken::Hash) && 4232 Parser.getTok().isNot(AsmToken::Dollar)) { 4233 Error(Parser.getTok().getLoc(), "'#' expected"); 4234 return MatchOperand_ParseFail; 4235 } 4236 Parser.Lex(); // Eat hash token. 4237 4238 const MCExpr *WidthExpr; 4239 SMLoc