/external/llvm/lib/Analysis/ |
InstructionSimplify.cpp | 137 if (BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS)) 138 if (Op0->getOpcode() == OpcodeToExpand) { 140 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1), *C = RHS; 196 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS); 200 if (Op0 && Op0->getOpcode() == Opcode) { 201 Value *A = Op0->getOperand(0); 202 Value *B = Op0->getOperand(1); 242 if (Op0 && Op0->getOpcode() == Opcode) [all...] |
/external/llvm/include/llvm/CodeGen/ |
FastISel.h | 193 unsigned Op0, bool Op0IsKill); 200 unsigned Op0, bool Op0IsKill, 209 unsigned Op0, bool Op0IsKill, 218 unsigned Op0, bool Op0IsKill, 227 unsigned Op0, bool Op0IsKill, 238 unsigned Op0, bool Op0IsKill, 265 unsigned Op0, bool Op0IsKill); 271 unsigned Op0, bool Op0IsKill, 278 unsigned Op0, bool Op0IsKill, 286 unsigned Op0, bool Op0IsKill [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
InstCombineMulDivRem.cpp | 121 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); 126 if (Value *V = SimplifyMulInst(Op0, Op1, DL)) 133 return BinaryOperator::CreateNeg(Op0, I.getName()); 174 if (Op0->hasOneUse()) { 177 if (match(Op0, m_Sub(m_Value(Y), m_Value(X)))) 179 else if (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1)))) 193 if (SelectInst *SI = dyn_cast<SelectInst>(Op0)) 197 if (isa<PHINode>(Op0)) 205 if (match(Op0, m_OneUse(m_Add(m_Value(X), m_Constant(C1))))) { 215 if (Value *Op0v = dyn_castNegVal(Op0)) // -X * -Y = X* [all...] |
InstCombineShifts.cpp | 26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); 33 if (isa<Constant>(Op0)) 39 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I)) 314 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, 332 CanEvaluateShifted(Op0, COp1->getZExtValue(), isLeftShift, *this)) { 334 " to eliminate shift:\n IN: " << *Op0 << "\n SH: " << I <<"\n"); 337 GetShiftedValue(Op0, COp1->getZExtValue(), isLeftShift, *this)); 342 uint32_t TypeBits = Op0->getType()->getScalarSizeInBits(); 348 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op0)) 355 if (SelectInst *SI = dyn_cast<SelectInst>(Op0)) [all...] |
InstCombineCompares.cpp | [all...] |
InstCombineAndOrXor.cpp | 801 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); 804 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder); [all...] |
InstCombineAddSub.cpp | [all...] |
InstructionCombining.cpp | 215 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(I.getOperand(0)); 220 if (Op0 && Op0->getOpcode() == Opcode) { 221 Value *A = Op0->getOperand(0); 222 Value *B = Op0->getOperand(1); 233 (!Op0 || (isa<BinaryOperator>(Op0) && Op0->hasNoSignedWrap()))) { 235 // the operands to Op0. 271 if (Op0 && Op0->getOpcode() == Opcode) [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
FastISel.cpp | 402 unsigned Op0 = getRegForValue(I->getOperand(0)); 403 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail. 427 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, 439 ISDOpcode, Op0, Op0IsKill, CF); 457 Op0, Op0IsKill, [all...] |
/external/llvm/lib/Transforms/Scalar/ |
Scalarizer.cpp | 74 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, 76 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name); 85 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, 87 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name); 96 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1, 98 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name); 370 Scatterer Op0 = scatter(&I, I.getOperand(0)); 372 assert(Op0.size() == NumElems && "Mismatched binary operation"); 377 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem], 398 Scatterer Op0 = scatter(&SI, SI.getOperand(0)) [all...] |
CorrelatedValuePropagation.cpp | 164 Value *Op0 = C->getOperand(0); 165 if (isa<Instruction>(Op0) && 166 cast<Instruction>(Op0)->getParent() == C->getParent())
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/external/llvm/include/llvm/IR/ |
GetElementPtrTypeIterator.h | 102 gep_type_begin(Type *Op0, ArrayRef<T> A) { 103 return generic_gep_type_iterator<const T *>::begin(Op0, A.begin()); 108 gep_type_end(Type * /*Op0*/, ArrayRef<T> A) {
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PatternMatch.h | [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelDAGToDAG.cpp | 202 SDValue Op0, Op1; 206 if (!SelectADDRrr(Op, Op0, Op1)) 207 SelectADDRri(Op, Op0, Op1); 211 OutOps.push_back(Op0);
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/external/llvm/lib/Target/SystemZ/ |
SystemZISelDAGToDAG.cpp | 286 // If Op0 is null, then Node is a constant that can be loaded using: 290 // If Op0 is nonnull, then Node can be implemented using: 292 // (Opcode (Opcode Op0 UpperVal) LowerVal) 293 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0, 396 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects 399 SDValue Op0, uint64_t Op1) { 403 changeComponent(AM, IsBase, Op0); 422 SDValue Op0 = N.getOperand(0); 425 unsigned Op0Code = Op0->getOpcode(); 431 return expandAdjDynAlloc(AM, IsBase, Op0); [all...] |
SystemZISelLowering.cpp | 44 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {} 47 SDValue Op0, Op1; 49 // The opcode that should be used to compare Op0 and Op1. [all...] |
/external/llvm/lib/Target/X86/ |
X86FloatingPoint.cpp | [all...] |
/external/llvm/include/llvm/Analysis/ |
InstructionSimplify.h | 134 Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, 141 Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, 148 Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact,
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/external/llvm/lib/ExecutionEngine/ |
ExecutionEngine.cpp | 625 Constant *Op0 = CE->getOperand(0); 629 GenericValue Result = getConstantValue(Op0); 638 GenericValue GV = getConstantValue(Op0); 644 GenericValue GV = getConstantValue(Op0); 650 GenericValue GV = getConstantValue(Op0); 657 GenericValue GV = getConstantValue(Op0); 663 GenericValue GV = getConstantValue(Op0); 668 GenericValue GV = getConstantValue(Op0); 683 GenericValue GV = getConstantValue(Op0); 699 GenericValue GV = getConstantValue(Op0); [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEISelLowering.cpp | 550 SDValue Op0 = N->getOperand(0); 552 unsigned Op0Opcode = Op0->getOpcode(); 570 SDValue Op0Op2 = Op0->getOperand(2); 577 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; 578 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT, 579 Op0->getVTList(), 580 makeArrayRef(Ops, Op0->getNumOperands())); 581 return Op0; 671 SDValue Op0 = N->getOperand(0) [all...] |
MipsFastISel.cpp | 92 unsigned Op0, bool Op0IsKill, uint64_t imm1, 266 Value *Op0 = I->getOperand(0); 279 SrcReg = getRegForValue(Op0);
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/external/llvm/lib/Target/ARM/ |
ARMLoadStoreOptimizer.cpp | [all...] |
ARMFastISel.cpp | 110 unsigned Op0, bool Op0IsKill); 113 unsigned Op0, bool Op0IsKill, 117 unsigned Op0, bool Op0IsKill, 122 unsigned Op0, bool Op0IsKill, 126 unsigned Op0, bool Op0IsKill, 288 unsigned Op0, bool Op0IsKill) { 294 Op0 = constrainOperandRegClass(II, Op0, 1); 297 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); 300 .addReg(Op0, Op0IsKill * RegState::Kill)) [all...] |
/external/llvm/lib/Target/AArch64/Utils/ |
AArch64BaseInfo.cpp | 794 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where the bits 804 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; 810 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 845 uint32_t Op0 = (Bits >> 14) & 0x3; 853 if (Op0 != 3 || (CRn != 11 && CRn != 15)) { 858 assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
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/external/llvm/lib/Target/MSP430/ |
MSP430ISelDAGToDAG.cpp | 290 SDValue Op0, Op1; 294 if (!SelectAddr(Op, Op0, Op1)) 299 OutOps.push_back(Op0);
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