1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the MachineRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16 17 #include "llvm/ADT/BitVector.h" 18 #include "llvm/ADT/IndexedMap.h" 19 #include "llvm/ADT/iterator_range.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBundle.h" 22 #include "llvm/Target/TargetRegisterInfo.h" 23 #include "llvm/Target/TargetSubtargetInfo.h" 24 #include <vector> 25 26 namespace llvm { 27 class PSetIterator; 28 29 /// MachineRegisterInfo - Keep track of information for virtual and physical 30 /// registers, including vreg register classes, use/def chains for registers, 31 /// etc. 32 class MachineRegisterInfo { 33 public: 34 class Delegate { 35 virtual void anchor(); 36 public: 37 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0; 38 39 virtual ~Delegate() {} 40 }; 41 42 private: 43 const MachineFunction *MF; 44 Delegate *TheDelegate; 45 46 /// IsSSA - True when the machine function is in SSA form and virtual 47 /// registers have a single def. 48 bool IsSSA; 49 50 /// TracksLiveness - True while register liveness is being tracked accurately. 51 /// Basic block live-in lists, kill flags, and implicit defs may not be 52 /// accurate when after this flag is cleared. 53 bool TracksLiveness; 54 55 /// True if subregister liveness is tracked. 56 bool TracksSubRegLiveness; 57 58 /// VRegInfo - Information we keep for each virtual register. 59 /// 60 /// Each element in this list contains the register class of the vreg and the 61 /// start of the use/def list for the register. 62 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 63 VirtReg2IndexFunctor> VRegInfo; 64 65 /// RegAllocHints - This vector records register allocation hints for virtual 66 /// registers. For each virtual register, it keeps a register and hint type 67 /// pair making up the allocation hint. Hint type is target specific except 68 /// for the value 0 which means the second value of the pair is the preferred 69 /// register for allocation. For example, if the hint is <0, 1024>, it means 70 /// the allocator should prefer the physical register allocated to the virtual 71 /// register of the hint. 72 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 73 74 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 75 /// physical registers. 76 std::vector<MachineOperand *> PhysRegUseDefLists; 77 78 /// getRegUseDefListHead - Return the head pointer for the register use/def 79 /// list for the specified virtual or physical register. 80 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 81 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 82 return VRegInfo[RegNo].second; 83 return PhysRegUseDefLists[RegNo]; 84 } 85 86 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 87 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 88 return VRegInfo[RegNo].second; 89 return PhysRegUseDefLists[RegNo]; 90 } 91 92 /// Get the next element in the use-def chain. 93 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) { 94 assert(MO && MO->isReg() && "This is not a register operand!"); 95 return MO->Contents.Reg.Next; 96 } 97 98 /// UsedRegUnits - This is a bit vector that is computed and set by the 99 /// register allocator, and must be kept up to date by passes that run after 100 /// register allocation (though most don't modify this). This is used 101 /// so that the code generator knows which callee save registers to save and 102 /// for other target specific uses. 103 /// This vector has bits set for register units that are modified in the 104 /// current function. It doesn't include registers clobbered by function 105 /// calls with register mask operands. 106 BitVector UsedRegUnits; 107 108 /// UsedPhysRegMask - Additional used physregs including aliases. 109 /// This bit vector represents all the registers clobbered by function calls. 110 /// It can model things that UsedRegUnits can't, such as function calls that 111 /// clobber ymm7 but preserve the low half in xmm7. 112 BitVector UsedPhysRegMask; 113 114 /// ReservedRegs - This is a bit vector of reserved registers. The target 115 /// may change its mind about which registers should be reserved. This 116 /// vector is the frozen set of reserved registers when register allocation 117 /// started. 118 BitVector ReservedRegs; 119 120 /// Keep track of the physical registers that are live in to the function. 121 /// Live in values are typically arguments in registers. LiveIn values are 122 /// allowed to have virtual registers associated with them, stored in the 123 /// second element. 124 std::vector<std::pair<unsigned, unsigned> > LiveIns; 125 126 MachineRegisterInfo(const MachineRegisterInfo&) = delete; 127 void operator=(const MachineRegisterInfo&) = delete; 128 public: 129 explicit MachineRegisterInfo(const MachineFunction *MF); 130 131 const TargetRegisterInfo *getTargetRegisterInfo() const { 132 return MF->getSubtarget().getRegisterInfo(); 133 } 134 135 void resetDelegate(Delegate *delegate) { 136 // Ensure another delegate does not take over unless the current 137 // delegate first unattaches itself. If we ever need to multicast 138 // notifications, we will need to change to using a list. 139 assert(TheDelegate == delegate && 140 "Only the current delegate can perform reset!"); 141 TheDelegate = nullptr; 142 } 143 144 void setDelegate(Delegate *delegate) { 145 assert(delegate && !TheDelegate && 146 "Attempted to set delegate to null, or to change it without " 147 "first resetting it!"); 148 149 TheDelegate = delegate; 150 } 151 152 //===--------------------------------------------------------------------===// 153 // Function State 154 //===--------------------------------------------------------------------===// 155 156 // isSSA - Returns true when the machine function is in SSA form. Early 157 // passes require the machine function to be in SSA form where every virtual 158 // register has a single defining instruction. 159 // 160 // The TwoAddressInstructionPass and PHIElimination passes take the machine 161 // function out of SSA form when they introduce multiple defs per virtual 162 // register. 163 bool isSSA() const { return IsSSA; } 164 165 // leaveSSA - Indicates that the machine function is no longer in SSA form. 166 void leaveSSA() { IsSSA = false; } 167 168 /// tracksLiveness - Returns true when tracking register liveness accurately. 169 /// 170 /// While this flag is true, register liveness information in basic block 171 /// live-in lists and machine instruction operands is accurate. This means it 172 /// can be used to change the code in ways that affect the values in 173 /// registers, for example by the register scavenger. 174 /// 175 /// When this flag is false, liveness is no longer reliable. 176 bool tracksLiveness() const { return TracksLiveness; } 177 178 /// invalidateLiveness - Indicates that register liveness is no longer being 179 /// tracked accurately. 180 /// 181 /// This should be called by late passes that invalidate the liveness 182 /// information. 183 void invalidateLiveness() { TracksLiveness = false; } 184 185 /// Returns true if liveness for register class @p RC should be tracked at 186 /// the subregister level. 187 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const { 188 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs; 189 } 190 bool shouldTrackSubRegLiveness(unsigned VReg) const { 191 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg"); 192 return shouldTrackSubRegLiveness(*getRegClass(VReg)); 193 } 194 bool subRegLivenessEnabled() const { 195 return TracksSubRegLiveness; 196 } 197 198 void enableSubRegLiveness(bool Enable = true) { 199 TracksSubRegLiveness = Enable; 200 } 201 202 //===--------------------------------------------------------------------===// 203 // Register Info 204 //===--------------------------------------------------------------------===// 205 206 // Strictly for use by MachineInstr.cpp. 207 void addRegOperandToUseList(MachineOperand *MO); 208 209 // Strictly for use by MachineInstr.cpp. 210 void removeRegOperandFromUseList(MachineOperand *MO); 211 212 // Strictly for use by MachineInstr.cpp. 213 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps); 214 215 /// Verify the sanity of the use list for Reg. 216 void verifyUseList(unsigned Reg) const; 217 218 /// Verify the use list of all registers. 219 void verifyUseLists() const; 220 221 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 222 /// and uses of a register within the MachineFunction that corresponds to this 223 /// MachineRegisterInfo object. 224 template<bool Uses, bool Defs, bool SkipDebug, 225 bool ByOperand, bool ByInstr, bool ByBundle> 226 class defusechain_iterator; 227 template<bool Uses, bool Defs, bool SkipDebug, 228 bool ByOperand, bool ByInstr, bool ByBundle> 229 class defusechain_instr_iterator; 230 231 // Make it a friend so it can access getNextOperandForReg(). 232 template<bool, bool, bool, bool, bool, bool> 233 friend class defusechain_iterator; 234 template<bool, bool, bool, bool, bool, bool> 235 friend class defusechain_instr_iterator; 236 237 238 239 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 240 /// register. 241 typedef defusechain_iterator<true,true,false,true,false,false> 242 reg_iterator; 243 reg_iterator reg_begin(unsigned RegNo) const { 244 return reg_iterator(getRegUseDefListHead(RegNo)); 245 } 246 static reg_iterator reg_end() { return reg_iterator(nullptr); } 247 248 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const { 249 return iterator_range<reg_iterator>(reg_begin(Reg), reg_end()); 250 } 251 252 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses 253 /// of the specified register, stepping by MachineInstr. 254 typedef defusechain_instr_iterator<true,true,false,false,true,false> 255 reg_instr_iterator; 256 reg_instr_iterator reg_instr_begin(unsigned RegNo) const { 257 return reg_instr_iterator(getRegUseDefListHead(RegNo)); 258 } 259 static reg_instr_iterator reg_instr_end() { 260 return reg_instr_iterator(nullptr); 261 } 262 263 inline iterator_range<reg_instr_iterator> 264 reg_instructions(unsigned Reg) const { 265 return iterator_range<reg_instr_iterator>(reg_instr_begin(Reg), 266 reg_instr_end()); 267 } 268 269 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses 270 /// of the specified register, stepping by bundle. 271 typedef defusechain_instr_iterator<true,true,false,false,false,true> 272 reg_bundle_iterator; 273 reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const { 274 return reg_bundle_iterator(getRegUseDefListHead(RegNo)); 275 } 276 static reg_bundle_iterator reg_bundle_end() { 277 return reg_bundle_iterator(nullptr); 278 } 279 280 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const { 281 return iterator_range<reg_bundle_iterator>(reg_bundle_begin(Reg), 282 reg_bundle_end()); 283 } 284 285 /// reg_empty - Return true if there are no instructions using or defining the 286 /// specified register (it may be live-in). 287 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 288 289 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 290 /// of the specified register, skipping those marked as Debug. 291 typedef defusechain_iterator<true,true,true,true,false,false> 292 reg_nodbg_iterator; 293 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 294 return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 295 } 296 static reg_nodbg_iterator reg_nodbg_end() { 297 return reg_nodbg_iterator(nullptr); 298 } 299 300 inline iterator_range<reg_nodbg_iterator> 301 reg_nodbg_operands(unsigned Reg) const { 302 return iterator_range<reg_nodbg_iterator>(reg_nodbg_begin(Reg), 303 reg_nodbg_end()); 304 } 305 306 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk 307 /// all defs and uses of the specified register, stepping by MachineInstr, 308 /// skipping those marked as Debug. 309 typedef defusechain_instr_iterator<true,true,true,false,true,false> 310 reg_instr_nodbg_iterator; 311 reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const { 312 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); 313 } 314 static reg_instr_nodbg_iterator reg_instr_nodbg_end() { 315 return reg_instr_nodbg_iterator(nullptr); 316 } 317 318 inline iterator_range<reg_instr_nodbg_iterator> 319 reg_nodbg_instructions(unsigned Reg) const { 320 return iterator_range<reg_instr_nodbg_iterator>(reg_instr_nodbg_begin(Reg), 321 reg_instr_nodbg_end()); 322 } 323 324 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk 325 /// all defs and uses of the specified register, stepping by bundle, 326 /// skipping those marked as Debug. 327 typedef defusechain_instr_iterator<true,true,true,false,false,true> 328 reg_bundle_nodbg_iterator; 329 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const { 330 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); 331 } 332 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() { 333 return reg_bundle_nodbg_iterator(nullptr); 334 } 335 336 inline iterator_range<reg_bundle_nodbg_iterator> 337 reg_nodbg_bundles(unsigned Reg) const { 338 return iterator_range<reg_bundle_nodbg_iterator>(reg_bundle_nodbg_begin(Reg), 339 reg_bundle_nodbg_end()); 340 } 341 342 /// reg_nodbg_empty - Return true if the only instructions using or defining 343 /// Reg are Debug instructions. 344 bool reg_nodbg_empty(unsigned RegNo) const { 345 return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 346 } 347 348 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 349 typedef defusechain_iterator<false,true,false,true,false,false> 350 def_iterator; 351 def_iterator def_begin(unsigned RegNo) const { 352 return def_iterator(getRegUseDefListHead(RegNo)); 353 } 354 static def_iterator def_end() { return def_iterator(nullptr); } 355 356 inline iterator_range<def_iterator> def_operands(unsigned Reg) const { 357 return iterator_range<def_iterator>(def_begin(Reg), def_end()); 358 } 359 360 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the 361 /// specified register, stepping by MachineInst. 362 typedef defusechain_instr_iterator<false,true,false,false,true,false> 363 def_instr_iterator; 364 def_instr_iterator def_instr_begin(unsigned RegNo) const { 365 return def_instr_iterator(getRegUseDefListHead(RegNo)); 366 } 367 static def_instr_iterator def_instr_end() { 368 return def_instr_iterator(nullptr); 369 } 370 371 inline iterator_range<def_instr_iterator> 372 def_instructions(unsigned Reg) const { 373 return iterator_range<def_instr_iterator>(def_instr_begin(Reg), 374 def_instr_end()); 375 } 376 377 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the 378 /// specified register, stepping by bundle. 379 typedef defusechain_instr_iterator<false,true,false,false,false,true> 380 def_bundle_iterator; 381 def_bundle_iterator def_bundle_begin(unsigned RegNo) const { 382 return def_bundle_iterator(getRegUseDefListHead(RegNo)); 383 } 384 static def_bundle_iterator def_bundle_end() { 385 return def_bundle_iterator(nullptr); 386 } 387 388 inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const { 389 return iterator_range<def_bundle_iterator>(def_bundle_begin(Reg), 390 def_bundle_end()); 391 } 392 393 /// def_empty - Return true if there are no instructions defining the 394 /// specified register (it may be live-in). 395 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 396 397 /// hasOneDef - Return true if there is exactly one instruction defining the 398 /// specified register. 399 bool hasOneDef(unsigned RegNo) const { 400 def_iterator DI = def_begin(RegNo); 401 if (DI == def_end()) 402 return false; 403 return ++DI == def_end(); 404 } 405 406 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 407 typedef defusechain_iterator<true,false,false,true,false,false> 408 use_iterator; 409 use_iterator use_begin(unsigned RegNo) const { 410 return use_iterator(getRegUseDefListHead(RegNo)); 411 } 412 static use_iterator use_end() { return use_iterator(nullptr); } 413 414 inline iterator_range<use_iterator> use_operands(unsigned Reg) const { 415 return iterator_range<use_iterator>(use_begin(Reg), use_end()); 416 } 417 418 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the 419 /// specified register, stepping by MachineInstr. 420 typedef defusechain_instr_iterator<true,false,false,false,true,false> 421 use_instr_iterator; 422 use_instr_iterator use_instr_begin(unsigned RegNo) const { 423 return use_instr_iterator(getRegUseDefListHead(RegNo)); 424 } 425 static use_instr_iterator use_instr_end() { 426 return use_instr_iterator(nullptr); 427 } 428 429 inline iterator_range<use_instr_iterator> 430 use_instructions(unsigned Reg) const { 431 return iterator_range<use_instr_iterator>(use_instr_begin(Reg), 432 use_instr_end()); 433 } 434 435 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the 436 /// specified register, stepping by bundle. 437 typedef defusechain_instr_iterator<true,false,false,false,false,true> 438 use_bundle_iterator; 439 use_bundle_iterator use_bundle_begin(unsigned RegNo) const { 440 return use_bundle_iterator(getRegUseDefListHead(RegNo)); 441 } 442 static use_bundle_iterator use_bundle_end() { 443 return use_bundle_iterator(nullptr); 444 } 445 446 inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const { 447 return iterator_range<use_bundle_iterator>(use_bundle_begin(Reg), 448 use_bundle_end()); 449 } 450 451 /// use_empty - Return true if there are no instructions using the specified 452 /// register. 453 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 454 455 /// hasOneUse - Return true if there is exactly one instruction using the 456 /// specified register. 457 bool hasOneUse(unsigned RegNo) const { 458 use_iterator UI = use_begin(RegNo); 459 if (UI == use_end()) 460 return false; 461 return ++UI == use_end(); 462 } 463 464 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 465 /// specified register, skipping those marked as Debug. 466 typedef defusechain_iterator<true,false,true,true,false,false> 467 use_nodbg_iterator; 468 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 469 return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 470 } 471 static use_nodbg_iterator use_nodbg_end() { 472 return use_nodbg_iterator(nullptr); 473 } 474 475 inline iterator_range<use_nodbg_iterator> 476 use_nodbg_operands(unsigned Reg) const { 477 return iterator_range<use_nodbg_iterator>(use_nodbg_begin(Reg), 478 use_nodbg_end()); 479 } 480 481 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk 482 /// all uses of the specified register, stepping by MachineInstr, skipping 483 /// those marked as Debug. 484 typedef defusechain_instr_iterator<true,false,true,false,true,false> 485 use_instr_nodbg_iterator; 486 use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const { 487 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); 488 } 489 static use_instr_nodbg_iterator use_instr_nodbg_end() { 490 return use_instr_nodbg_iterator(nullptr); 491 } 492 493 inline iterator_range<use_instr_nodbg_iterator> 494 use_nodbg_instructions(unsigned Reg) const { 495 return iterator_range<use_instr_nodbg_iterator>(use_instr_nodbg_begin(Reg), 496 use_instr_nodbg_end()); 497 } 498 499 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk 500 /// all uses of the specified register, stepping by bundle, skipping 501 /// those marked as Debug. 502 typedef defusechain_instr_iterator<true,false,true,false,false,true> 503 use_bundle_nodbg_iterator; 504 use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const { 505 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); 506 } 507 static use_bundle_nodbg_iterator use_bundle_nodbg_end() { 508 return use_bundle_nodbg_iterator(nullptr); 509 } 510 511 inline iterator_range<use_bundle_nodbg_iterator> 512 use_nodbg_bundles(unsigned Reg) const { 513 return iterator_range<use_bundle_nodbg_iterator>(use_bundle_nodbg_begin(Reg), 514 use_bundle_nodbg_end()); 515 } 516 517 /// use_nodbg_empty - Return true if there are no non-Debug instructions 518 /// using the specified register. 519 bool use_nodbg_empty(unsigned RegNo) const { 520 return use_nodbg_begin(RegNo) == use_nodbg_end(); 521 } 522 523 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 524 /// instruction using the specified register. 525 bool hasOneNonDBGUse(unsigned RegNo) const; 526 527 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 528 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 529 /// except that it also changes any definitions of the register as well. 530 /// 531 /// Note that it is usually necessary to first constrain ToReg's register 532 /// class to match the FromReg constraints using: 533 /// 534 /// constrainRegClass(ToReg, getRegClass(FromReg)) 535 /// 536 /// That function will return NULL if the virtual registers have incompatible 537 /// constraints. 538 /// 539 /// Note that if ToReg is a physical register the function will replace and 540 /// apply sub registers to ToReg in order to obtain a final/proper physical 541 /// register. 542 void replaceRegWith(unsigned FromReg, unsigned ToReg); 543 544 /// getVRegDef - Return the machine instr that defines the specified virtual 545 /// register or null if none is found. This assumes that the code is in SSA 546 /// form, so there should only be one definition. 547 MachineInstr *getVRegDef(unsigned Reg) const; 548 549 /// getUniqueVRegDef - Return the unique machine instr that defines the 550 /// specified virtual register or null if none is found. If there are 551 /// multiple definitions or no definition, return null. 552 MachineInstr *getUniqueVRegDef(unsigned Reg) const; 553 554 /// clearKillFlags - Iterate over all the uses of the given register and 555 /// clear the kill flag from the MachineOperand. This function is used by 556 /// optimization passes which extend register lifetimes and need only 557 /// preserve conservative kill flag information. 558 void clearKillFlags(unsigned Reg) const; 559 560 #ifndef NDEBUG 561 void dumpUses(unsigned RegNo) const; 562 #endif 563 564 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant 565 /// throughout the function. It is safe to move instructions that read such 566 /// a physreg. 567 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const; 568 569 /// Get an iterator over the pressure sets affected by the given physical or 570 /// virtual register. If RegUnit is physical, it must be a register unit (from 571 /// MCRegUnitIterator). 572 PSetIterator getPressureSets(unsigned RegUnit) const; 573 574 //===--------------------------------------------------------------------===// 575 // Virtual Register Info 576 //===--------------------------------------------------------------------===// 577 578 /// getRegClass - Return the register class of the specified virtual register. 579 /// 580 const TargetRegisterClass *getRegClass(unsigned Reg) const { 581 return VRegInfo[Reg].first; 582 } 583 584 /// setRegClass - Set the register class of the specified virtual register. 585 /// 586 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 587 588 /// constrainRegClass - Constrain the register class of the specified virtual 589 /// register to be a common subclass of RC and the current register class, 590 /// but only if the new class has at least MinNumRegs registers. Return the 591 /// new register class, or NULL if no such class exists. 592 /// This should only be used when the constraint is known to be trivial, like 593 /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 594 /// 595 const TargetRegisterClass *constrainRegClass(unsigned Reg, 596 const TargetRegisterClass *RC, 597 unsigned MinNumRegs = 0); 598 599 /// recomputeRegClass - Try to find a legal super-class of Reg's register 600 /// class that still satisfies the constraints from the instructions using 601 /// Reg. Returns true if Reg was upgraded. 602 /// 603 /// This method can be used after constraints have been removed from a 604 /// virtual register, for example after removing instructions or splitting 605 /// the live range. 606 /// 607 bool recomputeRegClass(unsigned Reg); 608 609 /// createVirtualRegister - Create and return a new virtual register in the 610 /// function with the specified register class. 611 /// 612 unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 613 614 /// getNumVirtRegs - Return the number of virtual registers created. 615 /// 616 unsigned getNumVirtRegs() const { return VRegInfo.size(); } 617 618 /// clearVirtRegs - Remove all virtual registers (after physreg assignment). 619 void clearVirtRegs(); 620 621 /// setRegAllocationHint - Specify a register allocation hint for the 622 /// specified virtual register. 623 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) { 624 assert(TargetRegisterInfo::isVirtualRegister(VReg)); 625 RegAllocHints[VReg].first = Type; 626 RegAllocHints[VReg].second = PrefReg; 627 } 628 629 /// getRegAllocationHint - Return the register allocation hint for the 630 /// specified virtual register. 631 std::pair<unsigned, unsigned> 632 getRegAllocationHint(unsigned VReg) const { 633 assert(TargetRegisterInfo::isVirtualRegister(VReg)); 634 return RegAllocHints[VReg]; 635 } 636 637 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 638 /// standard simple hint (Type == 0) is not set. 639 unsigned getSimpleHint(unsigned VReg) const { 640 assert(TargetRegisterInfo::isVirtualRegister(VReg)); 641 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg); 642 return Hint.first ? 0 : Hint.second; 643 } 644 645 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the 646 /// specified register as undefined which causes the DBG_VALUE to be 647 /// deleted during LiveDebugVariables analysis. 648 void markUsesInDebugValueAsUndef(unsigned Reg) const; 649 650 //===--------------------------------------------------------------------===// 651 // Physical Register Use Info 652 //===--------------------------------------------------------------------===// 653 654 /// isPhysRegUsed - Return true if the specified register is used in this 655 /// function. Also check for clobbered aliases and registers clobbered by 656 /// function calls with register mask operands. 657 /// 658 /// This only works after register allocation. It is primarily used by 659 /// PrologEpilogInserter to determine which callee-saved registers need 660 /// spilling. 661 bool isPhysRegUsed(unsigned Reg) const { 662 if (UsedPhysRegMask.test(Reg)) 663 return true; 664 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo()); 665 Units.isValid(); ++Units) 666 if (UsedRegUnits.test(*Units)) 667 return true; 668 return false; 669 } 670 671 /// Mark the specified register unit as used in this function. 672 /// This should only be called during and after register allocation. 673 void setRegUnitUsed(unsigned RegUnit) { 674 UsedRegUnits.set(RegUnit); 675 } 676 677 /// setPhysRegUsed - Mark the specified register used in this function. 678 /// This should only be called during and after register allocation. 679 void setPhysRegUsed(unsigned Reg) { 680 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo()); 681 Units.isValid(); ++Units) 682 UsedRegUnits.set(*Units); 683 } 684 685 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. 686 /// This corresponds to the bit mask attached to register mask operands. 687 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { 688 UsedPhysRegMask.setBitsNotInMask(RegMask); 689 } 690 691 /// setPhysRegUnused - Mark the specified register unused in this function. 692 /// This should only be called during and after register allocation. 693 void setPhysRegUnused(unsigned Reg) { 694 UsedPhysRegMask.reset(Reg); 695 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo()); 696 Units.isValid(); ++Units) 697 UsedRegUnits.reset(*Units); 698 } 699 700 701 //===--------------------------------------------------------------------===// 702 // Reserved Register Info 703 //===--------------------------------------------------------------------===// 704 // 705 // The set of reserved registers must be invariant during register 706 // allocation. For example, the target cannot suddenly decide it needs a 707 // frame pointer when the register allocator has already used the frame 708 // pointer register for something else. 709 // 710 // These methods can be used by target hooks like hasFP() to avoid changing 711 // the reserved register set during register allocation. 712 713 /// freezeReservedRegs - Called by the register allocator to freeze the set 714 /// of reserved registers before allocation begins. 715 void freezeReservedRegs(const MachineFunction&); 716 717 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called 718 /// to ensure the set of reserved registers stays constant. 719 bool reservedRegsFrozen() const { 720 return !ReservedRegs.empty(); 721 } 722 723 /// canReserveReg - Returns true if PhysReg can be used as a reserved 724 /// register. Any register can be reserved before freezeReservedRegs() is 725 /// called. 726 bool canReserveReg(unsigned PhysReg) const { 727 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 728 } 729 730 /// getReservedRegs - Returns a reference to the frozen set of reserved 731 /// registers. This method should always be preferred to calling 732 /// TRI::getReservedRegs() when possible. 733 const BitVector &getReservedRegs() const { 734 assert(reservedRegsFrozen() && 735 "Reserved registers haven't been frozen yet. " 736 "Use TRI::getReservedRegs()."); 737 return ReservedRegs; 738 } 739 740 /// isReserved - Returns true when PhysReg is a reserved register. 741 /// 742 /// Reserved registers may belong to an allocatable register class, but the 743 /// target has explicitly requested that they are not used. 744 /// 745 bool isReserved(unsigned PhysReg) const { 746 return getReservedRegs().test(PhysReg); 747 } 748 749 /// isAllocatable - Returns true when PhysReg belongs to an allocatable 750 /// register class and it hasn't been reserved. 751 /// 752 /// Allocatable registers may show up in the allocation order of some virtual 753 /// register, so a register allocator needs to track its liveness and 754 /// availability. 755 bool isAllocatable(unsigned PhysReg) const { 756 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) && 757 !isReserved(PhysReg); 758 } 759 760 //===--------------------------------------------------------------------===// 761 // LiveIn Management 762 //===--------------------------------------------------------------------===// 763 764 /// addLiveIn - Add the specified register as a live-in. Note that it 765 /// is an error to add the same register to the same set more than once. 766 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 767 LiveIns.push_back(std::make_pair(Reg, vreg)); 768 } 769 770 // Iteration support for the live-ins set. It's kept in sorted order 771 // by register number. 772 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 773 livein_iterator; 774 livein_iterator livein_begin() const { return LiveIns.begin(); } 775 livein_iterator livein_end() const { return LiveIns.end(); } 776 bool livein_empty() const { return LiveIns.empty(); } 777 778 bool isLiveIn(unsigned Reg) const; 779 780 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 781 /// corresponding live-in physical register. 782 unsigned getLiveInPhysReg(unsigned VReg) const; 783 784 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 785 /// corresponding live-in physical register. 786 unsigned getLiveInVirtReg(unsigned PReg) const; 787 788 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 789 /// into the given entry block. 790 void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 791 const TargetRegisterInfo &TRI, 792 const TargetInstrInfo &TII); 793 794 /// Returns a mask covering all bits that can appear in lane masks of 795 /// subregisters of the virtual register @p Reg. 796 unsigned getMaxLaneMaskForVReg(unsigned Reg) const; 797 798 /// defusechain_iterator - This class provides iterator support for machine 799 /// operands in the function that use or define a specific register. If 800 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 801 /// returns defs. If neither are true then you are silly and it always 802 /// returns end(). If SkipDebug is true it skips uses marked Debug 803 /// when incrementing. 804 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug, 805 bool ByOperand, bool ByInstr, bool ByBundle> 806 class defusechain_iterator 807 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 808 MachineOperand *Op; 809 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 810 // If the first node isn't one we're interested in, advance to one that 811 // we are interested in. 812 if (op) { 813 if ((!ReturnUses && op->isUse()) || 814 (!ReturnDefs && op->isDef()) || 815 (SkipDebug && op->isDebug())) 816 advance(); 817 } 818 } 819 friend class MachineRegisterInfo; 820 821 void advance() { 822 assert(Op && "Cannot increment end iterator!"); 823 Op = getNextOperandForReg(Op); 824 825 // All defs come before the uses, so stop def_iterator early. 826 if (!ReturnUses) { 827 if (Op) { 828 if (Op->isUse()) 829 Op = nullptr; 830 else 831 assert(!Op->isDebug() && "Can't have debug defs"); 832 } 833 } else { 834 // If this is an operand we don't care about, skip it. 835 while (Op && ((!ReturnDefs && Op->isDef()) || 836 (SkipDebug && Op->isDebug()))) 837 Op = getNextOperandForReg(Op); 838 } 839 } 840 public: 841 typedef std::iterator<std::forward_iterator_tag, 842 MachineInstr, ptrdiff_t>::reference reference; 843 typedef std::iterator<std::forward_iterator_tag, 844 MachineInstr, ptrdiff_t>::pointer pointer; 845 846 defusechain_iterator() : Op(nullptr) {} 847 848 bool operator==(const defusechain_iterator &x) const { 849 return Op == x.Op; 850 } 851 bool operator!=(const defusechain_iterator &x) const { 852 return !operator==(x); 853 } 854 855 /// atEnd - return true if this iterator is equal to reg_end() on the value. 856 bool atEnd() const { return Op == nullptr; } 857 858 // Iterator traversal: forward iteration only 859 defusechain_iterator &operator++() { // Preincrement 860 assert(Op && "Cannot increment end iterator!"); 861 if (ByOperand) 862 advance(); 863 else if (ByInstr) { 864 MachineInstr *P = Op->getParent(); 865 do { 866 advance(); 867 } while (Op && Op->getParent() == P); 868 } else if (ByBundle) { 869 MachineInstr *P = getBundleStart(Op->getParent()); 870 do { 871 advance(); 872 } while (Op && getBundleStart(Op->getParent()) == P); 873 } 874 875 return *this; 876 } 877 defusechain_iterator operator++(int) { // Postincrement 878 defusechain_iterator tmp = *this; ++*this; return tmp; 879 } 880 881 /// getOperandNo - Return the operand # of this MachineOperand in its 882 /// MachineInstr. 883 unsigned getOperandNo() const { 884 assert(Op && "Cannot dereference end iterator!"); 885 return Op - &Op->getParent()->getOperand(0); 886 } 887 888 // Retrieve a reference to the current operand. 889 MachineOperand &operator*() const { 890 assert(Op && "Cannot dereference end iterator!"); 891 return *Op; 892 } 893 894 MachineOperand *operator->() const { 895 assert(Op && "Cannot dereference end iterator!"); 896 return Op; 897 } 898 }; 899 900 /// defusechain_iterator - This class provides iterator support for machine 901 /// operands in the function that use or define a specific register. If 902 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 903 /// returns defs. If neither are true then you are silly and it always 904 /// returns end(). If SkipDebug is true it skips uses marked Debug 905 /// when incrementing. 906 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug, 907 bool ByOperand, bool ByInstr, bool ByBundle> 908 class defusechain_instr_iterator 909 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 910 MachineOperand *Op; 911 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) { 912 // If the first node isn't one we're interested in, advance to one that 913 // we are interested in. 914 if (op) { 915 if ((!ReturnUses && op->isUse()) || 916 (!ReturnDefs && op->isDef()) || 917 (SkipDebug && op->isDebug())) 918 advance(); 919 } 920 } 921 friend class MachineRegisterInfo; 922 923 void advance() { 924 assert(Op && "Cannot increment end iterator!"); 925 Op = getNextOperandForReg(Op); 926 927 // All defs come before the uses, so stop def_iterator early. 928 if (!ReturnUses) { 929 if (Op) { 930 if (Op->isUse()) 931 Op = nullptr; 932 else 933 assert(!Op->isDebug() && "Can't have debug defs"); 934 } 935 } else { 936 // If this is an operand we don't care about, skip it. 937 while (Op && ((!ReturnDefs && Op->isDef()) || 938 (SkipDebug && Op->isDebug()))) 939 Op = getNextOperandForReg(Op); 940 } 941 } 942 public: 943 typedef std::iterator<std::forward_iterator_tag, 944 MachineInstr, ptrdiff_t>::reference reference; 945 typedef std::iterator<std::forward_iterator_tag, 946 MachineInstr, ptrdiff_t>::pointer pointer; 947 948 defusechain_instr_iterator() : Op(nullptr) {} 949 950 bool operator==(const defusechain_instr_iterator &x) const { 951 return Op == x.Op; 952 } 953 bool operator!=(const defusechain_instr_iterator &x) const { 954 return !operator==(x); 955 } 956 957 /// atEnd - return true if this iterator is equal to reg_end() on the value. 958 bool atEnd() const { return Op == nullptr; } 959 960 // Iterator traversal: forward iteration only 961 defusechain_instr_iterator &operator++() { // Preincrement 962 assert(Op && "Cannot increment end iterator!"); 963 if (ByOperand) 964 advance(); 965 else if (ByInstr) { 966 MachineInstr *P = Op->getParent(); 967 do { 968 advance(); 969 } while (Op && Op->getParent() == P); 970 } else if (ByBundle) { 971 MachineInstr *P = getBundleStart(Op->getParent()); 972 do { 973 advance(); 974 } while (Op && getBundleStart(Op->getParent()) == P); 975 } 976 977 return *this; 978 } 979 defusechain_instr_iterator operator++(int) { // Postincrement 980 defusechain_instr_iterator tmp = *this; ++*this; return tmp; 981 } 982 983 // Retrieve a reference to the current operand. 984 MachineInstr &operator*() const { 985 assert(Op && "Cannot dereference end iterator!"); 986 if (ByBundle) return *(getBundleStart(Op->getParent())); 987 return *Op->getParent(); 988 } 989 990 MachineInstr *operator->() const { 991 assert(Op && "Cannot dereference end iterator!"); 992 if (ByBundle) return getBundleStart(Op->getParent()); 993 return Op->getParent(); 994 } 995 }; 996 }; 997 998 /// Iterate over the pressure sets affected by the given physical or virtual 999 /// register. If Reg is physical, it must be a register unit (from 1000 /// MCRegUnitIterator). 1001 class PSetIterator { 1002 const int *PSet; 1003 unsigned Weight; 1004 public: 1005 PSetIterator(): PSet(nullptr), Weight(0) {} 1006 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { 1007 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); 1008 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) { 1009 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); 1010 PSet = TRI->getRegClassPressureSets(RC); 1011 Weight = TRI->getRegClassWeight(RC).RegWeight; 1012 } 1013 else { 1014 PSet = TRI->getRegUnitPressureSets(RegUnit); 1015 Weight = TRI->getRegUnitWeight(RegUnit); 1016 } 1017 if (*PSet == -1) 1018 PSet = nullptr; 1019 } 1020 bool isValid() const { return PSet; } 1021 1022 unsigned getWeight() const { return Weight; } 1023 1024 unsigned operator*() const { return *PSet; } 1025 1026 void operator++() { 1027 assert(isValid() && "Invalid PSetIterator."); 1028 ++PSet; 1029 if (*PSet == -1) 1030 PSet = nullptr; 1031 } 1032 }; 1033 1034 inline PSetIterator MachineRegisterInfo:: 1035 getPressureSets(unsigned RegUnit) const { 1036 return PSetIterator(RegUnit, this); 1037 } 1038 1039 } // End llvm namespace 1040 1041 #endif 1042