| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.td | 158 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
[all...] |
| AArch64FastISel.cpp | [all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| thumb2.txt | 105 # CHECK: ands r3, r12, #15
118 # CHECK: ands.w r2, r1, r7, lsl #1
119 # CHECK: ands.w r4, r5, r2, lsr #20
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64.cc | 96 case ANDS: // Fall through.
114 case ANDS: // Fall through.
[all...] |
| assembler-arm64.h | [all...] |
| macro-assembler-arm64.h | 143 inline void Ands(const Register& rd,
[all...] |
| simulator-arm64.cc | [all...] |
| code-stubs-arm64.cc | [all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 134 "ands", "!0C, !1C", 2, kFixupNone),
[all...] |
| /external/antlr/antlr-3.4/runtime/C/src/ |
| antlr3collections.c | [all...] |
| /external/valgrind/VEX/priv/ |
| guest_arm64_toIR.c | [all...] |
| host_arm64_defs.c | [all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.h | 606 void Ands(const Register& rd,
[all...] |
| assembler-a64.h | [all...] |
| simulator-a64.cc | 1008 case ANDS: update_flags = true; VIXL_FALLTHROUGH();
[all...] |
| /external/clang/lib/CodeGen/ |
| CGExprScalar.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/hyphenation-patterns/nb/ |
| hyph-nb.pat.txt | 2484 4ands
[all...] |
| /external/hyphenation-patterns/nn/ |
| hyph-nn.pat.txt | 2484 4ands
[all...] |
| /art/compiler/utils/ |
| assembler_thumb_test_expected.cc.inc | 33 " 28: 4008 ands r0, r1\n",
[all...] |
| /external/lldb/source/Plugins/Instruction/ARM/ |
| EmulateInstructionARM.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
